Lecture-16

OPCODE FETCH Machine Cycle:

Figure shows the 8085A instruction fetch timing diagram. The
instruction fetch cycle requires either four or six clock periods (T-
states). The other machine cycles that follow OFMC will need three
clock cycles.
The purpose of an OFMC is to read the contents of a memory
location containing the opcode addressed by the program counter
and to place it in the instruction register (IR).
In the beginning of state T1, the 8085A puts a low on the IO/M
line of the system bus indicating a memory operation. The 8085A
sets S1=1 and S0=1 on the system bus, indicating the memory fetch
operation. This status information remains available for the duration
of the machine cycle. During T1 state, the 16-bit address A15-A0 of the
memory location containing the opcode is obtained from the program
counter (PC) and placed on the address and address/data latches.
The higher order 8-bits of the address appear on the address bus A8-
A15 remains constants until the end of the state T3. During T4 state the
data on the address bus is unspecified. The low order 8-bits of the
address are placed on the address/data bus, AD7-AD0 at the
beginning of T1. This data however remains valid only until the
beginning of state T2 at which time the address/data bus is floated
(tri-stated) because this is time multiplexed bus and used as the data
bus during T2 and T3 states. Therefore address latch enable (ALE)
signal issued by the 𝜇𝑝 during T1 is used to latch this lower order
address in some external latch 74LS373 on its falling edge. The 16-
bit address selects a particular memory location.
 During state T2, at the beginning, the RD signal goes low
indicating read operation and the opcode to be fetched is placed on
the data bus, AD7-AD0 by the addressed memory location. The
contents of (PC) is incremented be 1 during this state as during T1
state the (PC) has sent the address to address bus. The accessed
memory should be fast enough to output its data before RD goes
high. Slower memories can gain more time by pulling the READY
signal of 8085A LOW. This will introduce an integral number of TWAIT
states between T2 and T3 as long as READY is low. On the rising
edge of the RD control signal in T3 state, the opcode obtained from
the memory is transferred to the microprocessor instruction register.
During state T4, the 8085A decodes the instruction and
determines whether to enter state T5 or to enter T1 state of the next
machine cycle. From the operation code, the 𝜇𝑝 determines what
other machine cycles, if any, must be executed to complete the
instruction cycle. State T5 and T6 when entered, are used for internal
𝜇𝑝 operations necessitated by the instruction.
The micro RTL flow for 4-states OFMC is shown below.
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (IR) BDB
T4: 𝜇𝑝 decodes the opcode and decides whether T5 and T6 states
are required or next machine cycle executed is T1
During T2 state, after the RD signal is made LOW, the external
decoding circuit decodes the address put on the address bus duirng
T1 state. One of the memory location is selected and it puts 8-bit
information on the data bus during T2 and T3 states. Processor has
no control on it. Processor has already issued the signals and now it
is the job of the external decoding circuit to make use of the signals
IO/M and RD and address lines to allow the external memory to put
the data on the data bus. Therefore, this action is shown by shaded
area. Whatever information is avaiable on BDB at LOW to HIGH
transition of RD, that will be read and processed. The timing
waveform during 4-state OFMC is shown in fig.4.11.
T1 T2 T3 T4 T1
CLK

IO/M

S0

S1

PC high order byte Unspecified

A15-A8

PC low T.S
AD7-AD0 OP CODE
order byte High-Z

ALE

RD

middle
decode
latch low
order addr
Fig.4.11 Timing Diagram During 4-state OpCode Fetch Machine Cycle
During T4–T6 states, AD7-AD0 lines are tri-stated and A15-A8 lines are
unspecified.
Fig.4.12 shows the timing diagram for a 6-state OFMC:
T1 T2 T3 T4 T5 T6
CLK

IO/M

S0

S1

PC high order byte Unspecified

A15-A8

PC low T.S
AD7-AD0 OP CODE
order byte High-Z

ALE

RD

middle
decode
latch low
order addr

Fig.4.12 Timing Diagram During 6-state OpCode Fetch Machine Cycle

Note: Whenever the address information is sent from the program

counter to the external world during T1 state, then the (PC) is
incremented by 1 during the subsequent T2 state so that PC points to
the next subsequent byte. However, if the address information from
(PC) has not been sent out during the T1 state to the external world,
then (PC) will not be incremented during T2 state.

Memory READ Machine Cycle:

It requires 3 states T1 to T3. The purpose of the memory READ
operation is to read the contents of a memory location addressed by
a register pair and place the data in one of internal registers of the
𝜇𝑃. The source of address issued during T1 is not always the program
counter but may be any one of the several other register pairs in the
𝜇𝑃 depending on the particular instruction of which the machine cycle
is a part.
The 8085A uses machine cycle MC-1 to fetch and decode the
instruction. It then performs the memory read operation in MC-2. E.g.
in LXI H, Addr.
The IO/M signal is made LOW to indicate the external world
that a memory reference is required. Then 𝜇𝑃 made S0=0 and S1=1
indicating that memory READ operation is to be performed. During
T1, the 𝜇𝑃 places the contents of higher byte of the memory address
register, such as that contents of the (PCH) or (H) register on A15-A8
and the contents of the lower byte of the memory address register
such as contents of the (PCL) or (L) register on AD7-AD0. The 𝜇𝑃 sets
ALE signal HIGH indicating the beginning of MC-2. As soon as ALE
goes to LOW in the middle of T1, the lower byte of the address is
latched in an external latch. The same bus is now going to be used
as data bus.
During T2 state, the RD signal goes LOW indicating a READ
operation. If the address sent out during T1 state is from (PC), then
(PC) is incremented by 1 otherwise not. The external logic gets the
data from the memory location addressed by the memory address
register such as (H,L) pair and places the data on to bi-directional
data bus AD7-AD0.
 During T3 state, RD signal goes HIGH. This LOW to HIGH
transition of signal transfers the data from the data bus to internal
register such as the accumulator.
MRMC: Status signals IO/M=0, S1=1, S0=0
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (Internal Reg.) AD7-AD0 or BDB
Or
T1: A15-A8 (H), AD7-AD0 (L), ALE =
T2: RD = 0, AD7-AD0 M(AB)
T3: RD = 1, , (Internal Reg.) AD7-AD0 or BDB
The timing diagram during memory ready machine cycle is shown in
fig.4.13.
T1 T2 T3
CLK

IO/M

S0

S1

Higher order address byte

A15-A8

Low order T.S

AD7-AD0 Data from memory
addr byte

ALE

RD

Fig.4.13 Timing Diagram During Memory Read Machine Cycle