IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 31, NO.

4, AUGUST 2016 1493

Matrix Converter-Based Active Distribution

Transformer
S. F. Pinto, Member, IEEE, P. Alcaria, J. Monteiro, Member, IEEE, and J. Fernando Silva, Senior Member, IEEE

Abstract—This paper proposes a matrix converter-based active Also, voltage sags, especially short time duration sags (10 ms
distribution transformer (MC-ADT) with enhanced control func- to 100 ms) are one of the main Power Quality (PQ) issues [4],
tionalities to be used in smart grids (SG). The proposed MC-ADT [5]. They usually result from MV short circuits, turn-on of high
uses a matrix converter (MC) connected to a transformer inserted
in series with the grid, and allows: 1) real-time voltage regulation power machines and switching operations in the grid, and can
of the low-voltage side of the MC-ADT, based on an adjustable cause interruption or disruption of some industrial processes,
reference value defined by the SG requirements and bounded by leading to loss of production, usually with high associated costs.
the standard values; 2) capability to regulate the LV grid voltage In this context, it is necessary to rethink strategies to reg-
even in case of sags, voltage rises, and overvoltages in the trans- ulate the grid voltage. Smart grids are being planned to be
former medium-voltage side; and 3) contribution to power factor
correction in the MV side. The MC-ADT grid voltage regulators flexible, integrated, optimized and intelligent [2], [6]. They in-
are synthesized, establishing the MC reference currents. To guar- clude innovative grid infrastructures (AC or DC), active Dis-
antee the tracking of the MC input and output reference currents, tributed Energy Resources (DER), such as Distributed Stor-
the space vector representation, together with sliding-mode direct age devices (DS), Electrical Vehicles (EV), Distributed Gener-
control techniques, are used. The obtained experimental and simu-
ation units (DG), and controllable loads (large industrial con-
lation results show that the proposed system is able to regulate the
LV grid voltages even for sags and overvoltages up to 20% in the sumers/set of prosumers). Smart grids allow interaction with
MV side, and contributes to power factor correction in MV, while producers, consumers and markets, providing adaptableness to
presenting fast dynamic response, without overshoot and almost distinct operation scenarios, replacing reactivity with proactiv-
zero steady-state error. ity, thus predicting events leading emergencies, while providing
Index Terms—Active distribution transformer, AC-AC power self-healing capabilities, supported by high level of grid automa-
conversion, distributed energy resources, power quality, smart tion, smart metering, telemetering and other ICT technologies
grids, voltage control. [2].
The development of power electronic solutions is fundamen-
tal to the future grids [1], [6], as they allow the connection of
I. INTRODUCTION
DERs to the grid and enable a high level of controllability of
VER the last years, the penetration of distributed gener-
O ation (DG) has increased and it is expected that it will
continue to increase in the near future. This has changed the
the grid voltage [7], mitigating voltage sags [8] and frequency
fluctuations [9].
In particular, Matrix Converters (MC) [10]–[12], allow di-
paradigm of electrical generation sector and has created new rect AC/AC power conversion, with high efficiency [13], [14]
challenges to the Distribution System Operators (DSOs) [1], and without DC energy storage link, except for small ac filters
[2]. In particular in the Low Voltage (LV) grid, the bi-directional [14] to minimize switching ripples. The lack of bulky DC link
power flow has become a reality and issues as the voltage reg- electrolytic capacitors allows the reduction of this power con-
ulation are becoming more frequent [3]. Due to the connection verter volume, weight and costs, increasing the power density
of DGs to the LV grid, voltage rise is likely, especially in weak [14], [15] and their reliability [16] when compared to conven-
grids at no load scenarios, resulting in the noncompliance with tional Back to Back Voltage-Source Converter (VSC) structures
international standards and in the undesirable disconnection of with electrolytic capacitor banks. Furthermore, they allow bidi-
DG units when the grid voltage exceeds the equipment preset rectional power flow and do not contribute significantly to the
values. harmonic degradation of the input currents [11]. Due to these
characteristics, they have been proposed and used in the con-
nection of renewable energy resources to the grid [17]–[19],
Manuscript received March 24, 2015; revised November 25, 2015 and
September 13, 2015; accepted February 05, 2016. Date of publication February in Power Quality applications [20]–[22], as Dynamic Voltage
15, 2016; date of current version July 21, 2016. This work was supported by Restorers (DVR) with flywheel energy storage [20], as DVR
national funds through Fundação para a Ciência e a Tecnologia (FCT) with with fictious dc link [21], as DVR based topologies using asso-
reference UID/CEC/50021/2013. Paper no. TPWRD-00381-2015.
S. F. Pinto and J. F. Silva are with INESC-ID Lisboa, 1000-029, Lis- ciations of converters to compensate unbalanced loads, and in
boa, Portugal, and also with DEEC, Instituto Superior Técnico, Universidade Power Flow Controllers [23].
de Lisboa, 1049-001, Lisboa, Portugal (e-mail: [email protected]; The proposed MC-ADT (Fig. 1) consists of a MC and a se-
[email protected]).
P. Alcaria is with Instituto Superior Técnico, Universidade de Lisboa 1049- ries transformer that should be installed in the substation in the
001, Lisboa, Portugal (e-mail: [email protected]). low voltage side (Section II). The MC-ADT presents enhanced
J. Monteiro is with INESC-ID Lisboa, 1000-029, Lisboa, Portugal, and also functionalities when compared to on-load tap changer based so-
with ADESPA, Instituto Superior de Engenharia de Lisboa, Instituto Politécnico
de Lisboa, Lisboa 1959-007, Portugal (e-mail: [email protected]). lutions [24], performing as a DVR [25] without energy storage.
Digital Object Identifier 10.1109/TPWRD.2016.2530635 It allows an extended voltage control range, ensuring the com-
0885-8977 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
1494 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 31, NO. 4, AUGUST 2016

the series transformer (Tse), the matrix converter and filters, to

minimize harmonic contents. For MC-ADT system modelling,
the three phase voltage source, the shunt and series transformers
will be considered ideal.

A. Matrix Converter
An ideal three phase matrix converter may be considered as
an array of nine bi-directional switches, as presented in Fig. 2.
Fig. 1. Matrix Converter based Active Distribution Transformer. Each one of these bi-directional switches can be synthesized
using a pair of power semiconductor devices with turn-off ca-
pability and two diodes to guarantee bi-directional power flow.
The combination of these devices is presented as an inset in
Fig. 2.
Representing each Skj (k, j ∈ {1, 2, 3}) switch as a binary
variable with two possible states: “Skj = 1” if the switch is ON
and “Skj = 0” if it is OFF, the nine matrix converter switches
may be represented as a 3 × 3 matrix S [10]–[12] (1).
⎡ ⎤
S11 S12 S13
⎥ 
3
⎢
S = ⎣ 21S S 22 S 23 ⎦ Skj = 1 k, j ∈ {1, 2, 3} (1)
S31 S32 S33 k =1

As a result of topological constraints (1), there are 27 possible

switching combinations [10]–[12] that will result in 27 differ-
ent combinations for the MC output voltages vm o1 , vm o2 , vm o3 ,
and 27 combinations of input currents im i1 , im i2 , im i3 . The
Fig. 2. Detailed diagram of the MC-ADT showing the nine bi-directional matrix converter output phase voltages vm o1 , vm o2 , vm o3 are
switches S k j . related to the input phase voltages vm i1 , vm i2 , vm i3 depending
on the 9 switch states of matrix S. Then, the output line-to-
line voltages vm o12 , vm o23 , vm o31 are easily obtained from the
pliance with international standards, low amplitude low order output phase voltages vm o1 , vm o2 , vm o3 (2). The input phase
harmonics [11], reduced Total Harmonic Distortion, THDv , on currents im i1 , im i2 , im i3 are related to the output phase cur-
the LV grid voltage, and enabling the regulation of the feeder rents im o1 , im o2 , im o3 , depending on the transpose of matrix S
MV power factor to a nearly unitary value, thus reducing the [12].
capacitor banks in the substation. Also, it presents the possibil-
T
T
ity to adjust the LV grid voltage to DSO defined requirements, vm o1 vm o2 vm o3 = S vm i1 vm i2 vm i3
integrated in a smart grid, being able to increase or decrease
T
T
the LV grid reference voltage, for example, as a function of the im i1 im i2 im i3 = ST im o1 im o2 im o3 (2)
power flow in the distribution transformer, or as a function of
To control the MC using Space Vector based Modulation
overvoltage detection in the LV grid.
(SVM) approaches, it is useful to represent the 27 output volt-
In order to guarantee the robust behavior of the MC-ADT to
age and input current combinations as space vectors in the αβ
parameter variations and disturbances, external loop controllers
plane [12], by applying the transpose of Concordia transfor-
associated to sliding mode internal loop controllers are designed
mation to the 27 output voltage and input current combina-
(Section III). External loop controllers are used to control the
tions. Still, in most SVM based approaches, only the 18 vec-
voltage in the LV grid. They set the reference for the internal loop
tors with constant angular position (stationary vectors) are used
sliding mode current controllers, enabling the real time selec-
[11].
tion of the most adequate MC space vector, that will guarantee
In SVM approaches [11], or to control directly the MC output
the control of the matrix converter input and output currents.
voltages [12], it is usual to use the output line voltage space vec-
The dynamic behavior of the proposed MC-ADT is then evalu-
tors, obtained from the output line voltages vm o12 , vm o23 , vm o31 .
ated using detailed simulation and experimental implementation
However, in the proposed approach, where the matrix converter
(Section IV).
currents are to be controlled, to establish direct and decoupled
control actions, the output phase voltage space vectors are used
II. MODEL OF THE MC-ADT instead [17].
Fig. 2 presents a detailed representation of the proposed MC- To guarantee minimum harmonic contents, high frequency
ADT with the three-phase distribution shunt transformer (Tsh ), filters are required to the grid connection. From Fig. 2, the
PINTO et al.: MATRIX CONVERTER-BASED ACTIVE DISTRIBUTION TRANSFORMER 1495

To avoid over-sizing the series transformer, still guarantee-

ing the compensation of the most frequent sag/voltage rise, it
is assumed that the maximum sag compensation is 20%. The
series transformer rated power is calculated from the nominal
operation conditions (7), and for a 20% voltage sag compen-
sation its rated power should be nearly 20% of the distribution
transformer rated power.
Fig. 3. Per phase equivalent circuit of the MC-ADT.
SseN = 3 Vse L V m a x ILV (7)

dynamics of the input filter (3) [12] can be obtained in dq co- C. MC-ADT System Dynamic Model
ordinates using Park transformation, where ild and ilq are the From Fig. 2, the dynamics of the MC-ADT is obtained in αβ
matrix converter input filter coil currents, vm id and vm iq are the coordinates (8), using the Concordia transformation:
capacitor voltages, vsh LVd and vsh LVq are the shunt transformer
voltages, im id and im iq are the matrix converter input currents, ⎧ di rl 1 1
⎪
⎪
m oα
=− im o α + vm o α + √ vm o β −
and ω is the grid angular frequency (ω = 2πf ). ⎪
⎪ dt Lo 2Lo
⎧ ⎪
⎪ 2 3Lo
⎪
⎪ nse nse
⎪
⎪ dil d 1 1 1 ⎪
⎪ − vsh L V α + vL V α
⎪
⎪ = ω il q − vm i d − √ vm i q + vsh L V d ⎪
⎪
⎪
⎪ dt 2lf 2 3lf lf ⎪
⎪
Lo Lo
⎪
⎪ ⎪
⎪ dim o
⎪
⎪ di 1 1 1 ⎪
⎪ rl 1 1
⎪ lq ⎪
⎨ dt = − L im o β − √
β
vm o α + vm o β −
⎪ dt = −ω il d + √ vm i d − 2l vm i q + l vsh L V q
⎪
⎪ 2 3Lo 2Lo
⎪
⎪ 2 3lf f f o
(8)
⎪
⎪ ⎪
⎪
nse nse
⎪
⎪ dv m i 1 1 1 ⎪
⎪ − vsh L V β + vL V β
⎪
⎪
d
= il − √ il q − vm i d + ω v m i q ⎪
⎪ Lo Lo
⎪
⎪ dt 2Cf d 2 3Cf 3Cf rf ⎪
⎪
⎪
⎪ ⎪
⎪ dv n 1
⎪
⎪ 1 1 ⎪
⎪
LVα
=−
se
im o α −
⎪
⎪ + vsh L V d − √ vsh L V q − ⎪
⎪
iL V α
⎨ 2Cf rf ⎪
⎪
dt Co Co
2 3Cf rf ⎪
(3) ⎪
⎪
⎪
⎪ 1 1 ⎩ dvL V β = − nse im o − 1 iL V
⎪
⎪ − i + √ i dt Co β
Co β
⎪
⎪ 2Cf
m id
2 3Cf
m iq
⎪
⎪
⎪
⎪ dvm i q 1 1 1
⎪
⎪ where rl is the winding resistance of the output filter coils Lo ,
⎪ dt = √
⎪ il d + il q − ω vm i d − vm i q
⎪
⎪ 2 3Cf 2Cf 3Cf rf im oα and im oβ are the matrix converter output filter coil currents,
⎪
⎪
⎪
⎪ 1 1 vLV α and vLV β are the LV grid voltages, vm oα and vm oβ are the
⎪
⎪ + √ vsh L V d + vsh L V q
⎪
⎪ 2 3Cf rf 2C f rf
matrix converter output voltages and vsh LVα and vsh LVβ are the
⎪
⎪
⎪
⎪ 1 1 shunt transformer voltages.
⎪
⎪ − √ im i d −
⎩ 2Cf
im i q
2 3Cf
III. CONTROL OF THE MC-ADT
B. Series Transformer A. Control of Matrix Converter Output Currents
The series transformer guarantees the injection of a voltage The matrix converter output currents are controlled using a
vse LV in series with the distribution transformer voltage vsh LV non-linear sliding mode control approach associated to the space
(Fig. 3) ensuring the LV distribution line voltage vLV (4) is vector representation [17].
bounded by the standard voltage values. In the closed loop current controller, the matrix converter out-
vL V j = vsh LVj − vse L V j j ∈ {1, 2, 3} (4) put currents are measured and compared to the reference values
established by the LV grid voltage controller. Depending on
The series transformer turns ratio nse is defined according to the difference between the measured and the reference values
(5), where Vse and Vse LV are the RMS values of the voltages on the most adequate vector from the 18 possibilities [17] is cho-
the series transformer primary and secondary side (Fig. 2). sen to guarantee the sliding mode stability condition (9) [26],
nse = Vse /Vse LV (5) [27].

To design the series transformer it is necessary to establish Sγ (eγ , t) Ṡγ (eγ , t) < 0 γ ∈ {α, β} (9)
the RMS value of the maximum sag and voltage rise compen-
sation voltage (6), considering that the matrix√ converter max- From (8), and considering controlled voltages in the LV
imum voltage transfer ratio is Vm o /Vm i = 3/2 and neglect- grid, then the sliding surfaces Sα and Sβ will depend
ing the voltage drop in the matrix converter input and output only on the matrix converter output current errors (10) [17]
filters. (kγ > 0, γ ∈ {α, β}).
√
Vse m a x 1 3  
Vse LVj m a x = ≈ Vsh LVj j ∈ {1, 2, 3} (6) Sγ (eγ , t) = kγ im o γ r e f − im o γ = kγ eγ γ ∈ {α, β} (10)
nse nse 2
1496 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 31, NO. 4, AUGUST 2016

TABLE I
SELECTION OF VOLTAGE SPACE VECTORS FOR DIFFERENT
INPUT VOLTAGE SECTORS

Cα Cβ V1 2 V2 V4 V6 V8 V1 0
V1 V3 V5 V7 V9 V1 1

−1 −1 −9;+7 −9;+8 +8;−7 −7;+9 +9;−8 −8;+7

−1 0 +3;−1 +3;−2 −2;+1 +1;−3 −3;+2 +2;−1
−1 1 −6;+4 −6;+5 +5;−4 −4;+6 +6;−5 −5;+4
0 −1 −9;+7 −9;+8 +8;−7 −7;+9 +9;−8 −8+7
+6;−4 +6;−5 −5;+4 +4;−6 −6;+5 +5;−4
0 0 −8;+2 −7;+1 +9;−3 −8;+2 −7;+1 −9;+3
−5;+8 −4;+7 +6;−9 −5;+8 −4;+7 −6;+9
−2;+5 −1;+4 +3;−6 −2;+5 −1;+4 −3;+6
0 1 −6;+4 +5;−6 +5;−4 −4;+6 +6;−5 −5;+4
+9;−7 −8;+9 −8;+7 +7;−9 −9;+8 +8;−7
1 −1 +6;−4 +6;−5 −5;+4 +4;−6 −6;+5 +5;−4
1 0 −3;+1 +2; −3 −1;+2 +3;−1 −2;+3 +1;−2
1 1 +9;−7 +9;−8 +7;−8 +7;−9 −9;+8 +8;−7

From (9) and (10), the criteria to choose the space vectors
are:
1) If Sγ (eγ , t) > 0 ⇒ Ṡγ (eγ , t) < 0; (γ ∈ {α, β}) then
it should be chosen a vector to increase the current Fig. 4. (a) Matrix converter input voltages and corresponding sector; (b) Out-
put voltage space vectors when the input voltages are located in sector V 1 .
im o γ (γ ∈ {α, β});
2) If Sγ (eγ , t) < 0 ⇒ Ṡγ (eγ , t) > 0; (γ ∈ {α, β}) then
it should be chosen a vector to decrease the current From (11) and (12), the criteria to choose the space vector
im o γ (γ ∈ {α, β}); are:
3) If Sγ (eγ , t) ≈ 0; (γ ∈ {α, β}) then it should be chosen    
1) If Si i q ei i q , t > 0 ⇒ Ṡi i q ei i q , t < 0 then a vector
a vector that does not significantly change the current
im o γ (γ ∈ {α, β}) and contributes to minimize the input
should be chosen  to increase the
 current  iiq .
2) If Si i q ei i q , t < 0 ⇒ Ṡi i q ei i q , t > 0 then a vector
currents errors.
should be chosen to decrease the current iiq .
The control errors eα and eβ are quantized using two hystere-
The control error ei i q is then quantized using one hysteresis
sis comparators Cα and Cβ , each with three levels (−1, 0, +1),
comparator Ci i q with two levels (−1, +1). Considering the out-
resulting in nine output current error combinations.
put current error combinations, this will result in 2 × 9 = 18
As the input voltages are time dependent, to know the voltage
error combinations, which will be adequate to choose one of the
space vectors amplitude and location it is necessary to determine
18 vectors available. As the output currents are time dependent,
the input voltages location (sectors V1 to V12 ) [17]. To guarantee
to know the input current space vectors amplitude and location
the stability condition (9) only the highest amplitude voltage
it is necessary to determine the output currents location (sectors
vectors will be chosen (Table I). As an example, if the input
I1 to I12 ) [12], [17] (Fig. 5).
voltages are located in sector V1 and the result of the current
Picking up the previous example, if the input voltages are
error comparators is Cα = +1 and Cβ = +1, then vector +9 or
located in sector V1 , the result of the current error comparators is
−7 should be chosen (Fig. 4). Further, one of these redundant
Cα = +1, Cβ = +1, the output currents sector is Io1 (Table II)
vectors will be used to control the matrix converter input power
and the current error combination is Ci i q = +1 then vector +9
factor.
should be chosen. Otherwise, if Ci i q = −1 then vector −7 is
selected.
B. Control of Matrix Converter Input Power Factor
To control the input displacement factor it is considered that
the matrix converter is conservative, that is, the high frequency C. Control of the LV Grid Voltages
filter harmonic losses as well as the converter losses are ne-
The LV grid voltage controllers guarantee that the LV grid
glected [12], [17]. Then, considering a reference frame syn-
voltages are bounded by the standard limits, establishing the
chronous with the grid voltage, to guarantee the input power
references for the matrix converter output currents. The LV
factor control [12], [17] it will be necessary to control the input
voltage controllers are designed in a stationary reference frame
iiq current (11).
  [28], [29] assuming that the matrix converter sliding-mode con-
Si i q ei i q , t = ki i q (iiq r e f − iiq ) = ki i q ei i q (11) trolled currents may be represented as equivalent current sources
(γ ∈ {α, β}) (Fig. 6), where αi and αv represent the current and
The chosen vector should guarantee the sliding mode stability
voltage sensor gains.
condition [12] (12):
    The closed loop regulators for the LV grid voltages vLV α
Si i q ei i q , t Ṡi i q ei i q , t < 0 (12) and vLV β are obtained from Fig. 6 and the closed loop transfer
PINTO et al.: MATRIX CONVERTER-BASED ACTIVE DISTRIBUTION TRANSFORMER 1497

Fig. 7. Block diagram of the LV grid regulator.

Fig. 8. Vector diagram before PF correction in the MC-ADT.

Fig. 5. (a) Matrix converter output currents and corresponding sectors;

(b) Input current space vectors when the output currents are located in sec-
tor I1 .

TABLE II
CURRENT SPACE VECTORS SELECTION FOR DIFFERENT ERROR COMBINATIONS Fig. 9. Vector diagram after PF correction.

Sector V1 2 and V1 ; Sector I1

Cα Cβ Cq i

-1 1

−1 −1 −9 +7
−1 0 +3 −1
−1 1 −6 +4
0 −1 −9 +7
0 0 −2 +2
0 1 −7 +9
1 −1 −4 +6
1 0 +1 −3
1 1 −7 +9

Fig. 10. Global control scheme of Matrix Converter based Active Distribution
Transformer.
Fig. 6. Equivalent single phase model used to design the voltage regulator.

D. Power Factor Correction in MV

function for the LV grid voltages (γ ∈ {α, β}) (13) is obtained
from Fig. 7. The proposed MC-ADT is also able to regulate the power
factor locally in the MV feeding point of the distribution trans-
vL V γ nse Kp s + nse Ki former. Considering only the fundamental harmonic, the vector
= α n K
(13)
vLV γ ref 3 2 1
s + s T d + s Tvd αsie C op + αv nse Ki diagram before PF correction is represented in Fig. 8, where it
Td αi Co
is shown that the current in the LV grid (iLV ) is lagging the
The parameters of the PI compensators (14) can be deter- voltage (vLV ). Without PF correction, the current in the MV
mined using the optimum symmetry criterion [30]: grid (iM V ) is also lagging the MV grid voltage (vM V ), thus
requiring capacitors to compensate the power factor.
Co αi Co αi To guarantee near unity power factor locally in MV, it is nec-
Ki = Kp = (14)
a αv nse Td a3 αv nse Td2 essary that the current iM V is nearly in phase with the MV local
1498 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 31, NO. 4, AUGUST 2016

Fig. 11. Controlled LV grid voltages v LV 1 and v LV 2 , MV voltage (v M V 1 ) and current (iM V 1 ) under normal operation conditions. (a) Simulation results;
(b) Experimental results (5 ms/div).

Fig. 12. Response of the MC-ADT to a sag of 20% in the MV line, from t = 0.345 s to t = 0.48 s: waveforms of the MV voltage (vM V 1 ), series transformer
voltage (v se LV1 ), controlled LV grid voltage v LV 1 and LV grid current iLV 1 ; (a) Simulation results; (b) Experimental results (25 ms/div).

grid phase voltage VM V . This will be accomplished by measur- of the most adequate space vector at each sampling period
ing the LV current phase (φLV ) when compared to respective (Ts = 18 μs), according to the implemented control strategy.
voltage, and adding the measured angle to the reference phase The safe commutation between the MC bidirectional switches
of vLV ref (Fig. 9). was implemented in a Field Programmable Gate Array (FPGA)
using a Xilinx (Virtex 5) board (Fig. 10).
IV. SIMULATION AND EXPERIMENTAL RESULTS The obtained simulation and experimental results aim to test
the performance of the proposed MC-ADT in several operation
A detailed model of the proposed MC-ADT, including the
conditions: A) Nominal operation conditions; B) Voltage sag in
shunt and series transformers, the three-phase voltage source,
MV; C) Voltage rise in MV; D) Local Power Factor correction
the MC, the input and output LC filters, the three phase load and
in MV.
the designed control system was developed in Matlab/Simulink.
The experimental results were obtained using a scaled matrix
converter prototype, with three integrated modules from DAN- A. Nominal Operation Conditions
FOSS, rated 1200 V/25 A, each one with 6 IGBTs and 6 diodes Fig. 11 presents the results obtained under normal operation
in a common collector arrangement. The prototype was con- conditions, with the nominal load. The waveforms of the con-
nected to the laboratory low voltage network (230 V/50 Hz) us- trolled LV grid voltages vLV 1 and vLV 2 are nearly sinusoidal
ing a three-phase autotransformer and transformer Tsh adjusted with THDv40 < 1% and follow the preset references. The cur-
to turns ratio nsh = 2.09. The turns ratio of the series trans- rent in the MV side iM V is sinusoidal and, as the LV load
former is nse = 1. The matrix converter second order input LC is purely resistive, it is nearly in phase with the MV voltage
filter (Fig. 2) values are lf = 4.2 mH, Cf = 6.6 μF, rf = 25 Ω. vM V .
The output filtering inductance is Lo = 6.5 mF and the line
√ is Co = 20 μ F. The LV grid voltage is 110 V
grid capacitor
B. Voltage Sag in MV
(1 pu = √ 2 × 110 V), the nominal LV grid current is 3.3 A
(1 pu = 2 × 3.3 A) and the prototype power is 1.1 kVA (1 pu). The results obtained for MV voltage sags, under nominal
The MC-ADT control system was implemented in a digi- load operation, are presented in Figs. 12 and 13. Fig. 12 shows
tal signal processor dSPACE ds1103, guaranteeing the choice the waveforms of the MV voltage (vM V 1 ), series transformer
PINTO et al.: MATRIX CONVERTER-BASED ACTIVE DISTRIBUTION TRANSFORMER 1499

Fig. 13. Response of the MC-ADT to a sag of 20% in the MV line, from t = 0.365 s to t = 0.6 s: waveforms of the controlled LV grid voltages vLV 1 and
v LV 2 , matrix converter input current (im i1 ) and series transformer voltage (v se LV1 ); (a) Simulation results; (b) Experimental results (50 ms/div).

Fig. 14. Response of the MC-ADT to a voltage rise of 20% in the MV line, from t = 0.635 s to t = 0.78 s: waveforms of the MV voltage (vM V 1 ), series
transformer voltage (v se LV1 ), controlled LV grid voltage v LV 1 and LV grid current iLV 1 ; (a) Simulation results; (b) Experimental results (25 ms/div).

Fig. 15. Waveforms of the controlled LV grid voltage v LV 1 , series transformer voltage (v se LV1 ), MV voltage (v M V 1 ) and MV grid current iM V 1 without PF
compensation; (a) Simulation results; (b) Experimental results (5 ms/div).

voltage (vse LV1 ), controlled LV grid voltage vLV 1 and LV grid (vse LV1 ) is out of phase when compared to the MV grid voltage
current iLV 1 for a 20% voltage sag from t = 0.345 s to t = (Fig. 12), as expected.
0.48 s. It can be seen that the voltage at the LV grid remains Fig. 13 shows that the LV grid voltages vLV 1 and vLV 2 are
controlled at 1 pu, as a result of the series voltage injected in the sinusoidal and follow the preset references even for a 20%
distribution grid provided by the series transformer. According voltage sag from t = 0.365 s to t = 0.6 s. In normal operation
to the sign representation of Fig. 3, the series transformer voltage conditions the matrix converter input current (im i1 ) is nearly
1500 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 31, NO. 4, AUGUST 2016

Fig. 16. Waveforms of the controlled LV grid voltage v LV 1 , series transformer voltage (v se LV1 ), MV voltage (v M V 1 ) and MV grid current iM V 1 with PF
compensation; (a) Simulation results; (b) Experimental results (5 ms/div).

zero, but when the sag starts, it increases to 0.2 pu and is nearly the proposed MC-ADT is able to mitigate the propagation of
sinusoidal, as expected. sags, established undervoltages or voltage rise in the ±20%
range, and to regulate the power factor in MV, presenting
C. Voltage Rise in MV a fast dynamic response, without overshoot and nearly zero
steady-state error.
Fig. 14 shows the waveforms of the MV voltage (vM V 1 ),
series transformer voltage (vse LV1 ), controlled LV grid voltage
vLV 1 and LV grid current iLV 1 for a 20% voltage rise from
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