ZERO SKEW VS.
TOLERABLE SKEW
Clock soured the variation of delays from clock source to clock terminals.
Much research has been done in the area of performance driven clock
distribution mainly on the construction of clock trees to minimize clock
skew.
Most techniques used for skew minimization are based on adjusting the
interconnect lengths and widths.
1. Length adjustment technique to achieve zero skew.
2. Width sizing technique achieve zero by adjusting the widths of wires in
clock tree.
Due to the attempt to achieve the minimum skew for all clock sinks, wire
lengths or width of the clock tree may be increased substantially resulting
in increased power dissipation.
In electronic device or circuit SPCAP varies (size ,performance, cost,
accuracy& power consumption )
Here, we discuss an alternative approach by taking advantage of tolerance
skews.
Tolerable skew are the maximum value of clock skew b/w each pair of
clock sinks clock sinks with which the system can function correctly at
desired frequency.
DERIVATION OF TOLERABLE SKEW.
A typical synchronous system such as one which a pipelined /parallel
architecture can be building block figure show in below.
One single phase clock, assuming edge trigged flip flops are used.
Flip flops are characterized with dsetup-setup time ,dhold –hold time ,dFF-
flipflop delay.
Do1 is I/p of to flip-flop ffo1, D02 is I/p of to flip flop ff02, which is the o/p of
combinational logic.
Q01 d02
d0 q02
Ff01
logic Ff02
co1 c02
d11 q11 logic d12 q12
Ff11 Ff12
co c11 c12.
Dn1 qn1 dn2 qn2
Ffn1
logic
Ffn2
Cn1 cn2
Fig. Basic building block in pipelined /parallel
Some phase delay due to interconnection delay b/w the clock source c0 & c01,
c02 which terminal of ff01 and ff02.
The combinational logic block is characterized with maximum delay MAX
(dlogic) and minimum delay MIN (dlogic).
Two cases of correct synchronous operation with tolerable skews
a.Figure with negative clock skew
Seeing from above figure
c02<c01
Skew negative =c02-c01
= - (clock)
Hence known as negative clock skew
.
B .Figure positive tolerable skew
Seeing from above figure
C02>c01
Skew =c02-c01
= + (clock)
Hence known as positive clock skew
Incorrect synchronous operation with excessive clock skews
Figure a .double clocking with negative skew
Incorrect operation may occur as with excessive clock skew a phenomenon is
called double –clocking is caused by the late arrival of the clock signal at c02
At the clock transition, data is latched in the first flipflop, ff01. The second
stage flip flop ff02 latches in the data by combinational logic at same clock
transition .while missing data next clock transition.
A phenomenon called zero clocking occur when c02 is clock arrival too early
and second stage flip flop ,ff02 is unable to late the data at next clock transition
Figure b. shown below zero clocking with positive skew
Figure b .zero clocking with positive skew
To avoid these clock hazards under a given clock cycle time p.the clock timing
has to satisfy the following.
To avoid double clocking
D01+dff+MIN (dlogic)>= d02+ dhold
To avoid zero clocking
D01+dff+MAX (dlogic) +dsetup<=d02 +p
To tolerable skew clock sinks c01 & c02 can drive
Negative tolerable skew d01<=d02 (c02<=C1)
Skew t01 =d02-d01<=dff + MIN(dlogic)- dhlod
Positive tolerable skew ,d01>=d02
Skew to1 =d01-d02<=P - (dff +MAX(dlogic)+ dsetup)
If level sensitive latches are used instead of edge triggered flip flops ,the
sequential operation of register will allow larger positive tolerable skew
And smaller negative skew .clock cycle time ,P .
clock pulse width - Pwidth ,latch delay dlatch, latch setup time –dsetup& hold
time –dhold.
Negative tolerable skew with latches, d01<=d02
Skew t01=d02-d01<= dlatch +MIN(dlogic)-dhold-Ppulse
Positive tolerable skew wiyh latches d01 >=d02
Skew to1=d01-d02<=P+ Ppulse -(dlatch +Max(dlogic) +dsetup).
