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FORMAT-1B

Scaling of MOS Circuits

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CONTENTS

1. What is scaling?

2. Why scaling?

3. Figure(s) of Merit (FoM) for scaling

4. International Technology Roadmap for Semiconductors

(ITRS)

5. Scaling models

6. Scaling factors for device parameters

7. Implications of scaling on design

8. Limitations of scaling

9. Observations

10.Summary

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Scaling of MOS Circuits

1.What is Scaling?
Proportional adjustment of the dimensions of an electronic device while
maintaining the electrical properties of the device, results in a device either larger or
smaller than the un-scaled device. Then Which way do we scale the devices for VLSI?
BIG and SLOW … or SMALL and FAST? What do we gain?

2.Why Scaling?...

Scale the devices and wires down, Make the chips ‘fatter’ – functionality, intelligence,
memory – and – faster, Make more chips per wafer – increased yield, Make the end user
Happy by giving more for less and therefore, make MORE MONEY!!

3.FoM for Scaling

Impact of scaling is characterized in terms of several indicators:
o Minimum feature size

o Number of gates on one chip

o Power dissipation

o Maximum operational frequency

o Die size

o Production cost

Many of the FoMs can be improved by shrinking the dimensions of transistors and
interconnections. Shrinking the separation between features – transistors and wires
Adjusting doping levels and supply voltages.

3.1 Technology Scaling

Goals of scaling the dimensions by 30%:

Reduce gate delay by 30% (increase operating frequency by 43%)

Double transistor density

Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency)

Die size used to increase by 14% per generation

Technology generation spans 2-3 years

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Figure1 to Figure 5 illustrates the technology scaling in terms of minimum feature size,
transistor count, prapogation delay, power dissipation and density and technology
generations.

2
10
M inim um Feature Size (m icron)

1
10

0
10

-1
10

-2
10
1960 1970 1980 1990 2000 2010
Year
Figure-1:Technology Scaling (1)

Figure-2:Technology Scaling (2)

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Propagation Delay
Figure-3:Technology Scaling (3)

ears
100 x1.4 / 3 y 1000 ∝κ
0.7
Power Dissipation (W)

Power Density (mW/mm2 )

rs
y ea
3

10 /3 κ
x 4 100
∝

10
0.1
MPU
DSP
0.01 1
80 85 90 95 1 10
Scaling Factor κ
Year （
normalized by 4 µm design rule ）
(a) Power dissipation vs. year. (b) Power density vs. scaling factor.

Figure-4:Technology Scaling (4)

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Technology Generations

Figure-5:Technology generation

4. International Technology Roadmap for Semiconductors (ITRS)

Table 1 lists the parameters for various technologies as per ITRS.

Table 1: ITRS

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5.Scaling Models

Full Scaling (Constant Electrical Field)

Ideal model – dimensions and voltage scale together by the same scale factor

Fixed Voltage Scaling

Most common model until recently – only the dimensions scale, voltages remain constant

General Scaling

Most realistic for today’s situation – voltages and dimensions scale with different factors

6.Scaling Factors for Device Parameters

Device scaling modeled in terms of generic scaling factors:

1/α and 1/β
• 1/β: scaling factor for supply voltage VDD and gate oxide thickness D

• 1/α: linear dimensions both horizontal and vertical dimensions

Why is the scaling factor for gate oxide thickness different from other linear horizontal
and vertical dimensions? Consider the cross section of the device as in Figure 6,various
parameters derived are as follows.

Figure-6:Technology generation

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• Gate area Ag

Ag = L *W

Where L: Channel length and W: Channel width and both are scaled by 1/α
Thus Ag is scaled up by 1/α2

• Gate capacitance per unit area Co or Cox

Cox = εox/D
Where εox is permittivity of gate oxide(thin-ox)= εinsεo and D is the gate oxide thickness
scaled by 1/β 1
Thus Cox is scaled up by =β
1
 
β 

• Gate capacitance Cg C g = Co * L *W

Thus Cg is scaled up by β* 1/ α2 =β/ α2

• Parasitic capacitance Cx

Cx is proportional to Ax/d
where d is the depletion width around source or drain and scaled by 1/ α

Ax is the area of the depletion region around source or drain, scaled by (1/ α2 ).
Thus Cx is scaled up by {1/(1/α)}* (1/ α2 ) =1/ α

• Carrier density in channel Qon

Qon = Co * Vgs
where Qon is the average charge per unit area in the ‘on’ state.
Co is scaled by β and Vgs is scaled by 1/ β

Thus Qon is scaled by 1

• Channel Resistance Ron

L 1
Ron = *
W Qon * µ

Where µ = channel carrier mobility and assumed constant

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Thus Ron is scaled by 1.

• Gate delay Td

Td is proportional to Ron*Cg

Td is scaled by 1 β
2
*β =
α α2

• Maximum operating frequency fo

W µCoVDD
fo = *
L Cg

fo is inversely proportional to delay Td and is scaled by

 1  1
β *  =
2 
β  β

• Saturation current Idss

Co µ W
* * (Vgs − Vt )
2
I dss =
2 L
1 α2
Both Vgs and Vt are scaled by (1/ β). Therefore, Idss is scaled by =
 β  β
2
 α 

• Current density J
I dss
Current density, J = A where A is cross sectional area of the
Channel in the “on” state which is scaled by (1/ α2).
So, J is scaled by
1
β α2
=
1 β
α2

• Switching energy per gate Eg

•E = 1 C V 2
g g DD
2

So Eg is scaled by

β  1  1
*  2  = 2
2 
α β  α β 9
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• Power dissipation per gate Pg

Pg = Pgs + Pgd

Pg comprises of two components: static component Pgs and dynamic component Pgd:
2
Where, the static power component is given by: V DD
Pgs =
R on

And the dynamic component by: Pgd = E g f o

Since VDD scales by (1/β) and Ron scales by 1, Pgs scales by (1/β2).

Since Eg scales by (1/α2 β) and fo by (α2 /β), Pgd also scales by (1/β2). Therefore, Pg

scales by (1/β2).

• Power dissipation per unit area Pa

 1 
 
P g  β 2  α 2
Pa = = =
Ag  1  β 2
 2
α 
• Power – speed product PT 1  β  1
2  2 
PT = Pg * Td = = 2
β α  α β
6.1 Scaling Factors …Summary
Various device parameters for different scaling models are listed in Table 2 below.

Table 2: Device parameters for scaling models

NOTE: for Constant E: β=α; for Constant V: β=1
General Constant E Constant V
(Combined V
Parameters Description
and
Dimension)
VDD Supply voltage 1/β 1/α 1
L Channel length 1/α 1/α 1/α
W Channel width 1/α 1/α 1/α
D Gate oxide thickness 1/β 1/α 1
2 2 2
Ag Gate area 1/α 1/α 1/α
Gate capacitance per β α 1
Co (or Cox) unit area
Cg Gate capacitance β/α2 1/α 1/α
2

Cx Parsitic capacitance 1/α 1/α 1/α

Qon Carrier density 1 1 1
Ron Channel resistance 1 1 1
10
Idss Saturation current 1/β 1/α 1
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General Constant E Constant V

(Combined V
Parameters Description
and
Dimension)
Conductor cross 2 2 2
1/α 1/α 1/α
Ac section area
J Current density α2 / β α α2
Vg Logic 1 level 1/β 1/α 1
Eg Switching energy 1 / α2 β 1 / α3 1/α
2

Power dissipation per 2 2 1

1/β 1/α
Pg gate
N Gates per unit area α2 α2 α2
Power dissipation per α2 / β2 1 α2
Pa unit area
Td Gate delay β / α2 1/α 1/α
2

Max. operating α2 / β α α2
fo frequency
PT Power speed product 1 / α2 β 1 / α3 1/α
2

7.Implications of Scaling

Improved Performance

Improved Cost

Interconnect Woes

Power Woes

Productivity Challenges

Physical Limits

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7.1Cost Improvement
– Moore’s Law is still going strong as illustrated in Figure 7.

Figure-7:Technology generation

7.2:Interconnect Woes
• Scaled transistors are steadily improving in delay, but scaled wires are holding
constant or getting worse.
• SIA made a gloomy forecast in 1997
– Delay would reach minimum at 250 – 180 nm, then get
worse because of wires
• But…
• For short wires, such as those inside a logic gate, the wire RC delay is negligible.
• However, the long wires present a considerable challenge.
• Scaled transistors are steadily improving in delay, but scaled wires are holding
constant or getting worse.
• SIA made a gloomy forecast in 1997
– Delay would reach minimum at 250 – 180 nm, then get
worse because of wires
• But…
• For short wires, such as those inside a logic gate, the wire RC delay is negligible.
• However, the long wires present a considerable challenge.
Figure 8 illustrates delay Vs. generation in nm for different materials.

Figure-8:Technology generation

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7.3 Reachable Radius

• We can’t send a signal across a large fast chip in one cycle anymore

• But the microarchitect can plan around this as shown in Figure 9.

– Just as off-chip memory latencies were tolerated

Chip size

Scaling of
reachable radius

Figure-9:Technology generation

7.4 Dynamic Power

• Intel VP Patrick Gelsinger (ISSCC 2001)

– If scaling continues at present pace, by 2005, high speed processors would

have power density of nuclear reactor, by 2010, a rocket nozzle, and by
2015, surface of sun.

– “Business as usual will not work in the future.”

• Attention to power is increasing(Figure 10)

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Figure-10:Technology generation

7.5 Static Power

• VDD decreases

– Save dynamic power

– Protect thin gate oxides and short channels

– No point in high value because of velocity saturation.

• Vt must decrease to maintain device performance

• But this causes exponential increase in OFF leakage

A Major future challenge(Figure 11)

Moore(03)

Figure-11:Technology generation

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7.6 Productivity
• Transistor count is increasing faster than designer productivity (gates / week)

– Bigger design teams

• Up to 500 for a high-end microprocessor

– More expensive design cost

– Pressure to raise productivity

• Rely on synthesis, IP blocks

– Need for good engineering managers

7.7 Physical Limits

o Will Moore’s Law run out of steam?

 Can’t build transistors smaller than an atom…

o Many reasons have been predicted for end of scaling

 Dynamic power

 Sub-threshold leakage, tunneling

 Short channel effects

 Fabrication costs

 Electro-migration

 Interconnect delay

o Rumors of demise have been exaggerated

8. Limitations of Scaling

Effects, as a result of scaling down- which eventually become severe enough to prevent
further miniaturization.
o Substrate doping

o Depletion width

o Limits of miniaturization

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o Limits of interconnect and contact resistance

o Limits due to sub threshold currents

o Limits on logic levels and supply voltage due to noise

o Limits due to current density

8.1 Substrate doping

o Substrate doping

o Built-in(junction) potential VB depends on substrate doping level – can be

neglected as long as VB is small compared to VDD.

o As length of a MOS transistor is reduced, the depletion region width –scaled

down to prevent source and drain depletion region from meeting.

o the depletion region width d for the junctions is d = 2 ξ si ξ 0V

q NB 1

o ε si relative permittivity of silicon

o ε 0 permittivity of free space(8.85*10-14 F/cm)

o V effective voltage across the junction Va + Vb

o q electron charge

o NB doping level of substrate

o Va maximum value Vdd-applied voltage

o Vb built in potential and KT  N B N D 

VB = ln  
q  ni ni 

8.2 Depletion width

• N B is increased to reduce d , but this increases threshold voltage Vt -against
trends for scaling down.

• Maximum value of N B (1.3*1019 cm-3 , at higher values, maximum electric field

applied to gate is insufficient and no channel is formed.

• N B maintained at satisfactory level in the channel region to reduce the above

problem.
2V
• Emax maximum electric field induced in the junction. Emax =
d
ln α
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If N B is inreased by α Va =0 Vb increased by ln α and d is decreased by

• Electric field across the depletion region is increased by

ln α
1/
α

• Reach a critical level Ecrit with increasing N B 2 ξ si  Ecrit .d 

d= ξ 
ξ si ξ 0 q NB  2 
Where d= ( Ecrit )
q NB

Figure 12 , Figure 13 and Figure 14 shows the relation between substrate concentration
Vs depletion width , Electric field and transit time.
Figure 15 demonstrates the interconnect length Vs. propagation delay and Figure 16
oxide thickness Vs. thermal noise.

Figure-12:Technology generation

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Figure-13:Technology generation

8.3 Limits of miniaturization

• minimum size of transistor; process tech and physics of the device

• Reduction of geometry; alignment accuracy and resolution

• Size of transistor measured in terms of channel length L

L=2d (to prevent push through)

• L determined by NB and Vdd

• Minimum transit time for an electron to travel from source to drain is

v drift = µE

L 2d
t= =
Vdrift µE

• smaximum carrier drift velocity is approx. Vsat,regardless of supply voltage

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Figure-14:Technology generation

8.4 Limits of interconnect and contact resistance

• Short distance interconnect- conductor length is scaled by 1/α and resistance is

increased by α

• For constant field scaling, I is scaled by 1/ α so that IR drop remains constant as a

result of scaling.-driving capability/noise margin.

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Figure-15:Technology generation

8.5 Limits due to subthreshold currents

• Major concern in scaling devices.
• I sub is directly praportinal exp (Vgs – Vt ) q/KT
• As voltages are scaled down, ratio of Vgs-Vt to KT will reduce-so that threshold
current increases.
• Therefore scaling Vgs and Vt together with Vdd .
• Maximum electric field across a depletion region is

Emax = 2{Va + Vb }/ d

8.6 Limits on supply voltage due to noise

Decreased inter-feature spacing and greater switching speed –result in noise problems

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Figure-16:Technology generation

9. Observations – Device scaling

o Gate capacitance per micron is nearly independent of process
o But ON resistance * micron improves with process
o Gates get faster with scaling (good)
o Dynamic power goes down with scaling (good)
o Current density goes up with scaling (bad)
o Velocity saturation makes lateral scaling unsustainable
9.1 Observations – Interconnect scaling
o Capacitance per micron is remaining constant
o About 0.2 fF/mm
o Roughly 1/10 of gate capacitance
o Local wires are getting faster
o Not quite tracking transistor improvement
o But not a major problem
o Global wires are getting slower
o No longer possible to cross chip in one cycle
10. Summary
• Scaling allows people to build more complex machines
– That run faster too
• It does not to first order change the difficulty of module design

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– Module wires will get worse, but only slowly

– You don’t think to rethink your wires in your adder, memory
Or even your super-scalar processor core
• It does let you design more modules
• Continued scaling of uniprocessor performance is getting hard
-Machines using global resources run into wire limitations
-Machines will have to become more explicitly parallel

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CMOS SUBSYSTEM DESIGN

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CONTENTS

1. System
2. VLSI design flow

3. Structured design approach

4. Architectural issues

5. MOSFET as switch for logic functionality

6. Circuit Families
Restoring Logic: CMOS and its variants - NMOS and Bi CMOS
Other circuit variants
NMOS gates with depletion (zero -threshold) pull up
Bi-CMOS gates

7. Switch logic: Pass Transistor and Transmission gate (TG)

8. Examples of Structured Design

MUX
DMUX
D Latch and Flop
A general logic function block

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1.What is a System?
A system is a set of interacting or interdependent entities forming and integrate whole.
Common characteristics of a system are
o Systems have structure - defined by parts and their composition
o Systems have behavior – involves inputs, processing and outputs (of material,
information or energy)
o Systems have interconnectivity the various parts of the system functional as well
as structural relationships between each other

1.1Decomposition of a System: A Processor

5. VLSI Design Flow

• The electronics industry has achieved a phenomenal growth –mainly due to the
rapid advances in integration technologies, large scale systems design-in short due
to VLSI.
• Number applications of integrated circuits in high-performance computing,
telecommunications, and consumer electronics has been rising steadily.
• Current leading-edge technology trend –expected to continue with very important
implications on VLSI and systems design.
• The design process, at various levels, is evolutionary in nature.
• Y-Chart (first introduced by D. Gajski) as shown in Figure1 illustrates the design
flow for mast logic chips, using design activities.
• Three different axes (domains) which resemble the letter Y.
• Three major domains, namely
Behavioral domain
Structural domain

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Geometrical domain
• Design flow starts from the algorithm that describes the behavior
of target chip.

Figure 1. Typical VLSI design flow in three domains(Y-chart)

VLSI design flow, taking in to account the various representations, or abstractions of

design are
Behavioural,logic,circuit and mask layout.

Verification of design plays very important role in every step during process.
Two approaches for design flow as shown in Figure 2 are
Top-down
Bottom-up

Top-down design flow- excellent design process control

In reality, both top-down and bottom-up approaches have to be combined.
Figure 3 explains the typical full custom design flow.

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Figure 2. Typical VLSI design flow

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Figure 3. Typical ASIC/Custom design flow

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3 Structured Design Approach

• Design methodologies and structured approaches developed with complex

hardware and software.
• Regardless of the actual size of the project, basic principles of structured design-
improve the prospects of success.
• Classical techniques for reducing the complexity of IC design are:
Hierarchy
Regularity
Modularity
Locality

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Figure 4-Structured Design Approach –Hierarchy

Figure5-.Structured Design Approach –Regularity

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• Design of array structures consisting of identical cells.-such as parallel

multiplication array.
• Exist at all levels of abstraction:
transistor level-uniformly sized.
logic level- identical gate structures
• 2:1 MUX, D-F/F- inverters and tri state buffers
• Library-well defined and well-characterized basic building block.
• Modularity: enables parallelization and allows plug-and-play
• Locality: Internals of each module unimportant to exterior modules and internal
details remain at local level.

Figure 4 and Figure 5 illustrates these design approaches with an example.

4 Architectural issues

• Design time increases exponentially with increased complexity

• Define the requirements
• Partition the overall architecture into subsystems.
• Consider the communication paths
• Draw the floor plan
• Aim for regularity and modularity
• convert each cell into layout
• Carry out DRC check and simulate the performance

5. MOSFET as a Switch

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9.4 D Flip-flop Operation

QM Q
D

CLK = 0

QM
D Q

CLK = 1

CLK

9.5 Race Condition

• Back-to-back flops can malfunction from clock skew
– Second flip-flop fires late
– Sees first flip-flop change and captures its result
– Called hold-time failure or race condition

CLK1
CLK1 CLK2 CLK2

Q1
Flop

Flop

Q1 Q2
D
Q2

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5.2 Series connection of Switches..

5.3 Series and parallel connection of Switches..

a a a a a
0 0 1 1
g1
g2
0 1 0 1
b b b b b
(a) OFF OFF OFF ON

a a a a a
0 0 1 1
g1
g2
0 1 0 1
b b b b b
(b) ON OFF OFF OFF

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF

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6. Circuit Families : Restoring logic

CMOS INVERTER

A Y V DD

0
A Y
A Y
1

GND

V DD
A Y
OFF

0 A Y A= 1

ON
Y= 0

1 0 GND

V DD

A Y ON
A= 0 Y= 1
0 1 A Y OFF

1 0 GND

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6.1 NAND gate Design..

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A B Y
ON ON
0 0 1 Y=1
A=0
0 1 OFF
1 0 B=0
OFF
1 1

A B Y OFF ON
0 0 1 Y=1
A=0
0 1 1 OFF
1 0
B=1
1 1
ON

A B Y
ON OFF
0 0 1 Y=1
A=1
0 1 1 ON
B=0
1 0 1 OFF
1 1 0

NAND gate Design..

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Y
A
B
C

6.2 NOR gate Design..

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A
B
C
D
Y

CMOS INVERTER

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6.3 CMOS Properties

Pull-up OFF Pull-up ON

Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)

pMOS
pull-up
network
inputs
output

nMOS
pull-down
network

• Complementary CMOS gates always produce 0 or 1

• Ex: NAND gate
• Series nMOS: Y=0 when both inputs are 1
• Thus Y=1 when either input is 0
• Requires parallel pMOS
• Rule of Conduction Complements

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• Pull-up network is complement of pull-down

• Parallel -> series, series -> parallel
• Output signal strength is independent of input.-level restoring
• Restoring logic. Ouput signal strength is either Voh (output high) or Vol. (output
low).
• Ratio less logic :output signal strength is independent of pMOS device size to
nMOS size ratio.
• significant current only during the transition from one state to another and - hence
power is conserved..
• Rise and fall transition times are of the same order,
• Very high levels of integration,
• High performance.

6.4 Complex gates..

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6.5 Complex gates AOI..

Y = A B + C D (A ND -A N D-OR-INV ERT, A O I22)

A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
AY = (A+ B +C
C) D D
B D
(f)

(e) A
B
C D
Y
D
A B C

unit inverter AOI21 AOI22 Complex AOI

Y=A Y = A B+C Y = A B+C D Y = A ( B + C) + D E
D
A A E
Y
B B A
A Y Y Y
C C B
D C

A 4 B 4 A 4 B 4 B 6
2 C 4 C 4 D 4 C 6 A 3
A Y Y Y
1 A 2 A 2 C 2 D 6 E 6
C 1 Y
B 2 B 2 D 2 E 2 A 2
D 2 B 2 C 2

gA = 3/3 gA = 6/3 gA = 6/3 gA = 5/3

p = 3/3 gB = 6/3 gB = 6/3 gB = 8/3
gC = 5/3 gC = 6/3 gC = 8/3
p = 7/3 gD = 6/3 gD = 8/3
p = 12/3 gE = 8/3
p = 16/3

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6.6 Circuit Families : Restoring logic CMOS Inverter- Stick diagram

6.7 Restoring logic CMOS Variants: nMOS Inverter-stick diagram

• Basic inverter circuit: load replaced by depletion mode transistor

• With no current drawn from output, the current Ids for both transistor must
be same.
• For the depletion mode transistor, gate is connected to the source so it is
always on and only the characteristic curve Vgs=0 is relevant.

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• Depletion mode is called pull-up and the enhancement mode device pull-
down.
• Obtain the transfer characteristics.
• As Vin exceeds the p.d. threshold voltage current begins to flow, Vout thus
decreases and further increase will cause p.d transistor to come out of
saturation and become resistive.
• p.u transistor is initially resistive as the p.d is turned on.
• Point at which Vout = Vin is denoted as Vinv
• Can be shifted by variation of the ratio of pull-up to pull-down resistances
–Zp.u / Zp.d
• Z- ratio of channel length to width for each transistor

For 8:1 nMOS Inverter

Z p.u. = L p.u. / W p.u =8

R p.u = Z p.u. * Rs =80K
similarly
R p.d = Z p.d * Rs =10K
Power dissipation(on) Pd = V2 /Rp.u + Rp.d =0.28mV
Input capacitance = 1 Cg

For 4:1 nMOS Inverter

Z p.u. = L p.u. / W p.u =4

R p.u = Z p.u. * Rs =40K
similarly
R p.d = Z p.d * Rs =5K
Power dissipation(on) Pd = V2 /Rp.u + Rp.d =0.56mV
Input capacitance = 2Cg

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6.8Restoring logic CMOS Variants: BiCMOS Inverter-stick diagram

• A known deficiency of MOS technology is its limited load driving capabilities

(due to limited current sourcing and sinking abilities of pMOS and nMOS
transistors. )
• Output logic levels good-close to rail voltages
• High input impedance
• Low output impedance
• High drive capability but occupies a relatively small area.
• High noise margin
• Bipolar transistors have
• higher gain
• better noise characteristics
• better high frequency characteristics
• BiCMOS gates can be an efficient way of speeding up VLSI circuits
• CMOS fabrication process can be extended for BiCMOS
• Example Applications
CMOS- Logic
BiCMOS- I/O and driver circuits
ECL- critical high speed parts of the system

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6.9 Circuit Families : Restoring logic CMOS NAND gate

6.10 Restoring logic CMOS Variants: nMOS NAND gate

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6.11 Restoring logic CMOS Variants: BiCMOS NAND gate

• For nMOS Nand-gate, the ratio between pull-up and sum of all pull-downs must
be 4:1.
• nMOS Nand-gate area requirements are considerably greater than corresponding
nMOS inverter
• nMOS Nand-gate delay is equal to number of input times inverter delay.
• Hence nMOS Nand-gates are used very rarely
• CMOS Nand-gate has no such restrictions
• BiCMOS gate is more complex and has larger fan-out.

7.Circuit Families :Switch logic: Pass Transistor

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7.1 Switch logic: Pass Transistor

g g=0 Input g = 1 Output

s d 0 strong 0
s d
g=1 g=1
s d 1 degraded 1

g g=0 Input Output

g=0 49
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7.1 Switch logic: Pass Transistor-nMOS in series

VDD VDD VDD

VDD VDD
VDD
Vs = VDD-Vtn VDD-Vtn
VDD-Vtn VDD-Vtn

VDD
Vs = |Vtp| VDD-Vtn
VDD VDD-2Vtn
VSS

7.2 :Switch logic: Transmission gates

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Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb

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8 Structured Design-Tristate
• Tristate buffer produces Z when not enabled

EN A Y

0 0

0 1

1 0
E N
1 1 A Y

Tristate buffer produces Z when not enabled

E N
EN A Y
A Y
0 0 Z
E N
0 1 Z

1 0 0

1 1 1

8.1 Structured Design-Nonrestoring Tristate

EN

A Y

EN

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8.3 Structured Design-Tristate Inverter

A
EN
Y
EN

• Tristate inverter produces restored output

– Violates conduction complement rule
– Because we want a Z output

A A
A
EN
Y Y Y
EN

EN = 0 EN = 1
Y = 'Z' Y=A

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8.4 Structured Design-Multiplexers

• 2:1 multiplexer chooses between two inputs

S D1 D0 Y

0 X 0 0 S
0 X 1 1 D0 0
Y
1 0 X 0 1
D1
S D1 D0 Y
1 1 X 1

0 X 0

0 X 1

1 0 X

1 1 X

8. 5 Structured Design-Mux Design.. Gate-Level

Y = SD1 + SD0 (too many transistors)

• How many transistors are needed?

• How many transistors are needed? 20

D1
S Y
D0
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8.6 Structured Design-Mux Design-Transmission Gate

• Nonrestoring mux uses two transmission gates
– Only 4 transistors

D0
S Y
D1

Inverting Mux
• Inverting multiplexer
– Use compound AOI22
– Or pair of tristate inverters
• Noninverting multiplexer adds an inverter

D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1

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8.7 Design-4:1 Multiplexer

• 4:1 mux chooses one of 4 inputs using two selects
Two levels of 2:1 muxes
Or four tristates
S1S0 S1S0 S1S0 S1S0

D0
S0 S1

D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1

D3

9 Structured Design-D Latch

• When CLK = 1, latch is transparent
– D flows through to Q like a buffer
• When CLK = 0, the latch is opaque
– Q holds its old value independent of D
• a.k.a. transparent latch or level-sensitive latch

CLK CLK

D
Latch

D -a latch is level
Q sensitive Q
– a register is edge-triggered
– A flip-flop is a bi-stable element
–

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9.1 D Latch Design

• Multiplexer chooses D or old Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

CLK

9.2 D Latch Operation

Q Q
D Q D Q

CLK = 1 CLK = 0 57
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Structured Design-Latch Design

φ
X
D Q
• Inverting buffer
Restoring φ
No backdriving φ
Fixes either
Output noise sensitivity D Q
Or diffusion input
Inverted output φ

9.3 Structured Design-D Flip-flop

• When CLK rises, D is copied to Q
• At all other times, Q holds its value
• a.k.a. positive edge-triggered flip-flop, master-slave flip-flop

CLK
CLK
D
Flop

D Q Q

• Structured Design-D Flip-flop Design

• Built from master and slave D latches

CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch

Latch

QM
D Q
CLK CLK

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9.4 D Flip-flop Operation

QM Q
D

CLK = 0

QM
D Q

CLK = 1

CLK

9.5 Race Condition

• Back-to-back flops can malfunction from clock skew
– Second flip-flop fires late
– Sees first flip-flop change and captures its result
– Called hold-time failure or race condition

CLK1
CLK1 CLK2 CLK2

Q1
Flop

Flop

Q1 Q2
D
Q2

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