INDUSTRIAL TRAINING REPORT

ON

Implementation of Digital Clock on FPGA

By
Sonam Singhal (2014BEC1161)

Submitted to the department of Electronics & Communication Engineering

In partial fulfilment of the requirements for the degree of
Bachelor of Technology
In
Electronics & Communication Engineering

ABES Engineering College, Ghaziabad

Dr. A.P.J. Abdul Kalam Technical University, Lucknow
August, 2017
 ACKNOWLEDGEMENT

I take this opportunity to express my sincere gratitude towards Training and

placement officer of my college for forwarding my training letter to Tech Adityaa,
Ghaziabad and also to Mr. Vaibhav Mishra Co-founder, Tech Adityaa, Ghaziabad
for accepting my letter and allowing me to complete my training in Tech Adityaa.

I am grateful to Mr. Abhishek, to guide and help me throughout my project. It is

not without his help I could have been able to complete my training here. I would
like to express my deep satisfaction and gratitude for their support for their kind
help extended during the entire period of training.

Finally, I would like to thank each member of Tech Adityaa family for making me
feel comfortable and helping me in every possible manner.
 Index
1 General Description

2 System Requirements
2.1 General Requirements
2.2 Functional Requirements
2.3 Memory Requirements

3 Overview of FPGA
3.1 Introduction
3.2 Features

4 Architectural Overview of FPGA

4.1 Architectural Overview
4.2 Control Logic Blocks(CLBs)
4.2.1 Look Up Table(LUTs)
4.3 Input-Output Blocks (IOBs)
4.4 Block RAM
4.4.1 Arrangement of RAM Blocks on die
4.4.2 Internal structure of Block RAM

5 Design Summary
5.1 Block Diagram
5.2 RTL Schematic

6 Working

7 Appendix
7.1 Verilog Code-Alarm.v

8 Conclusion

9 Refrences
1. General Description

The aim this project is to implement the functionality of a digital

alarm clock on a FPGA. As soon as the FPGA is switched on, the clock
starts. The alarm can be set using the dip-switches provided on the
FPGA board. This is indicated through the LEDs of the corresponding
dip switch. The counter keeps rolling and as soon as the alarm goes
off, a buzzer like sound is magnified via a speaker.
2. System Requirements

2.1 General Requirements

The Digital Alarm Clock system has the following general requirements:
• It should use low power
• The cost of production should be low
• The software architecture must be modular

2.2 Functional Requirements

The Digital Alarm Clock system should have following Functional Requirements:
 The clock timing should be accurate i.e. no glitches should be present.
 The design should use power judiciously.
 The speaker should play the sound clearly and should be synchronized.

2.3 Memory Requirements

No permanent storage is required. All the data is stored on the programming stack
3. Overview of the FPGA

3.1 Introduction

The Spartan™-3 family of Field-Programmable Gate Arrays is specifically designed to meet

the needs of high volume, cost-sensitive consumer electronic applications. The Spartan-3
family builds on the success of the earlier. Spartan-IIE family by increasing the amount of
logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level
of performance as well as by improving clock management functions. Because of their
exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer
electronics applications; including broadband access, home networking, display/projection
and digital television equipment.

The Spartan-3 family is a superior alternative to mask programmed ASICs. FPGAs avoid the
high initial cost, the lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no
hardware replacement necessary, an impossibility with ASICs.

3.2 Features

•Low-cost, high-performance logic solution for high-volume, consumer-oriented applications

-Densities up to 74,880 logic cells
•SelectIO™ signaling
-Up to 784 I/O pins
-622 Mb/s data transfer rate per I/O
-18 single-ended signal standards
-8 differential I/O standards including LVDS, RSD
-Termination by Digitally Controlled Impedance
-Signal swing ranging from 1.14V to 3.45V
-Double Data Rate (DDR) support
-DDR, DDR2 SDRAM support up to 333 Mbps
•Logic resources
-Abundant logic cells with shift register capability
-Wide, fast multiplexers
-Fast look-ahead carry logic
-Dedicated 18 x 18 multipliers
-JTAG logic compatible with IEEE 1149.1/1532
•SelectRAM™ hierarchical memory
-Up to 1,872 Kbits of total block RAM
-Up to 520 Kbits of total distributed RAM
•Digital Clock Manager (up to four DCMs)
-Clock skew elimination
-Frequency synthesis
-High resolution phase shifting
•Eight global clock lines and abundant routing
•Fully supported by Xilinx ISE development system
-Synthesis, mapping, placement and routing
•MicroBlaze™ processor, PCI, and other cores •Pb-
free packaging options
•Low-power Spartan-3L Family and Automotive Spartan-3 XA Family variants
4. Architectural Overview of the FPGA

4.1 Architectural Overview

The Spartan-3 family architecture consists of five fundamental programmable functional
elements:
1. Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to
implement logic and storage elements that can be used as flip-flops or latches. CLBs
can be programmed to perform a wide variety of logical functions as well as to store
data.
2. Input-Output Blocks (IOBs) control the flow of data between the I/O pins and the
internal logic of the device. Each IOB supports bidirectional data flow plus 3-state
operation. Twenty-four different signal standards, including seven high-performance
differential standards, are available as shown in Table2. Double Data-Rate (DDR)
registers are included. The Digitally Controlled Impedance (DCI) feature provides
automatic on-chip terminations, simplifying board designs.
3. Block RAM provides data storage in the form of 18-Kbit dual-port blocks.
4. Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the
product.
5. Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for
distributing, delaying, multiplying, dividing, and phase shifting clock signals.

These elements are organized as shown in Figure below. A ring of IOBs surrounds a regular
array of CLBs.

Spartan-3 Family Architecture

4.2 Configurable Logic Blocks (CLBs)

The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing
synchronous as well as combinatorial circuits. Each CLB comprises four interconnected slices.
These slices are grouped in pairs. Each pair is organized as a column with an independent
carry chain.
 Local routing provides feedback between slices in the same CLB, and it
provides routing to neighboring CLBs
 A switch matrix provides access to general routing resources
 Each slice has four outputs
 Two registered outputs, two non-registered outputs
 Two BUFTs associated with each CLB, accessible by all 16 CLB outputs
 Simplified Slice Structure

4.2.1 Look Up Tables

• Combinatorial logic is stored in Look-Up Tables (LUTs)
– Also called Function Generators (FGs)
– Capacity is limited by the number of inputs, not by the complexity
• Delay through the LUT is constant

The RAM-based function generator — also known as a Look-Up Table or LUT — is the main
resource for implementing logic functions. Furthermore, the LUTs in each left-hand slice pair
can be configured as Distributed RAM or a 16-bit shift register.
The storage element, which is programmable as either a D-type flip-flop or a level-sensitive
latch, provides a means for synchronizing data to a clock signal, among other uses.
The storage elements in the upper and lower portions of the slice are called FFY and FFX,
respectively. Wide-function multiplexers effectively combine LUTs in order to permit more
complex logic operations.
4.3 Input-output Blocks (IOB)
The Input-Output Block (IOB) provides a programmable, bidirectional interface between an
I/O pin and the FPGA’s internal logic. There are three main signal paths within the IOB: the
output path, input path, and 3-state path. Each path has its own pair of storage elements
that can act as either registers or latches.
The three main signal paths are as follows:
•The input path carries data from the pad, which is bonded to a package pin, through
an optional programmable delay element directly to the I line. There are alternate
routes through a pair of storage elements to the IQ1 and IQ2 lines. The IOB outputs I,
IQ1, and IQ2 all lead to the FPGA’s internal logic. The delay element can be set to
ensure a hold time of zero.
•The output path, starting with the O1 and O2 lines, carries data from the FPGA’s
internal logic through a multiplexer and then a three-state driver to the IOB pad. In
addition to this direct path, the multiplexer provides the option to insert a pair of
storage elements.
•The 3-state path determines when the output driver is high impedance. The T1 and
T2 lines carry data from the FPGA’s internal logic through a multiplexer to the output
driver. In addition to this direct path, the multiplexer provides the option to insert a
pair of
storage elements. When the T1 or T2 lines are asserted High, the output driver is
high-impedance (floating, Hi-Z). The output driver is active-Low enabled.
All signal paths entering the IOB, including those associated with the storage elements, have
an inverter option. Any inverter placed on these paths is automatically absorbed into the
IOB.
There are three pairs of storage elements in each IOB, one pair for each of the three paths. It
is possible to configure each of these storage elements as an edge-triggered D-type flip-flop
(FD) or a level-sensitive latch (LD). The storage-element-pair on either the Output path or
the Three-State path can be used together with a special multiplexer to produce Double-
Data-Rate (DDR) transmission. This is accomplished by taking data synchronized to the clock
signal’s rising edge and converting them to bits synchronized on both the rising and the
falling edge.
4.4 Block RAM

All Spartan-3 devices support block RAM, which is organized as configurable, synchronous
18Kbit blocks. Block RAM stores relatively large amounts of data more efficiently than the
distributed RAM feature described earlier. (The latter is better suited for buffering small
amounts of data any-where along signal paths) The aspect ratio — i.e., width vs. depth — of
each block RAM is configurable. Furthermore, multiple blocks can be cascaded to create still
wider and/or deeper memories.

4.4.1 Arrangement of RAM Blocks on die

The XC3S50 has one column of block RAM. The Spartan-3 devices ranging
from the XC3S200 to XC3S2000 have two columns of block RAM. The
XC3S4000 and XC3S5000 have four columns. The position of the columns on
the die is shown in the following figure. For a given device, the total available
RAM blocks are distributed equally among the columns. The following table
shows the number of RAM blocks, the data storage capacity, and the number
of columns for each device.
4.4.2 Internal structure of the Block RAM
The block RAM has a dual port structure. The two identical data ports called A
and B permit independent access to the common RAM block, which has a
maximum capacity of 18,432 bits — or 16,384 bits when no parity lines are
used.
Each port has its own dedicated set of data, control and clock lines for
synchronous read and write operations There are four basic data paths, as
shown in the figure:
(1) Write to and read from Port A
(2) Write to and read from Port B
(3) Data transfer from Port A to Port B
(4) Data transfer from Port B to Port A.
5. Design Summary

Summary
ALARM Project Status

Project File: alarm.ise Current State: Placed and Routed

Module Name: alarm  Errors: No Errors

Target Device: xc3s400-4pq208  Warnings: 6 Warnings

Product Version: ISE 14  Updated: Mon 15. Aug 16:31:44 2017

ALARM Partition Summary

Partition Name Synthesis Status Placement Status Routing Status

/alarm Implemented

Device Utilization Summary

Logic Utilization Used Available Utilization Note(s)

Number of Slice Flip Flops 59 7,168 1%

Number of 4 input LUTs 125 7,168 1%

Logic Distribution

Number of occupied Slices 81 3,584 2%

Number of Slices containing only related logic 81 81 100%

Number of Slices containing unrelated logic 0 81 0%

Total Number 4 input LUTs 147 7,168 2%

Number used as logic 125

Number used as a route-thru 22

Number of bonded IOBs 29 141 20%

 IOB Flip Flops 19

Number of GCLKs 2 8 25%

Total equivalent gate count for design 1,605

Additional JTAG gate count for IOBs 1,392

Performance Summary

Final Timing Score: 0 Pinout Data: Pinout Report

Routing Results: All Signals Completely Routed Clock Data: Clock Report

Timing Constraints: All Constraints Met

Detailed Reports

Report Name Status Generated Errors Warnings Infos

Synthesis Report Current Mon 15. Nov 16:26:50 2010 0 4 Warnings 3 Infos

Translation Report Current Mon 15. Nov 16:28:04 2010 0 0 0

Map Report Current Mon 15. Nov 16:28:11 2010 0 0 3 Infos

Place and Route Report Current Mon 15. Nov 16:28:23 2010 0 2 Warnings 2 Infos

Static Timing Report Current Mon 15. Nov 16:28:27 2010 0 0 2 Infos

Bitgen Report

Secondary Reports

Report Name Status Generated

Xplorer Report
 5.1 Block Diagram

seg 0

clock red Clk 4MHz

seg 1
22 bits [6:0]
display
seg 2

seg 3

CS[4:0]
alarm alarm
min sec

at 1 KHz

alarm

at 1 second
speaker
½ second clock

Clk
4MHz
5.2 RTL Schematic

Level 1

Level 2
6. Working

Generating different frequencies' clock:

FPGA provides 4 MHz clock by default. to achieve 1 Hz clock we are taking 22 bit register
which can go upto 4194304 value which is approximately 4000000. The 22nd bit of this
register toggles its value at every .5 second and has frequency of 1HZ.
For getting 1 KHz frequency we take the 12th bit of the register which toggles after
every .5 ms.

Working of digital clock:

 We are taking four variable seg3 to seg-0 (from MSB to LSB).
 At every one second we just increment the value of seg-0. When seg-0 reach at 9
it makes seg-1 to increment by 1 and reset its own value to 0.
 When seg-0 reaches at 9 and seg-1 reaches at 5 we make seg-2 incremented by 1
and reset both seg-0 1nd seg-1 to 0. (This is because every minute have 60
seconds.)
 When seg-2 reaches at 9 and also sed-1 and seg-0 at 5 and 9 respectively then
seg-3 get incremented by 1.
 After every 60 minutes clock starts counting again from 0 second.
 There is a set alarm button given to make clock start from the beginning at any
point of time.

Seven segment display algorithm:

We are assigning the variables seg-3 - seg-0 to four seven-segment LEDs and then at
1 KHz frequency we show LEDs one by one in order to make it look continuous.

Alarm:
Total 12 input ports have been used in this to set alarm. Six ports to set seconds and
other six to set minutes. After setting values on this input port by pressing set key we
are fixing the alarm value in order to make it activated. Now at every second the
logic will check whether the set value matches with the current time of the digital
clock. When match happens an LED will become on and the speaker starts generating
volume of two different frequencies.
Speaker:
When the alarm match take place, a variable starts toggling at the desired frequency
rate for 0.5 second and for other 0.5 second that same variable changes its toggling
frequency to some other value. By this, we get two different values of frequency and
it sounds like a beep or siren. It goes on until we press reset alarm button.
7. Appendix

7.1 Verilog Code

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
/ Company:
/ Engineer:
/
/ Create Date: 16:55:38 11/15/2010
/ Design Name:
/ Module Name: alarm
/ Project Name:
/ Target Devices:
/ Tool versions:
/ Description:
//
/ Dependencies:
/
/ Revision:
/ Revision 0.01 - File Created
/ Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alarm(input clkip ,input [5:0] alarmsec ,input [5:0] alarmmin ,input set
,input rst ,input alarmrst ,output reg [6:0]display,output reg [3:0]cs=4'b0001 ,output
reg alarm = 0 ,output reg speaker = 0);

reg [21:0] clkreg = 0;

wire clkone = clkreg[21];
wire clk1kay = clkreg[11];

reg [5:0]min,sec;
reg [5:0]amin,asec;
wire [3:0]predisplay;
parameter clkdivider = 4000000/440/2;

reg [3:0] seg1 = 0,seg2=0 ,seg3=0,seg0 = 0;

assign predisplay = (~cs[3]&&~cs[2]&&~cs[1]&&cs[0])? seg0:
(~cs[3]&&~cs[2]&&cs[1]&&~cs[0])?seg1:(~cs[3]&&cs[2]&&~cs[1]&&~cs[0])?se
g2:seg3;

reg [14:0] counter;

always @(posedge clkip) if(counter==0) counter <= (clkreg[21] ? clkdivider-1 :
clkdivider/2-1); else counter <= counter-1;

always @(posedge clkip)

begin
if(alarm == 0)
speaker <=0 ;
else if(counter==0) speaker <= ~speaker;
end

always@(posedge set)
begin
amin = alarmmin;
asec = alarmsec;
end

always @ (posedge clkip)

begin
clkreg = clkreg + 1'b1;
end

//every one second

always @ (posedge clkone )
begin
min = seg3*4'b1010 + seg2;
sec = seg1*4'b1010 + seg0 + 1;

if(alarm == 0 && min == amin && sec == asec)

begin
alarm = 1;

end
 if(rst == 0)begin seg0 = 0; seg1 = 0; seg2 = 0;seg3 = 0;end

if(alarmrst == 0) begin alarm = 0; end

if(seg3 == 5 && seg2 == 9 && seg0 == 9 && seg1 == 5)

begin
seg3 = 0;
seg2 = 0;
seg1 = 0;
seg0 = 0;
end

else if(seg2 == 9&&seg0 == 9 && seg1 == 5)

begin
seg3 = seg3 + 1;
seg2 = 0;
seg1 = 0;
seg0 = 0;
end

else if(seg0 == 9 && seg1 == 5)

begin
seg2 = seg2 + 1;
seg1 = 0;
seg0 = 0;
end

else if(seg0 == 9)
begin
seg1 = seg1+1;
seg0 = 0;
end

else seg0 = seg0+1;

end

// for the seven segment display

always @ (posedge clk1kay)
begin
cs = {cs[2],cs[1],cs[0],cs[3]};
case(predisplay)

4'b0000: display = 7'b1111110;

4'b0001: display = 7'b0110000;
4'b0010: display = 7'b1101101;
4'b0011: display = 7'b1111001;
4'b0100: display = 7'b0110011;
4'b0101: display = 7'b1011011;
4'b0110: display = 7'b1011111;
4'b0111: display = 7'b1110000;
4'b1000: display = 7'b1111111;
4'b1001: display = 7'b1110011;
default: display = 7'b0000000;
endcase
end
endmodule
8 Conclusions
Again, the clock’s display is fully functional. It is capable of using the all four digits of the seven-
segment display and the board mounted am/pm LED indicator.

Design Steps:

Completed:

1. Extensive internet research of alarm clock design

2. Obtain a thorough understanding of the Xilinx clock code (Digital Clock using Multiplexed
7-Segment Display) obtained at: http://www.xilinx.com/products/boards/DO-SPAR3-
DK/reference_designs.htm
3. Begin to adding useful comments into the clock.vhdl code.
4. Change clock to display hh::mm format
5. Develop a state machine ideas for clock
6. Successful FPGA board implementation
7. Develop a set-time FSM
8. Create a up minutes process to increment the minutes
9. Write a VHDL test bench
9 References

Digilent Inc.

http://www.digilentinc.com/

Digital Clock using Multiplexed 7-Segment Display:

The original code for this project was written by Xilinx and can be found at the following
website:

http://www.xilinx.com/products/boards/DO-SPAR3-DK/reference_designs.html