Exercise :: Combinational Logic

Analysis - General Questions

1 Referring to the GAL diagram, which is the
. correct logic function?

A.

B.

C.

D. None of these
Answer: Option C

4. The 8-input XOR circuit shown has an

output of Y = 1. Which input combination
A. below (ordered A – H) is correct?

B.

C.

D.
Answer: Option A

2. The output of an exclusive-NOR gate is 1.

Which input combination is correct?
A. A = 1, B = 0

B. A = 0, B = 1

C. A = 0, B = 0

D. none of the above A. 10111100

Answer: Option C
B. 10111000

C. 11100111
3. The Boolean SOP expression obtained
from the truth table below is ________. D. 00011101
 Answer: Option A

5 Implementing the expression AB + CDE

. using NAND logic, we get:

A. 2-input AND gate

B. 2-input OR gate

C. Exclusive-OR gate

D. None of the above

Answer: Option B

8. Implementing the

expression with
NOR logic, we get:

A. (A)

B. (B)

C. (C)

D. (D)
Answer: Option A

6. Before an SOP implementation, the

expression would
require a total of how many gates?
A. 1

B. 2

C. 4

D. 5
Answer: Option D

7. The following waveform pattern is for a(n) A. (A)

________.
B. (B)

C. (C)
 D. (D) 12. One positive pulse with tw = 75 µs is
applied to one of the inputs of an
Answer: Option A exclusive-OR circuit. A second positive
pulse with tw = 15 µs is applied to the
other input beginning 20 µs after the
9. A 4-variable AND-OR-Invert circuit leading edge of the first pulse. Which
produces a 0 at its Y output. Which statement describes the output in relation
combination of inputs is correct? to the inputs?

A. The exclusive-OR output is a 20 s

pulse followed by a 40 s pulse,
A.
with a separation of 15 s between
B.
the pulses.
C. The exclusive-OR output is a 20 s
pulse followed by a 15 s pulse,
D. none of the above B.
with a separation of 40 s between
Answer: Option C the pulses.

The exclusive-OR output is a 15 s

C.
pulse followed by a 40 s pulse.
10. The following waveform pattern is for a(n)
________. *The exclusive-OR output is a 20
D. s pulse followed by a 15 s pulse,
followed by a 40 s pulse.
Answer: Option D

13. How many AND gates are required to

A. 2-input AND gate implement the Boolean
B. 2-input OR gate expression, ?
A. 1
C. Exclusive-OR gate
B. 2
D. None of the above
Answer: Option C C. 3

D. 4
11. To implement the Answer: Option C
expression , it
takes one OR gate and ________.
14. How many NOT gates are required to
three AND gates and three
A. implement the Boolean
inverters
expression, ?
B. three AND gates and four inverters
A. 1
C. three AND gates
B. 2
D. one AND gate
C. 4
Answer: Option A
D. 5
 Answer: Option B

15. The inverter can be produced with how

many NAND gates?
A. 1

B. 2

C. 3

D. 4
Answer: Option A

16. A 4-variable AND-OR circuit produces a 0

at its Y output. Which combination of
inputs is correct?
A. A = 0, B = 0, C = 1, D = 1

B. A = 1, B = 1, C = 0, D = 0

C. A = 1, B = 1, C = 1, D = 1

D. A = 1, B = 0, C = 1, D = 0
Answer: Option D

17. A 4-variable AND-OR circuit produces a 1 A. (A)

at its Y output. Which combination of
inputs is correct? B. (B)

A. A = 0, B = 0, C = 0, D = 0 C. (C)

B. A = 0, B = 1, C = 1, D = 0 D. (D)

C. A = 1, B = 1, C = 0, D = 0 Answer: Option D

D. A = 1, B = 0, C = 0, D = 0
Answer: Option C 1 Implementing the
9. expression using NAND logic,
we get:
18. Implementing the

expression using NAND

logic, we get:
 three AND gates, one NOT gate,
C.
three OR gates

D. three AND gates, three OR gates

Answer: Option B

22. One possible output expression for an

AND-OR-Invert circuit having one AND
gate with inputs A, B, and C and one AND
gate with inputs D and E is ________.
A.

B.
A. (A)
C.
B. (B)
D.
C. (C)
Answer: Option C
D. (D)
Answer: Option B
23. How many 2-input NOR gates does it take
to produce a 2-input NAND gate?
20. The following waveform pattern is for a(n) A. 1
________.
B. 2

C. 3

D. 4
Answer: Option D
A. 2-input AND gate

B. 2-input OR gate 24. A logic circuit with an

C. Exclusive-OR gate output consists of

________.
D. None of the above two AND gates, two OR gates, two
A.
Answer: Option A inverters

three AND gates, two OR gates,

B.
21. Implementation of the Boolean one inverter
expression results in
two AND gates, one OR gate, two
________. C.
inverters
A. three AND gates, one OR gate
D. two AND gates, one OR gate
three AND gates, one NOT gate,
B. Answer: Option C
one OR gate
Exercise :: Combinational Logic
Analysis - True or False
7. An exclusive-OR gate's output is HIGH
1. The output of a NAND gate is LOW when when its inputs are equal.
all inputs are HIGH at the same time.
A. True
A. True
B. False
B. False
Answer: Option B
Answer: Option A

8. A VHDL component is a predefined logic

2. When the output of an AND-OR circuit is function.
complemented, it results in an AND-OR-
Invert circuit. A. True

A. True B. False

B. False Answer: Option B

Answer: Option A
9. The output of an AND gate is HIGH when
any input is HIGH.
3. If one input to a 2-input AND gate is
HIGH, the output reflects the other input. A. True

A. True B. False

B. False Answer: Option B

Answer: Option A
10. A NOR gate's truth table is the opposite of
that of an OR gate.
4. A NAND gate can function as a negative-
OR gate. A. True

A. True B. False

B. False Answer: Option A

Exercise :: Combinational Logic
Answer: Option A Analysis - Filling the Blanks
1. Assume you have A, B, C, and D
available but not their complements. The
5. An AND gate is a universal gate. minimum number of 2-input NAND gates
A. True required to implement the
equation is ________.
B. False
A. 3
Answer: Option B
B. 4
6. A NOR gate is a universal gate. C. 5
A. True
D. 6
B. False Answer: Option C
Answer: Option A
 C. XOR gate
2. The symbol shown represents a(n)
D. XNOR gate
________.
Answer: Option A

A. AND gate 6. If both inputs of a 2-input NOR gate are

connected, the gate will function as an
B. OR gate ________.

C. NAND gate A. OR gate

D. NOR gate B. AND gate

Answer: Option D C. inverter

D. any of the above

3. A gate can drive a number of load gate Answer: Option C
inputs up to its specified ________.
A. supply voltage
7. Assume that you have a 3-input NAND
B. noise margin gate but need only a 2-input gate. The
unused input should be ________.
C. fan-in
A. connected to ground
D. fan-out
B. left open
Answer: Option D
C. connected to a HIGH

D. any of the above

4. The expression can be directly
implemented using only ________. Answer: Option C
A. an XOR gate

B. an XNOR gate 8. A node is defined as ________.

A. a common point in a circuit
C. an AOI circuit
a circuit implemented as a sum-of-
D. three 2-input NAND gates B.
products
Answer: Option C
C. the output signals from a circuit

D. a shorted input
5. The symbol shown represents ________.
Answer: Option A

9. Using the universal property of a NAND

gate, one or more NAND gates can be
used to replace an ________.
A. AND-OR logic
A. OR gate
B. AOI logic
 B. AND gate

C. inverter

D. any of the above

Answer: Option D

10. The expression can be directly

implemented using only ________.
A. an XOR gate

B. an XNOR gate

C. an AOI circuit

D. three 2-input NAND gates

Answer: Option A