CHAPTER -1

INTRODUCTION

With the tremendous progress of modern electronic system and the evolution
of the nanotechnology, the low- power &high speed microelectronic device has come
to the forefront. Now a day, as growing applications (higher complexity),speed and
portability are the major concerns of any smart device it demands small-size, low-
power high through put circuitry. So, sub circuits of any VLSI chip needs high speed
operation along with low-power consumption. Now a day logic circuits are designed
using pass transistor logic techniques. In PTL based VLSI chips MOS switches are
used to propagate different logic values in various node points, as it reduces area and
delay as compared to any other switches type.

It reduces the number of MOS transistors used in circuit, but it suffers with a
major problem that output voltage levels is no longer same as the input voltage level.
Each transistor in series has a lower voltage at its output than at its input. In order to
minimize sneak paths, charge sharing, and switching delays of the circuit all the sub-
circuit component has to be arranged obeying the VLSI design rules. Ensuring this
simulation of circuit schematics provides a platform to verify Circuit performance.

To get better speed and power consumption results lot of approaches have
been recently proposed. Among them, two have been established by Hitachi CPL and
DPL. In1993 Hitachi demonstrated a 1.5ns 32-bit ALU in 0.25μmCMOS technology
and 4.4ns 54X54 bit multiplier using DPL technique. Like Pass Transistor Logic
(PTL), Domino logic, NORA logic, Complementary Pass Logic (CPL), Differential
Cascade Voltage Switch (DCVS), MOS Current Mode Logic (MCML), Clocked
CMOS (C2MOS) etc. are also different approach for reducing the circuit power.

In 2002, A. Morgenshtein, A. Fish, and Israel A.Wagner introduced a new

method for low-power digital combinational circuit design known as Gate Diffusion
Input(GDI) .The main purpose of this work is to implement a low power GDI based
full adder & to draw a detailed comparative study with a CMOS full adder. The
purpose of implementing the low power full adder is to show that using fewer
numbers of transistors in comparison to the conventional full adder, the propagation
delay time & power consumption gets reduced. It also helps in reducing the layout
area thereby decreasing the entire size of a device where this adder is used. Power

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consumption is becoming the major tailback in the design of VLSI chips in modern
process technologies. These are evaluated from an industrial product development
perspective.

1.1 OBJECTIVE/AIM OF THE STUDY:

Power consumption has recently become a major design issue due to the
rapid growth in the technology of mobile communications and other portable
applications using portable power supplies. The need for low power dissipation
systems has motivated the development of power efficient designs for basic cells.
The most challenging part is to maintain the high performance while attempting to
reduce the consumed power. Several techniques exist to keep power dissipation to a
minimum.

This objective can be achieved at different design levels such as the

algorithmic, architecture and circuit level. This paper is concerned with power
optimization at the circuit level. With the tremendous progress of modern electronic
system and the evolution of the nanotechnology, the low- power & high speed
microelectronic devices have come to the forefront. Now a day, as growing
applications (higher complexity), speed and portability are the major concerns of any
smart device it demands small-size, low-power high throughput circuitry. So, sub
circuits of any VLSI chip needs high speed operation along with low-power
consumption. Now a day logic circuits are designed using GATE DIFFUSION
INPUT (GDI) technique.

1.2 VLSI INTRODUCTION:

Very-large-scale integration (VLSI) is the process of creating integrated

circuits by combining thousands of transistor-based circuits into a single chip. VLSI
began in the 1970s when complex semiconductor and communication technologies
were being developed. The microprocessor is a VLSI device. The term is no longer
as common as it once was, as chips have increased in complexity into the hundreds
of millions of transistors.

1.2.1 HISTORY:

The first semiconductor chips held one transistor each. Subsequent advances
added more and more transistors, and, as a consequence, more individual functions
or systems were integrated over time. The first integrated circuits held only a few
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devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making
it possible to fabricate one or more logic gates on a single device. Now known
retrospectively as "small-scale integration" (SSI), improvements in technique led to
devices with hundreds of logic gates, known as large-scale integration (LSI), i.e.
systems with at least a thousand logic gates. Current technology has moved far past
this mark and today's microprocessors have many millions of gates and hundreds of
millions of individual transistors.

At one time, there was an effort to name and calibrate various levels of large-
scale integration above VLSI. Terms like Ultra-large-scale Integration (ULSI) were
used. But the huge number of gates and transistors available on common devices has
rendered such fine distinctions moot. Terms suggesting greater than VLSI levels of
integration are no longer in widespread use. Even VLSI is now somewhat quaint,
given the common assumption that all microprocessors are VLSI or better.

The invention of transistor by William Shockley and his colleagues at bell

laboratories, Murray hills, NJ, ushered in the “solid state” era of electronic circuit
and system. Within few years after the invention, transistor were commercially
available and almost all electronic system started carrying the symbol “solid state,”
signifying the conquest of the transistor over its rival-the vacuum tube. Smaller size,
lower power consumption, and higher reliability were some of the reasons that made
it a winner over the vacuum tube. About a decade later, Shockley and his colleagues,
John Bardeen and Walter Brattain, of Bell laboratories were rewarded with a noble
prize for their revolutionary invention. The tremendous success of the transistor led
to vigorous research activity in the field of microelectronics. Later, Shockley founded
a semiconductor.

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 Name Signification Year Transistor Logic gates number
Number

SSI Small-scale 1964 1to 10 1 to 12

Integration

MSL Medium- 1968 100 to 500 13 to 19

Scale
Integration

LSI Large-scale 1971 500 to 20000 100 to 9999

Integration

VLSI Very large 1980 20000 to 10000 to 99999

Scale 1000000
Integration

ULSI Ultra-large 1984 1000000 and 100000 and more

Scale More
Integration

TABLE: 1.1 IC TECHNOLOGIES

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1.3 VLSI DESIGN FLOW:

System Specifications

Functional (architecture ) Design

Functional Verification

Logic Design

Logic Verification

Circuit Design

Circuit Verification

Physical Design

Layout Verification

Fabrication and Testing

Fig:1.1: VLSI design flowchart

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 IC’s are made on a thin circular silicon wafer. Each wafer contains hundreds
of dies. They are one twenties or more layers or mask layers that define the
functionality of each die.

A full custom IC design is the design methodology. The designers first

begins at transistor level progresses to design schematics then to circuit simulation
(spices simulation)m and finally the proven transistor schematic is handed to layout
designers. The layout designers then take the schematics and draw out mask with IC
layout tools. The finally verified layout is converted to a stream file format (GDS)
and send to mask shop. This stage is called tape-out. This full custom design is good
for mixed signals or analog design projects.

A semicustom design is a IC design methodology. That utilizes set of pre

qualified pre layout cells (called standard cells) and perform placement and coating
of those cells. To come out of a complete chip based on net list that logic designer
provide for large design chip semicustom design methodology will save layout time
by not only using the prelayout cells but also with automation tools.

First a schematic view of circuit is created by using specific we have derived

them that circuit is simulated if the schematic is simulated then we go for the next
step ie., creating layout. If we get errors while simulation we go back to the step
schematic entry and does some modifications and then simulation.

One circuit specifications are fulfilled in simulation the layout is created the
resulting layout must verified some geometric cells. Dependent on the technology
(design rules) design rule check is performed then the layout should be compared to
the schematic to ensure that the intended functionality is implemented. These can be
done with us check. Finally a netlist including all layouts parasitic should be
extracted and finally simulation of these netlist should be made. This is called post
layout simulation. Once the layout functionality is verified, finally layout is
converted to a certain standard file format using the translate tool. Full custom and
handcrafted IC design is the process of creating on IC by manually creating and
editing each polygon. Full custom layout generally gives the most compact design.

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Schematic Entry:

Before we create the physical layout data for an IC we must create schematic
for our design. A schematic is a graphical and behavioral description of a circuit
which can be as simple as a paper copy the design for logic source for our layout
that can be either electronic design data model. Design view point that we create
with design architect. IC and design view point editor or a netlist.

Transistor level schematic:

The traditional method for describing our transistor level is via design
architect window. Design architect provide simply infusive means to draw to place
and to connect it individual components that makeup our design. The resulting
schematic drawing must accurately describing the main electrical power of all
components and their interconnects. The generation of complete circuit schematic is
therefore the first important step for format design flow.

Simulation:

The process of modeling exercising and analyzing the behavior of electronic

design without the ownership cost of the physical hardware is called simulation.
After the description of the transistor level schematic is completed. The electrical
performance and functionality of the circuit must be verified using simulation tool.
Based on simulation results the designer usually modifies some of the device
properties in order to optimize the performance. The initial simulation phase also
serves to detect some of the design errors that many have been created during the
schematic entry step. The second phase of the simulation will follow the extraction
of a mask layout (post layout simulation) to accurately access the electrical
performance of the completely design.

Layout:

The creation of mask layout is one of most important steps in full custom
design flow. Where the designer describes the detailed geometry and relative
positioning of the each mask layers to be used in actual fabrication it extremely
important that the layout design must not violate many of the3 layout design of
fabricating process. In order to ensure a high probability of defect for a fabrication
of all fitness describing in mask layout. It is also important to extract the netlist and

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laying the layout view for two main purposes this allows comparing it with the
netlist extract from the schematic. This layout Vs schematic ensures that the layout
actually implements the required functionality if the extraction program allows to
extract parasitic allows from layout view a more accurate, post layout. Simulation
can be performed taking into account the geometry of the circuit. The detailed mask
layout requires a very intensive and time consuming design effort, so that automatic
tool employed as much as possible. Once our layout is completed a design rule
check is performed to enforce this point.

1.4 Verification:

Layout verification is the process of interpreting the physical layout the data
to determine whether it conforms the physical design. Rules and source schematic
as well as extracting parasitic information we can see with simulators to determine if
the design performance according to specifications.

Design rule check (DRC):

The checked mask layout must confirm to a complex set of design rules,
inorder to ensure a lower probability of fabrication defects. A tool built into a caliber
of called “Run DRC” is used to detect any design rule violations during and after the
mask layout design. The defected errors are displayed on the layout editor window
as error markers and the corresponding rule is also displayed in separate window.
The designer must perform DRC and make sure that all layout errors usually
removed from the mask layout before the final design is saved.

Layout Vs Schematic:

Once the layout fulfills all the design rules the next verification step follows.
The netlist behind the layout view is extracted and compared to that of a schematic
view. This is called Layout Vs Schematic comparison and is detail level simulation.
The tool layout schematic will compares the original network with one extracted
from the mask layout and prove that two networks are indeed equivalent. The LVS
should be corrected in the mask layout. After successfully LVS, we will have two
main cell views for the same circuit. Since both of these view refer to the same
circuit they can be interchanged. Once performed these verification steps at
hierarchal level our design is ready to submit to foundry.

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Post Layout Simulation:

The final step in the design process is post layout simulation. In this section,
we will see if the circuit as desired timings and derive characteristics that we hope
for. The electrical performed of a full custom design can be best analyzed by
performing a post layout simulation on expected circuit net list. At this point, the
designer should have a complete mask layout intended circuit and should have
passed DRC and LVS steps with no violations.

Parasitic Extraction (PEX):

Parasitic extraction is used to identify the parasitic that are present in the final
layout in meeting. The required functionality Calibrie PEX is a separate program
which will extract information about the connectivity and associated capacitances,
resistances in our layout. The calibre PEX setup inform will be saved. However, so
we only needed to enter it once. The calibre PEX extraction tool; reads in our layout
from a GDS II file and create a spice netlist file suitable for simulation.

1.5 NEED OF ADDERS:

Today demand and popularity of the battery- operated portable devices such
as cellular phone, laptop computers, tablet and personal digital assistant (PDA) is
increasing that depends on high speed, small size, high reliability, low power
consumption and longer battery life that demand for VLSI. Full adders, being one of
the most fundamental building blocks of all the aforementioned circuit applications,
remain a key focus domain of the researchers over the years.

1. Basic building block of on-chip libraries.

2. Configured according to desired complexity of arithmetic and numeric
computations.
3. In processors and other kinds of computing devices, adders are used in the
arithmetic logic unit.
4. Adders also use in other parts of the processor, where they are used to
calculate addresses, table indices, and similar operations.

1.6 SOFTWARE REQUIREMENT:

MENTOR GRAPHIS:130nm

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ELDO Simulator

Tool Introduction:

The evaluation of integrated circuit fabrication in a unique fact in the history

of modern industry. They have been studied improvement inte4rms of speed, density
and cost for more than 30 years. The push for smaller size, reduced power supply
consumption and enhancement of services as resulted in continuous technological
advances with the possibility of ever higher integration.

Originally IC were designed at the layout level with the help of logic design
tools to achieve design complexity of around 10,000 transistors. The basic design
flow for IC design is shown with different logic device tools shown in figure. The
tools are :

1)Mentorg (DA-IC) for schematic entry.

2)Mentorg (eldo) for simulation

3)Mentorg (IC Station) for layout design

4)Mentorg (calibre) for LVS,DRC,PEX.

The description of each block is as follows:

1.6.1 Design architect IC:

Design architect is more than a computer aided schematic capture

applications it is a multi level design environment that includes

1)A schematic editor and

2)Symbol editor.

As shown in the figure, the design architect is the centre of activity for
most mentorgraphic design process. Design architect let us to create and edit logic
designs that are used by downstream process.

Design architect offers a collection of functionality which is summarized in the

following list

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1)Schematic capture

2)Symbol creation

Schematic capture:

Schematic capture is the process of drawing a schematic with a computer and

storing it so that it can be used in other process simplest form we can think of work
station. Schematic drawn by design archit4ect can improve more than simple wiring
diagram. The design architect schematic editor is used to capture schematic
information.

Symbol creation:

Design architect allows us to create and modify analog and digital logic
symbol that can be used in other design architect schematic designs. Symbols can
represent basic design elements such as logic gates, transistors or a complete board
design that represents a portion of total design effort. The design architect symbol
editor is used to create symbols.

Design architect environment:

We have to access two editors within design architect environment.

1) Schematic editor to create schematics.

2) Symbol editor to create user defined symbols.

Each editor operates in its own window within the session window.

1.6.2 Design architect session window:

The design architect session window can be invoked from the design
manager tool window by double clicking on the design architect icon. After the
design architect session window is activated, design architect editing windows can
be opened using design architect pop up menu items, function key (or) palate icons.

The most commonly used schematic editor window palates and menus include
command to

1. Instantiate components.

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 2. Create and modify properties.
3. Create and modify nets.
Set up templates for creating nets, comment grids.

1. Create and edit comment graphics and text.

2. Edit objects moving, copying, deleting, connecting) and checks
schematic errors.
3. Save and register schematic.
The most commonly used symbols editor commands.

1) Create symbol body graphics

2)Edit objects (moving,copying,deleting)

3)Add pins and properties to the symbol

4)Check symbols for errors

5)Save and register a symbol.

1.6.3 Elements of a schematic:

A schematic is a graphical behavioral description of a circuit. Schematics are

built by combining and connecting electrical objects together.

A schematic can contain the following elements.

1) Instances of logic symbols.

2) Nets
3) Property name/value.

1.6.4 Build a schematic:

A schematic may include many instances wires and buses connecting the
instances to build a simple schematic involves following steps.

1) Open a schematic editor window.

2) Draw a schematic

3) Check schematic for errors

4) Register schematic with component

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Draw the schematic:

Here are the basic steps that allow us to draw a simple circuit.

1)Choose and place components.

2)Draw and route nets

3)Terminate off sheet nets

4)Name nets.

Check the schematics:

We may pass a set of required mentorgraphic schematic checks before a

downstream application is invoked, if these checks falls, the downstream application
will issue a warning, highlighting a problem that may be uncovered at a later time.

Definition:

The symbol editor creates symbols model. A symbol model is a graphical

representation of a component. A symbol consists of four basic element.

1) Body shape: The symbol body is the graphical image of a symbol.

2) Pins: Pins are points where an instant of the symbol electrically

connected to schematic sheet.

3) Origin: The origin is the reference point used to place the symbol on
schematic sheet.

4) Properties: Properties provide information describing the functionality of

the symbol.

Symbol from a schematic:

Design architect can create a symbol to represent a schematic sheet. When

we choose the mislaneous Generate symbol menu items while in the schematic editor
a dialogue box is displayed for us to specify the name of symbol that will be created.
The symbol can be generated from the currently open schematic sheet on another
sheet or a pin list.

Checking a symbol for errors:

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 Once a symbol has been drawn, pins placed and properties added, the last
step before saving and registering symbol is to check the symbol for errors. All
symbols must pass a set of required checks before the symbol can be placed on
schematic sheet.

HIIIIIIII

1.6.5 IC Station:

IC Station is the mentor software tool that performs IC layout it is possible to

layout IC’s completely by hand, where each polygon for each mask is done
explicitly.

What is an IC Station:

A total design solution which provides complete analog/mixed IC design

flow. From schematic capture to physical layout and verification. IC station is the
mentorgraphics layout editing software toolset. The specific tool used in this course
include.

IC graph:

The interactive layout editor and tool interface IC station tool set.

1)Used for polygon editing.

2)Supports extensive set of editing functions for efficient polygon editing.

IC Station SDL Bundle:

1)It consists of IC-SDL,IC Eco and IC Short checker tools.

2)Includes all the functionality of basic editor module.

3) Reduces layout risk by using SDL option.

IC Station SDL:

Pick and place devices either automatically or graphically. The

dynamic connectivity display with cross probing makes navigation between the
layout and schematic fast and easy. Connectivity shorten LVs debug cycles, enobling
designers in creating LVs correct layout.

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 1) Accelerated custom layout.
2) Advanced support for Eco’s.
3) Shorten LVs debug cycles with short checker.
IC Short checker:

1) IC Short checker finds connectivity errors before running LVs.

2) Finds overlapping and attributes nets with different names.
3) Only checks for shorts at one level of hierarchy.
4) Pin points the location of shorts better than LVs.
IC Device:

Device generators generates standard device types included generators.

MOS, Resistors, capacitors, inductors, vias Guard bonds.

IC Route:

1)Interactive routing solution

2)Easy routing of signals.

3)Maintain full control of critical signals during cell level and top level routing.

IC ECO:

ECO describes a change or changes mode within a large system, such as the
logic that drives an IC layout.

With IC graph, ECO classifies the change and compares the old to the new and
makes the most of the changes for layout devices.

IC Rules:

A set of functions callable within IC graph that lets us to perform design rule check
(DRC).

IC Trace:

A set of functions callable within IC graph that let us perform layout vs

schematic verification.

IC Blocks:

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 A set of functions callable from within IC Graph that let us perform cell outs
placement and in connect routing.

IC extract:

A set of functions callable from within IC graph that let us perform parasitic
capacitance or resistance extraction and back annotation.

1.6.6 Calibre:

We can verify the physical electrical integrity of our IC Designs and then
view and debug the re4sults using calibre interface in IC station using the calibre
pull down menu from IC cell window, we can perform flat or hierarchal processing
and display the results.

Calibre DRC:

Calibre DRC an edge based design rule checking system works with
polygons edges. When an IC designer creates layers calibre DRC checks the edges
located an those layers by reading the database flat and operating on resulting flat
geometrics.

Calibre LVS:

Calibre LVS performs flat and hierarchal layout LVs comparisons. LVS
processing consisting of connectivity, extraction and device recognisation.
Discrepancies between the layout and schematic appear in LVS report, showing the
differences between circuits from both a source and a layout perspectives. These two
perspectives allows us to compare all possible views.

Using the IC session calibre menu.

The calibre pulldowns menus in the IC cell window is shown in figure

provides us with quick access to the calibre tools. From this menu, we can invoke the
calibre DRC LVS and PEX windows through which we can check the conditions and
compare number of parts and nets in layout and schematics also we can predict
parasitic.

Using calibre run PEX:

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 The calibre run PEX menu item invokes the calibre interactive PEX GUI an
interface to the calibre PX-C/PX-RC or the flat extraction mode.

Using calibre – RUN DRC:

The calibre RUN DRC menu item displays the setup calibre dialogue box.
We use this dialogue box to enter the path to calibre software free. The calibre DRC
window allows to specify options and selected rule file statements that execute the
desired calibre DRC functionality.

Using calibre Run LVS:

After we specify the path to calibre free and execute the dialoguebox, the
calibre interactive LVs dialogue ox displays. Calibre uses a TCD socket to
communicate with calibre RVE and caliber interactive tolls. Calibre attempts to
initialize a server sockets at port 9189, which is default IPC port number present in
set up calibre dialogue box.

The most commonly used symbols editor commands.

1)Create symbol body graphics

2)Edit objects (moving, copying, deleting)

3)Add pins and properties to the symbol

4) Check symbols for errors

5)Save and register a symbol.

6)Set up templates for creating nets, comment grids.

7)Save and register schematic.

8)Create and edit comment graphics and text.

9)Edit objects moving, copying, deleting, connecting) and checks schematic errors.

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 CHAPTER 2

LITERATURE SURVEY

As the technology and time advances the demand of low power and fast operating devices
is increasing. Full adder is the basic combinational element of the electronics industry. For the
fast operation of the signal processing integrated circuits (ICs), the basic algorithms such as
convolution, multiplication, swapping etc. must be fast as much as possible. Full adder is the
basic arithmetic circuit which is used in almost all algorithms. Based on logic styles being used,
the designs of adder circuits are basically divided into two categories, (1) static and (2) dynamic
style. The choice of using static or dynamic logic is dependent on many criteria than just its low-
power performance, delay, testability, area and ease of design.

Static full adders show more reliability and simplicity with lesser energy requirement, but the on
chip area requirement is usually more as compared to dynamic logic based adders [1],

[2]. Whereas, dynamic full adders have some advantages over static full adders like fast
switching speed, output having full swing voltage levels, no static power consumption etc. [1],
[2].

There are many drawbacks related to static full adders i.e. performance, delay, power
consumption in which delay and power are the main area of concern. So to improve the power

and delay of the ICs, full adder should consume the minimum power and have the lowest delay.
Thus, power and delay are the vital resources of an added. Hence, optimizing these parameters
has been the interesting topic for researchers and low power very-large scale integrated circuit
(VLSI) designers over the years [9]-[10]. So designers try to save the power and lessen the delay.

Power is one of the main resources of digital circuits hence design engineers try to save
it. Switching activity, size of the transistor, intermediate node capacitances (diffusion, gate and
wiring capacitances) are main resources of power dissipation in CMOS circuits [1]. At the device
level power dissipation can be reduced by reducing the level of supply voltage and threshold
voltage. However, lower supply voltage increases the delay problem and degrades the drivability
of cascaded cells where as threshold voltage reduction increases the standby leakage currents.

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 Transistor sizing is one of the best techniques to reduce power consumption [1], [2]. By
selecting the optimum width to length (W/L) ratio of every individual transistor we can succeed
in power saving [8]. In context to the single bit full adder design, various design techniques were
investigated and compared with the new design [1]-[9].

Every design tends to favour one parameter at the cost of others. On the basis of output, full
adder cells are mainly classified into two types. Transmission gate full adder(TGA),
complimentary pass transistor logic (CPL), static complimentary metal-oxide-semiconductor
(CMOS), dynamic CMOS, transmission function full adder (TFA), 14T and 16T full adders[5]-
[7], [3], [16] lie under first type which have the full swing output voltage level. The second type
(10T, 9T, 8T Full adders) is a group of full adders without full swing output [14], [16]-[19]. The
group of first type full adders is having more number of transistors, high power consuming, large
area as compared to second type. Complimentary CMOS, dynamic CMOS, CPL, TGA are the
main conventional logic designs [1]-[2]. Complimentary CMOS (C-CMOS) is having the
advantage of robustness against voltage scaling and arbitrary transistor sizing which is
responsible for its reliable operation at low voltage while the disadvantages of C-CMOS are
requirement of buffers, more number of transistor count (28T) and capacitances at input level [1].
Carry propagation delay of C-CMOS adder was reduced in Mirror adder design [2] with same
power consumption and transistor count. CPL shows a better voltage swing restoration by the use
of 32 transistors but higher switching activity of intermediate nodes, over loading of inputs, high
transistor count makes it inappropriate e for low power applications [5], [7]. The main drawback
of CPL is voltage degradation problem which was overcome in TGA with twenty transistors
(20T) only [6], [8]. Other drawbacks of CPL are high power consumption and slow speed which
remain a concern for designers. To overcome these problems later hybrid design styles were
employed. Hybrid design contains more than one logic styles [11]-[14]. 14T full adder [3] and
hybrid logic with static CMOS output drive full adder (HPSC) [4] are hybrid adders. Although
these hybrid logic styles provide the full swing output but the poor driving capability makes them
inappropriate for cascaded mode of operation.

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 CHAPTER 3

EXISTENCE DESIGN

This implementation will ultimately reduce the circuit complexity and, hence, save chip
area. Also ,we identify two separate sub- networks consisting of several gates (highlighted with
dashed boxes) which will be utilized for the transistor-level realization of the full-adder circuit.

For translating the gate-level design into a transistor-level circuit description, we note
that both the sum-out and the carry-out function are represented by nested AND-OR-NOR
structures. Each such combined structure (complex logic gate) can be realized in CMOS as
follows: the AND terms are implemented by series-connected NMOS transistors, and the OR

FIG 3.1: BASIC 28 CONVENTIONAL TRANSISTORS

terms are implemented by parallel-connected NMOS transistors. The input variable are applied to
the gates of the NMOS (and the complementary pmos) transistors. Thus, the NMOS net may
consists of nested series-parallel connections of NMOS transistor s between the output node and
the power supply, is obtained as the dual network of the NMOS net. The resulting transistor-level

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design of the CMOS full-adder circuit. Note that the circuit contains a total of 14 NMOS and 14
PMOS transistors, together with the two CMOS inverters which are used together with the two
CMOS inverters which are used to generate the outputs.

A B C SUM CARRY

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

TABLE 3.1 TRUTH TABLEOF 1-BIT FULL ADDER

In this specific example, it can also be shown that the dual (PMOS) network is actually
equivalent to the NMOS network for both the sum _out and the carry _out functions, which leads
to a fully symmetry circuit topology .The alternate circuit diagram obtained by applying this
principle of symmetry. Note that the Boolean functions realized by the circuit are identical; yet
the symmetric circuit topology significantly simplifies the layout.

3.1 RIPPLE CARRY ADDER

Multiple full adder circuits can be cascaded in parallel to add an N-bit number. For an N-
bit parallel adder, there must be N number of full adder circuits. A ripple carry adder is a logic
circuit in which the carry-out of each full adder is the carry in of the succeeding next most
significant full adder. It is called a ripple carry adder because each carry bit gets rippled into the
next stage. In a ripple carry adder the sum and carry out bits of any half adder stage is not valid
until the carry in of that stage occurs. Propagation delays inside the logic circuitry is the reason
behind this. Propagation delay is time elapsed between the application of an input and
occurance of the corresponding output. Consider a NOT gate, When the input is “0” the output
will be“1” and vice versa. The time taken for the NOT gate’s output to become “0” after the

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application of logic “1” to the NOT gate’s input is the propagation delay here.Similarly
the carry propagation delay is the time elapsed between the application of the carry in signal and
the occurance of the carry out (Cout) signal. Circuit diagram of a 4-bit ripple carry adder is
shown below.

Fig 3.1 ripple carry adder

Sum out S0 and carry out Cout of the Full Adder 1 is valid only after the propagation delay of
Full Adder 1. In the same way, Sum out S3 of the Full Adder 4 is valid only after the joint
propagation delays of Full Adder 1 to Full Adder 4. In simple words, the final result of the ripple
carry adder is valid only after the joint propagation delays of all full adder circuits inside it.
Ripple Carry Adder adds 2 n-bit number plus carry input and gives n-bit sum and a carry output.
The Main operation of Ripple Carry Adder is it ripple the each carry output to carry input of next
single bit addition. Each single bit addition is performed with full Adder operation (A, B, Cin)
input and (Sum, Cout) output. The 4-bit Ripple Carry Adder VHDL Code can be Easily
Constructed by Port Mapping 4 Full Adder. The following figures represent the 4-bit ripple
carry adder.

TRUTH TABLE OF RIPPLE CARRY ADDER:

A1 A2 A3 A4 B4 B3 B2 B1 S4 S3 S2 S1 CARRY

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 0 0 0 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 1 0 0 1 0 0 0 0

1 0 0 0 1 0 0 0 0 0 0 0 1

1 0 1 0 1 0 1 0 0 1 0 0 1

1 1 0 0 1 1 0 0 1 0 0 0 1

1 1 1 0 1 1 1 0 1 1 0 0 1

1 1 1 1 1 1 1 1 1 1 1 0 1

Table 3.2 ripple carry adder

It is possible to create a logical circuit using multiple full adders to add N-bit numbers.
Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is called
a ripple-carry adder (RCA), since each carry bit "ripples" to the next full adder. Note that the first
(and only the first) full adder may be replaced by a half adder (under the assumption that Cin =
0).
The layout of a ripple-carry adder is simple, which allows fast design time; however, the
ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be
calculated from the previous full adder. The gate delay can easily be calculated by inspection of
the full adder circuit. Each full adder requires three levels of logic. In a 32-bit ripple-carry adder,
there are 32 full adders, so the critical path (worst case) delay is 3 (from input to carry in first
adder) + 31 × 2 (for carry propagation in latter adders) = 65 gate delays. [3] The general equation
for the worst-case delay for a n-bit carry-ripple adder, accounting for both the sum and carry bits.
A ripple carry adder allows you to add two k-bit numbers.

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 1) We use the half adders and full adders and add them a column at a time

2) Before Adding

3) Adding column 0 – add x0 to y0, to produce z0 .

4) Adding column 2 – add x2 to y2 and c2 to produce z2, and c3.

5) We can use a full adder – for column 0 with Cin=0

CHAPTER 4

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 PROPOSED SYSTEM

4.1 GATE DIFFUSION INPUT TECHNIQUE (GDI):

Gate Diffusion Input (GDI) Technique the GDI technique offers realization of extensive
variety of logic functions using simple two transistor based circuit arrangement. This scheme is
appropriate for fast and low power circuit design, which reduces number of MOS transistors as
compared to CMOS and other existing low power techniques, while the logic level swing and
static power dissipation improves. It also allows easy top- down approach by means of small cell
library. The basic cell of GDI is shown below

The GDI cell consists of one NMOS and one PMOS. The structure looks like a CMOS
inverter. Though in case of GDI both the sources and corresponding substrate terminals of
transistors are not connected with supply and it can be randomly biased.

It has three input terminals: G (NMOS and PMOS shorted gate input), P (PMOS
source input), and N (NMOS source input). The output is taken from D (NMOS and PMOS
shorted drain terminal).

OUT
G

FIG.4.1 GDI BASED CELL USING PMOS AND NMOS

4.2 VARIOUS LOGIC FUNCTIONS:

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 P

O/
G P
N
N

TABLE.4.1 GDI CELL WITH VARIOUS LOGIC FUNCTIONS

GDI logic style approach consumes less silicon area compared to other logic styles as it
consists of less transistor count. In view of the fact that, the area is less, the value of node
capacitances will be less and for this reason GDI gates have faster operation which presents that
GDI logic style is a power efficient method of design. We can realize different Boolean functions
with GDI basic cell. Table shows how different Boolean functions can be realized by using
different input arrangements of the GDI cell.

The basic architecture of the XNOR gates using GDI method is shown in below fig .In
this configuration we have connected PMOS and NMOS gate. As we know that PMOS works on
ACTIVE LOW and NMOS works on ACTIVE HIGH. So, when the SELECT input is low (0)
then the PMOS get activated, and show the input ‘B’ in the output and due to low input (0) the
NMOS stands idle, as it is activated in high input.

4.3 Basic view of XNOR gate using GDI technique:

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 B (P)
FIG.4.3: BASIC VIEW OF XNOR GATE USING GDI TECHNIQUE
In this we have considered XNOR gate especially for the designing of full adder using
GDI technique XOR and XNOR functions are the key variables in adder equations. If the
generation of them is optimized, this could greatly enhance the performance of the full adder cell.
A new
In this (G)cell has used the GDI technique for generating
AB+A’B’
of XOR and XNOR functions. It uses
only eight transistors to generate the balanced XOR and XNOR functions.

ADVANTAGES OF GATE DIFFUSION INPUT:

1) Low power circuit design. B’ (N)

2) Reducing power dissipation.

3) Reducing transistor count.

4) Reducing area of digital circuits.

5) Maintaining low complexity of logic design

4.4 Importance of GDI technique:

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 Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit
design - is described. This technique allows reducing power consumption, propagation delay, and
area of digital circuits while maintaining low complexity of logic design. Performance
comparison with traditional CMOS and using GDI technique is presented. The different methods
are compared with respect to the layout area, number of devices, delay, and power dissipation.
Issues like technology compatibility, top-down design, and pre-computing synthesis, showing
advantages and drawbacks of GDI compared to other methods. Several logic circuits have been
implemented in various design styles.

4.4.1 PROPOSED FULL ADDER:

Fig4.4 shows the basic structure of a full adder. Equations describe the sum and carry
outputs in the form of input variables. The proposed structure basically contains three modules.
Modules 1-2 are XNOR logics which are responsible for the sum function and module 3 is a
carry module. Module 1and Module 2 are generating the sum signal, by connecting in cascaded
form and module 3 is a Mux, designed by using the pass transistors.

FIG 4.4:MODULE STRUCTURE

4.4.2 Design Approach of the Proposed Full Adder:

The proposed full adder circuit is represented by three blocks such as modules that
generate the sum signal (SUM) and module structure of the proposed full adder circuit is shown
in figure Fig. 1: Schematic structure of hybrid 1 Where, A, B, Cin - Three inputs SUM, Cout -
Output Each module is designed individually such that the entire adder circuit is optimized in
terms of power, delay, and area. The modified XNOR module is responsible for most of the
power consumption of the entire adder circuit. Therefore, this module is designed to minimize
the power to the best possible extend with avoiding the voltage degradation possibility.

4.5MODIFIED XNOR MODULE:

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 Fig 4.5 MODIFIED XNOR MODULE

In the three module based consumption is mainly dominate. Therefore, XNOR module is
design consumption is minimum. Fig.5.2 XNOR circuit, where the power conuse of weak
inverters. A weak invert the small channel width, comprised weak inverter is used to form a
conform a level restore the full swing of the output signal.
X. XN uses 4T but its output is having the proposed modified XNOR different manner as
compared to it consumes lesser power.

4.5.1 Proposed Carry Module

Carry signal is mainly response to the proposed full adder circuit. A carry l adder
implemented and simulated consumption is reduced and delay is improved by the adder. The
RCA FULL ADDER use of a full adder. Equation outputs in the form of input e basically
contains three logics which are responsible is a carry module. Module 1sum signal, by
connecting in Mux, designed by using the proposed circuit, power generated by XNOR module.
Designed such that, the power shows the modified consumption is reduced by the inverter is that

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which is having of Q1 and Q2 which is responsible for XNOR/XOR topologies and the proposed
circuit.

4.5.2 Modified XNOR Module Circuit :

The modified XNOR circuit where the power consumption is reduced significantly by
delibera weak inverter (channel width of transistors being small) formed by transistors Mp1 and
Mn1. The modified XNOR module circuit is shown in figure 4.5. 2016/ Advances in Natural and
Applied Sciences. April 201 Because of its high switching activity of intermediate nodes
(increased switching transistor count, static inverters and overloading of its inputs are the
bottleneck approach. The prime disadvantage of CPL, that is, the voltage degradation was
successfully addressed in TGA, which uses only 20 transistors for full adder implementation.
However, the other drawbacks of CPL like slow power consumption remain an area of concern
for the researchers focused on the hybrid logic approach which exploited the features of different
logic style Design Approach Of The Proposed Full Adder: The proposed full adder circuit is
represented by three blocks such as module 1 and module 2 are the XNOR modules that generate
the sum signal (SUM) and module 3 generates the carry signal structure of the proposed full
adder circuit is shown in figure4.5.

Schematic structure of hybrid 1-bit full adder. Each module is designed individually such
that the entire adder circuit is optimized in terms of power, delay, and area. The modified XNOR
module is responsible for most of the power consumption of the entire fore, this module is
designed to minimize the power to the best possible extend with avoiding the voltage degradation
possibility. Modified XNOR Module Circuit: The modified XNOR circuit where the power
consumption is reduced significantly by delibera weak inverter (channel width of transistors
being small) formed by transistors Mp1 and Mn1. The modified XNOR module circuit is shown
in fig, Because of its high switching activity of intermediate nodes (increased switching
bottlenecks of this approach. The prime disadvantage of CPL, that is, the voltage degradation was
successfully addressed in TGA., However, the other drawbacks of CPL like slow.

Later, researchers focused on the hybrid logic approach which exploited the features of
different logic styles in order to improve Module 1 and module 2 are the XNOR 3 generates the
carry signal (Cout). The schematic each module is designed individually such that the entire
adder circuit is optimized in terms of power, delay, and area. The modified XNOR module is
responsible for most of the power consumption of the entire fore, this module is designed to
minimize the power to the best possible extend with The modified XNOR circuit where the
power consumption is reduced significantly by deliberate use of weak inverter (channel width of
transistors being small) formed by transistors Mp1 and Mn1.Fig. Modified XNOR module circuit
Where, Mp - PMOS transistor, PMOS Mn - NMOS transistor, NMOS Full swing of the levels of
output signals is guaranteed by level restoring transistors Mp3 and Mn3. The XNOR module
employed six transistors (6T) six transistors (6T) are used to minimize the power consumption of
the overall full adder circuit.

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4.6 CARRY GENERATION MODULE:

Fig 4.6 CARRY GENERATION MODULE

4.6.1 Carry Generation Module Circuit:

The output carry signal is implemented by the (Cin) propagates only through a single
transmission gate (Q14 and Q13), reducing the overall carry propagation path significantly. The
carry generation module circuit is shown in fig. In Carry generation module circuit the deliberate
use of strong transmission gates (channel width of transistors Q13, Q14, Q15, and Q16 is made
large) guaranteed further reduction in propagation delay of the carry signal. Modified XNOR
module and carry generation module circuit is designed individually by using p and n-channel
metal oxide semiconductor (NMOS) transistors. 3. Detail Circuit Diagram of Proposed Full
Adder The hybrid 1-bit full adder circuit has 16 transistors such as eight PMOS transistors and
eight NMOS transistors. The sum output of the full adder is implemented by XNOR modules.
Modified XNOR module circuit - P-channel metal oxide semiconductor NMOS transistor,
NMOS - N-channel metal oxide semiconductor Full swing of the levels of output signals is
guaranteed by level restoring transistors Q13 and Q14. The XNOR module employed six
transistors (16T) (three PMOS transistors and three NMOS transistors). Because the sixteen
transistors (16T) are used to minimize the power consumption of the overall full adder circuit.
The output carry signal is implemented by the transistors Q14, Q16, Q13, and Q15.

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 Carry generation module circuit is the deliberate use of strong transmission gates (channel
width of transistors Q13, Q14, Q15, and Q16 is made large) guaranteed further reduction in
propagation delay of the carry signal. Modified XNOR module and generation module circuit is
designed individually by using p-channel metal oxide semiconductor (PMOS) channel metal
oxide semiconductor (NMOS) transistors. Detail Circuit Diagram of Proposed Full Adder: bit full
adder circuit has 16 transistors such as eight PMOS transistors and eight NMOS transistors. The
sum output of the full adder is implemented by XNOR modules. The (three PMOS transistors
and three NMOS transistors.

4.6.2 TRUTH TABLE OF 1-BIT FULL ADDER:

A B Cin SUM Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

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 Table 4.2 TRUTH TABLE OF 1-BIT FULL ADDER

TRANSISTOR SIZES OF PROPOSED 1-BIT FULL ADDER:

Tr. Name Width(nm) Length(nm)

Q1,Q3 800 130

Q2,Q4 400 130

Q5,Q7 800 130

Q8,Q9 400 130

Q6,Q10 400 130

Q11,Q12 400 130

Q13,Q16 400 130

Q14,Q15 400 130

TABLE 4.3 TRANSISTOR SIZES OF PROPOSED 1-BIT FULL ADDER

As shown in fig.4.6(c) which is composed of (Q13, Q14, Q15, Q16) pass transistors. In
CMOS Design, pass transistors are known for the low power circuits [1]. The carry signal (Cin)
passes only through a single transistor in every combination of input vector which reduces the
carry propagation path. Reduction in the carry propagation path reduces the delay of carry signal.

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 Fig 4.6 shows a detailed circuit of the proposed full adder. Sum output is implemented by
two cascaded XNOR modules. Signal B is applied to the weak inverter comprised of Q3, Q4.
Input and output signals (B and B’ respectively), of this weak inverter are used to construct the
controlled inverter with Q3 and Q4 transistors. The output of the controlled inverter is XNOR of
A and B but it is degraded one. To overcome this swing degradation problem pass transistors Q5
and Q6 are used. A p-MOS pass transistor (Q5) is used to get strong 1 at its output and n-MOS
pass transistor (Q6) for strong . So the output of the XNOR module is having full swing levels.
The output of the first XNOR module is applied as input to the Second XNOR module for
complete SUM function. Table I is the truth table for SUM and Cout functions in form of input
variables. According to the truth Table-I the carry signal can be analysed as following. If A=B,
then Cout=B, else Cout=Cin
The proposed single bit full adder may malfunction under low voltage when deployed to
real time environment. This Malfunctioning may occur because of the loading capacitance of
cascaded adder cells or because of improper input to the driven cells. So to test the real time
applications of the circuit a practical test bench set-up is shown in the fig. To avoid the signal
degradation in practical application conditions, three buffers are incorporated at the input stage
and two at output stage. Output buffers ensure the proper loading effect while input buffers
incorporate the input capacitances. The number of stages for test bench is set to three (detailed
discussion in delay calculation) because after third stage the delay of carry signal increased
gradually. All Possible input combinations were applied to the test bench at room temperature
and worst case power and delay parameters are calculated.

4.7 Design of full adder using XNOR gates

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 FIG.4.7 DESIGN OF FULL ADDER USING XNOR GATES
XOR and XNOR functions are the key variables in adder equations. If the generation of
them is optimized, this could greatly enhance the performance of the full adder cell. In this new
cell has used the GDI technique for generating of XOR and XNOR functions. It uses only eight
transistors to generate the balanced XOR and XNOR functions.

Performance analysis:

Power: The performance of the proposed full adder in terms of propagation delay, speed,
transistors count, total nodes, total devices and temperature level. Power consumption of the
hybrid full adder can be broadly classified into two categories
• Static power and • Dynamic and short-circuit power.
Static power, originated from biasing and leakage currents, in most of the CMOS-based
implementations is fairly low when compared with its dynamic counterpart. The transistor size
could be an effective parameter for reducing dynamic power consumption.

Delay: In the present design, the carry signal is generated by controlled transmission of the
input carry signal and either of the input signals A or B (when A = B). As the carry signal
propagates only through the single transmission gate, the carry propagation path is minimized
leading to a substantial reduction in propagation delay. The delay incurred in the propagation is
further reduced by efficient transistor sizing and deliberate incorporation of strong transmission
gates. However, during cascaded operation of the proposed full adder, operating in the carry
propagation mode, the speed performance of the adder deteriorates with increase in the number
of adder stages.

Speed: Full adder is the fundamental computational unit in most of the systems, its delay
predominantly governs the overall speed performance of the entire system. Also, the speed of
response of an adder is mainly dependent on the propagation delay of the carry signal which is
usually minimized by reducing path length of the carry signal.

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Transistors Count: The transistors count of the proposed full adder is given by using 16
transistors for 8- PMOS transistors and 8- NMOS transistors. It is used to minimize the chip size
and minimize the noise of the overall full adder circuit.

Total Devices: The total devices are used to reduce the power dissipation of the overall full
adder circuit. It is consists of two types

• Active devices •Passive devices

An active devices or components which are required external source to their operation are called
active devices. It is used to produce energy in the form of voltage or current. Active devices are
transistors and vacuum tubes.

4.8 PASS TRANSISTORS:

In electronics, pass transistor logic (PTL) describes several logic families used in the
design of integrated circuits. It reduces the count of transistors used to make different logic gates,
by eliminating redundant transistors. Transistors are used as switches to pass logic levels between
nodes of a circuit, instead of as switches connected directly to supply voltages. [1] This reduces the
number of active devices, but has the disadvantage that the difference of the voltage between
high and low logic levels decreases at each stage. Each transistor in series is less saturated at its
output than at its input. [2] If several devices are chained in series in a logic path, a conventionally
constructed gate may be required to restore the signal voltage to the full value. By contrast,
conventional switches transistors so the output connects to one of the power supply rails, so logic
voltage levels in a sequential chain do not decrease. Simulation of circuits may be required to
ensure adequate performance.

4.8.1Basic principles of pass transistor circuits:

The pass transistor is driven by a periodic clock signal and acts as an access switch to
either charge up or charge down the parasitic capacitance Cx, depending on the input signal Vin.
Thus, two possible operations when the clock signal is active (CK=1) are the logic "1" transfer
(charging up the capacitance Cx to a logic-high level) and the logic "0" transfer (charging down
the capacitance Cx to a logic-low level). In either case, the output of the depletion load nMOS
inverter obviously assumes a Logic-low or a logic-high level, depending upon the voltage Vx.

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 Fig 4.8 logic low or a logic high level circuit

4.9 Complementary pass transistor logic:

Some authors use the term "complementary pass transistor logic" to indicate a style of
implementing logic gates that uses transmission gates composed of both NMOS and PMOS pass
transistors. Other authors use the term "complementary pass transistor logic" (CPL) to indicate a
style of implementing logic gates where each gate consists of a NMOS-only pass transistor
network, followed by a CMOS output inverter. Other authors use the term "complementary pass
transistor logic" (CPL) to indicate a style of implementing logic gates using dual-rail encoding.
Every CPL gate has two output wires, both the positive signal and the complementary signal,
eliminating the need for inverters.

Complementary pass transistor logic or "Differential pass transistor logic" refers to a

logic family which is designed for certain advantage. It is common to use this logic family for
multiplexers and latches. CPL uses series transistors to select between possible inverted output
values of the logic, the output of which drives an inverter The CMOS transmission gates consist
of nMOS and pMOS transistor connected in parallel.

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4.10 Ripple Carry Adder Delay:
1) Combinational logic circuits can't compute the outputs instantaneously.
2) Some delay between the time the inputs are sent to the circuit, and the time the
output is computed.
3) Assume the delay is T units of time for one adder, what is the delay for a n-bit
ripple carry adder? – the adders are working in parallel – the carry must "ripple"
their way from the least significant bit and work their way to the most significant
bit.
4) The delay is not a big problem, usually, because hardware adders are fixed in
size.

ECE DEPARTMENT, ACOE Page 38

 CHAPTER-5
RESULT ANALYSIS
Results:
5.1 Conventional 28-T Full Adder:

Fig 5.1 Schematic conventional 28-T FullAdder

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 Fig.5.2 symbol

Fig 5.3 Test Circuit

ECE DEPARTMENT, ACOE Page 40

 Fig 5.4 Output Waveform

5.2 Modified Full Adder Design Using GDI Technique:

Fig 5.5 Schematic of a full adder using GDI

Fig 5.6 Symbol

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 Fig 5.7 Test Circuit

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 Fig 5.8 Output waveforms of Full Adder Using GDI Technique

5.3 Comparison of power between conventional 28-T and 16-T

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 Fig: 5.9 Comparison of Power Between Conventional28-T And Gdi 16-T Transister

5.4 Conventional Ripple Carry Adder:

Fig 5.10 Schematic Conventional 28-T ripple carry adder

ECE DEPARTMENT, ACOE Page 44

 Fig 5.11 symbol

Fig 5.12 Test Circuit

ECE DEPARTMENT, ACOE Page 45

 Fig 5.13 Output Waveforms

Fig 5.14 Output Waveforms

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 Fig 5.15 Output Waveforms

5.5 64-T GDI Ripple Carry Adder:

Fig 5.16 Schematic 64-T Ripple Carry Adder

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 Fig 5.17 symbol

Fig 5.18Test Circuit

ECE DEPARTMENT, ACOE Page 48

 Fig 5.19 Output Waveforms

5.6 Comparison of RCA and GDI RCA

Fig 5.20 Output Waveforms

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 Fig 5.21 Output Waveforms

5.7 COMPARISON TABLES:

5.7.1 Comparison of full adders:

No. of Power Average Minimum Maximum

Transistors consumption Power Power Power

EXISTING 28T 13.8877w 2.9275w 2.9155w 2.9362w

PROPOSED 16T 562.5389mw 433.61nw 103.7mw 1.1450w

Table 5.1 comparison of full adder

5.7.2 Comparison of ripple carry adders:

Existing Proposed

No. of transistors 112 64

Power consumption 2.2502uw 595.25nw

Average power 115.51uw 48.5uw

Table 5.2 comparison of Ripple Carry Adder

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5.7.3 COMPARISON OF DELAY:
SUM CARRY

FULL ADDER 159.98ns 98.25ns

GDI FULL ADDER 130.99ns 90.34ns

TABLE 5.3 COMPARISON OF DELAY

5.7.4: Power Analysis of Full Adder:

No. of Power Average Minimum Maximum

Transistors Consumption Power Power Power

EXISTING 28T 13.8877w 2.9275w 2.9155w 2.9362w

PROPOSED 16T 562.5389mw 433.61nw 103.7mw 1.1450w

TABLE 5.4 POWER ANALYSIS OF FULL ADDER

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5.7.5 POWER ANALYSIS OF RCA:

Existing Proposed

No. of transistors 112 64

Power consumption 2.2502uw 595.25nw

Average power 115.51 48.5uw

TABLE 5.5: Power analysis of RCA

5.8 power analysis graph:

ECE DEPARTMENT, ACOE Page 52

 Fig.22 power analysis graph

CHAPTER-6
CONCLUSION
According to the above results it can be concluded that our proposed 16-T full adder has
got better performance in power and area consideration in comparison with conventional 28-T
full adder .It shows that in contrast to other conventional techniques, this approach is better and it
will be more appropriate for industrial practice in complex process technologies.

In this we have used GATE DIFFUSION INPUT (GDI) TECHNIQUE in order to

perform various logic functions to decrease the purpose of transistors, area and complexity of the
circuit for better and fast results and carry function is implemented by Pass transistor logic. Pass
transistors helps us to reduce voltage degradation problems.

ECE DEPARTMENT, ACOE Page 53

 REFERENCES

[1] Rabaey J.M., A. Chandrakasan, B.Nikolic, “Digital Integrated Circuits, A Design” 2nd 2002,
prentice Hall, Englewood Cliffs,NJ.

[2] A. M. Shams, T. K. Darwish and M. A. Bayoumi. “Permormancess Analysis of LowPower 1-

Bit CMOS full adder cells”, IEEE Transaction on VLSI Systems, Vol. 10, Feb. 2002.

[3] K.Navi, M.R.Saatchi, O.Daei, “A high speed hybrid full Adder”, European journal of
scientific research.vol.26, No.1, 2009.

[4] M.Moaiyeri, R. Faghih Mirzaee, K.Navi, “Two New Low Power and High Performance Full
Adders”, Journal of Computers, Vol. 4, No. 2, February 2009.

[5] C. H. Chang, J. Gu and M. Zhang, “A review of 0.18um full adder performance for tree
structured arithmetic circuits”, IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 13, No. 6, pp.686-695, June 2005.

ECE DEPARTMENT, ACOE Page 54

[6] K. Navi, O. Kavehei, M. Ruholamini, A. Sahafi, Sh. Mehrabi and N. Dadkhahi , “Low power
and High Performance 1-Bit CMOS Full Adder Cell”, Journal of Computers, Vol. 3, No. 2,
February 2008.

[7] Young. Woon Kim, Hae. Jun Seo, Tae.Won Cho, “A Design of High Speed 1-Bit Full Adder
Cell using 0.18 µm Cmos Process”, Proceeding of The 23rd International Technical Conference
on Circuits/Systems, Computers and communications, ITC-CSCC 2008.

[8] A.R, Saberkari, SH. Shokouhi, “A Novel Low-Power-Voltage Cmos 1-Bit Full Adder Cell
with the GDI Technique”, Proceeding of the 2006 IJME-INTERTECH conference.

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