Lab Assignment 3: Title: Seven-Segment Display Logic Learning Objective
Lab Assignment 3: Title: Seven-Segment Display Logic Learning Objective
Learning Objective:
Specification:
Design a combination circuit that takes a decimal/hexadecimal digit encoded using 4 bits
and produces 7-bit output for seven segment displays of BASYS3 FPGA board. Do
extensive simulation of the design using Xilinx simulator, and then implement the circuit
on BASYS-3 FPGA board.
Details:
The figure below shows a 7-segment display circuit of BASYS3 boards. There are four
displays as shown. Each of these four consists of 7 LEDs (Light Emitting Diodes)
forming 7 segments. These diodes have a common anode and individual cathodes. To
display a digit, it is required to give a ‘1’ as input to the anode and a ‘0’ or ‘1’ to each
segment depending upon whether that segment needs to be lighted (‘0’) or not (‘1’).
This assignment focuses on a single digit display. In a later assignment we will deal with
all four displays and produce anode signals to control which digit(s) need to be displayed.