designfeature By Jim Flynn, Synopsys Professional Services

POWER ISSUES CAN PLAGUE ANY SOC, SO EVERY

DESIGN FLOW NEEDS METHODS FOR PREDICTING
POWER CONSUMPTION, BEGINNING AT RTL.

Accurate power-analysis
techniques support smart
SOC-design choices
s power consumption becomes increasingly age from 1.8 to 1.25V. The parallel-processing logic

A critical for both portable and nonportable ap-

plications, accurate techniques for predicting an
SOC’s (system on chip’s) power have become essen-
is much larger than the serial-processing equivalent,
but the resulting logic’s reduced voltage and oper-
ating frequency combine to cut power consumption
tial. Designers need to know, for example, whether by 75%. This parallel approach succeeds, because
a mobile-phone SOC requires both voltage and fre- power has a squaring function to voltage and only a
quency scaling or whether a network-router SOC linear function for frequency and switching. Often,
consumes as much power as a desk lamp. A design- the area penalty is small, but the power saving is sig-
er can make these determinations only by estimat- nificant, so it is worth exploring the trade-offs.
ing a design’s power consumption and intelligently Power-related trade-offs at any level of design ab-
applying power-saving methods. Conducting pow- straction depend on a designer’s ability to analyze
er analysis throughout the flow enables designers to power consumption, and the earlier the better. One
address power issues early on and avoid the lengthy analysis method uses a spreadsheet to estimate pow-
iterations caused by redesigns required to meet pow- er at the RTL (register-transfer level). Other meth-
er budgets.
Four analysis methods apply to various points 600
throughout the design flow: before synthesis, with 518
rough synthesis results, after full synthesis, and af- 500
ter layout; a fifth method provides a vectorless tech- 430
nique for calculating switching activity that design- 400
ers can use at any point from synthesis on. Table 1
details the power-analysis and associated power-op- POWER
(mW) 300
timization methodologies in the context of the de- 260
237
sign flow.
Most SOC-power-analysis methods depend on 200

gate-level representations, but, by that point in the

design flow, the power-saving opportunities with the 100
greatest impact have passed. At the system and al-
gorithm levels, for example, using a parallel ap- 0
proach rather than a serial implementation reduces 1 2 3 4
CASE
clock frequencies, which can significantly decrease
power consumption. In the course of a design flow, power esti-
Figure 1
In one design that serially processes data sam- mates change for a sample block at four
ples, for example, designers estimate with early de- points in the flow. Case 1 uses worst-case switching activity
sign models that the chip’s power consumption and worst-case wire-load estimates; Case 2 uses more accu-
would be far too high. They change the architecture rate wire-load estimates and worst-case activity; Case 3 uses
so that the chip processes the samples in parallel to accurate wire-load estimates and realistic activity; and Case
reduce the logic’s clock speed from 80 to 10 MHz. 4 uses exact wire loads (extracted) and realistic activity
Additionally, the designers reduce the supply volt- based on Spice-accurate simulation.

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designfeature Power analysis

ods rely on tool reports and provide in- TABLE 1—POWER ANALYSIS AND ASSOCIATED POWER-OPTIMIZATION METHODS
creasingly accurate results at each stage
Power optimization Power analysis
as additional design and library infor-
System design Architecture optimization (for example, Power estimates based on:
mation becomes available. The vector- parallel versus serial), supply- estimated gate counts, estimated activity
less-analysis method offers a way to get voltage scaling, clock-frequency scaling
“full power coverage” analogous to the RTL design Module-clock gating RTL power analysis based on:
way static-timing analysis provides full defined clocks and registers, estimated
timing coverage. gate counts, realistic activity
Table 2 summarizes the analysis meth- Floorplanning Voltage islands
ods. (For background on static and dy- Synthesis Threshold-voltage scaling, power- Gate-level power analysis based on:
namic power consumption, see sidebar optimization in synthesis, RTL- actual gate counts, realistic activity,
“Where an SOC consumes power.”) Al- clock gating wire-load models, final libraries
though this article focuses on analyzing Place and route Gate-level power analysis based on:
dynamic power, note that leakage power actual gate counts, realistic activity,
is becoming increasingly important at accurate routing, final libraries
process geometries of 130 nm and below.
crowatts/megahertz⫻activity⫻frequency. A net having an activity of five logic-one-
RTL-POWER ANALYSIS Summing these power values for all to-logic-zero transitions and five logic-
In the earliest stages of a design flow, the types of cells in a block gives the zero-to-logic-one transitions during a
a spreadsheet power analysis can provide block’s overall internal active-power es- 10-nsec interval also has a toggle rate of
rough but valuable estimates of a design’s timate. Before performing synthesis, de- one. As these examples illustrate, a toggle
power consumption. If designers have signers need to estimate gate counts rate of one indicates one activity transi-
not yet selected the library, this analysis based on architectural choices and an un- tion per nanosecond.You can relate pow-
can reveal the best power-conscious li- derstanding of the design. For example, er and toggle rate by understanding that
braries and design architectures. After li- they can derive approximate gate counts each transition requires some amount of
brary selection, using Synopsys Design from features such as bus sizes, word energy to change the state of an internal
Compiler and Synopsys Power Compiler lengths, control layers, and memory circuit during the time interval of the
tools can supply values for use in the depth. After selecting the library and per- state change.
spreadsheets. The power-analysis spread- forming early synthesis, a designer can It is key to note that power estimates at
sheet includes approximate gate counts, estimate the gate counts for a block by us- any level of abstraction are meaningful
rough activity-per-block values, side-by- ing a report from the synthesis tool to only when the switching activity repre-
side vendor microwatts-per-megahertz show the number of each instance type sents the chip’s actual working operation.
data, and relative power estimates. The for the design. Assigning the activity lev- A common mistake is to use a vector set
analysis at this point can show that a de- els is a key aspect of the power calcula- that simulates system-boot sequences.
sign consumes far too much power to be tion. The gates of a design have different This activity rarely represents actual
practical—thus avoiding weeks of work activity levels that you can estimate with working conditions and therefore leads
to create a chip that is useful only as a cof- or without a simulation to extract to inaccurate power estimates. An RTL
fee-cup warmer. switching activity. After selecting the li- simulator can automatically generate an
The spreadsheet-analysis method re- brary, however, it is a good idea to run a SAIF (Switching Activity Interchange
quires an estimate of each block’s gate functional simulation to determine the Format) file, but the activity values are
count (number of library cells of each switching activity. accurate only if the vector set is realistic.
type) and activity level. It also requires in- Designers measure the switching ac- No tool can automatically generate such
formation on the amount of energy con- tivity in terms of a toggle rate. The tog- vectors, because the task requires an un-
sumed by the switching of each cell type. gle rate equals the number of logic-zero- derstanding of the circuit’s intent. (How-
Data from a library vendor’s manual can to-logic-one and logic-one-to-logic-zero ever, the vectorless-analysis technique
facilitate the assignment of an appropri- transitions of a design object (for exam- presented later in this article offers an-
ate power value relative to speed (in mi- ple, a net, pin, or port) per unit of time. other way to obtain activity values.)
crowatts per megahertz). Designers cal- A net having an activity of 50 logic-one- Some power-analysis tools can use an
culate a block’s internal power to-logic-zero transitions and 50 logic- SAIF file to define libraries and con-
consumption for a particular type of cell zero-to-logic-one transitions during a straints and to annotate the design for
as: Power consumption⫽gate count⫻mi- 100-nsec interval has a toggle rate of one. power estimation. The Synopsys Power
Compiler tool’s default switching activi-
TABLE 2—SUMMARY OF POWER-ANALYSIS METHODS ty for nonannotated ports is 0.25 toggle
When to perform estimation How gates are calculated How load is calculated per positive edge. This tool applies and
Design/library exploration Rough estimation Unknown/in definition propagates this value throughout the
Presynthesis/early synthesis Rough estimation DC-wire-load models block. Table 3 lists examples of results es-
Postsynthesis Accurate (placed) Wire-load models/SPEF timated using the spreadsheet method.
Postlayout Exact Extracted SPEF
After using this method to calculate in-

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designfeature Power analysis

ternal power, a designer can estimate

switching power as 30% of internal pow- TABLE 3—RESULTS USING THE
er. Without accurate load and switching SPREADSHEET METHOD
Gate type Activity ␮W/MHz
data, engineers need to treat this value as
A=125 0.25 5
a rough estimate. Such estimates are B=150 0.05 12
more useful in comparing the power im- C=50 0.1 16
plications of various design strategies Note: Block 1: Frequency=100 MHz.
than in predicting a chip’s actual power
consumption. However, rough estimates erwise. After selecting the library, you can
at the RTL stage do provide an early calculate static probability during simu-
warning that a design may turn out to be lation by comparing the time a signal is
unacceptably hot. at a certain logic state with the total sim-
ulation time.
ESTIMATING LEAKAGE POWER
Switching power is usually the most GATE-LEVEL POWER ANALYSIS
important value to determine in early After performing synthesis, designers
analysis, but you can also estimate leak- can obtain fairly accurate power esti-
age power based on each cell type’s leak- mates based on actual gate counts and
age data. Because leakage differs for high simulated activity. The most significant
and low states, you must base the leakage sources of inaccuracy at this point are the
analysis on the static probability that a activity and the prelayout wire-load val-
signal is at a certain logic state. ues. A designer can improve accuracy by
Static probability has a value between generating an SAIF file from gate-level
zero and one that depends on a signal’s simulations. The activity values are ac-
function. For example, an active-low re- curate only when the simulation vectors
set signal typically has a logic-one static represent actual application behavior. As
probability (SP1) at or near 1.0 (100%). for the load values, a tool such as Synop-
For a data-bus signal, you can assume a sys Physical Compiler software can im-
value of 0.5 (50%) for SP1 unless some prove their accuracy after physical opti-
architectural characteristic suggests oth- mization. You can produce an SPEF

WHERE AN SOC CONSUMES POWER

The total power that a chip consumes equals and drain through the transistor channel.
dynamic power plus static power. Dynamic The subthreshold leakage current is problem-
power is the power consumed in switching atic because it increases as transistor thresh-
logic states, both internal to the cells (inter- old voltages (VTH) decrease. In fact, the move
nal power) and for driving the chip’s nets to 130 nm and beyond may boost leakage
and external loads (switching power): Dy- power to as much as 50% of total chip pow-
namic power⫽CV2F, where C is the load, V er. Increased leakage power can exponential-
is the voltage swing, and F is the number of ly increase reliability-related failures in chips
logic-state transitions. (even in standby). As CMOS technologies
As semiconductor structures become scale down, the main approach for reducing
smaller, device and interconnect capaci- power has been to scale down the supply
tances decrease, allowing for higher per- voltage, VDD. Voltage scaling is a good tech-
formance and lower power. Countering nique for controlling a chip’s dynamic power
these factors are power increases due to because of the quadratic effect of voltage on
larger designs and higher switching rates. A power consumption. However, just reducing
device consumes static power (leakage pow- the power supply degrades circuit speed, be-
er) while transistors are not switching: Static cause the switching delay time is proportional
power⫽VISTAT. to the load capacitance and the ratio VTH/VDD.
Although transistors have some reverse- To maintain sufficient drive strength for
biased diode leakage from drain to sub- fast switching, VTH must decrease in propor-
strate, most leakage power is due to the tion to VDD. This relationship leads to the
subthreshold current through a transistor in leakage-power increase. Fortunately, a pow-
the off state. This subthreshold current re- er-aware design flow can balance timing re-
sults from the conduction between source quirements with various power goals.

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 designfeature Power analysis

(Standard Parasitic Delay Format) file switching activity but may be difficult to
annotating Steiner route and RC para- obtain. The design may be too large to
sitic estimates. After layout, a gate-level simulate at the gate level, or an incom-
simulation can generate a VCD (value- plete netlist may cause inaccurate timing
change-dump) file. VCD files log that makes gate-level simulations im-
changes to signal values during a simu- possible. There may also be lack of a test-
lation and provide the design’s nodal ac- bench, test cases, or both that force max-
tivity, structural-data hierarchical con- imum power usage. Simulation test cases
nectivity, path delays, and timing and often fail to generate the values for
event information. switching activity that are necessary for
Chip I/Os can significantly reduce ac- power analysis. It is difficult to verify that
curacy if they are numerous, switching at you covered the cases that cause the high-
high speed, and driving long wires. est power consumption, and this uncer-
Lumped load models for the I/Os may tainty parallels the problems of using
produce too pessimistic results, which simulations to verify timing, where there
can be a problem if design goals call for is no certainty that all the timing paths
accurate rather than worst-case power are covered. Due to this uncertainty, stat-
ic-timing analysis has largely replaced
THE ACCURACY OF THE INFOR- simulation for timing verification.
Designers can achieve a similar degree
MATION AVAILABLE IN PHASES of coverage for power analysis using a
vectorless technique. In this technique,
OF THE DESIGN AND IMPLE- the designer annotates the worst-case
switching values on all of a design’s ar-
MENTATION CYCLE AFFECTS chitecturally stable parts (ports and reg-
isters). For best accuracy, engineers need
THE POWER ESTIMATES. to propagate the switching values for the
ports and registers throughout the design
estimates. For a more accurate picture, based on statistical/heuristic calcula-
you can run Synopsys HSpice tool sim- tions. Power-analysis tools can automat-
ulations on critical I/O-cell types with ically perform this task through all of the
accurate distributed-impedance models. design’s logic cones and write a net
You calculate the I/O cell power using switching report. Designers can then use
numeric methods that determine charge a Perl script to process the report data
and energy per rising/falling edge. Giv- into a sequence of net-switching-activi-
en the Synopsys HSpice tool output of ty annotation commands. These com-
current and time, you can also calculate mands drive a tool to annotate all nets
the internal energy per transient using with appropriate switching data, which
the trapezoidal integration method (in designers can then use with any of the
Matlab, for example).You can use the I/O aforementioned power-analysis meth-
activity recorded during analysis to scale ods. A statistical propagation technique
I/O power. Finally, you combine the to- allows designers to specify pessimistic
tal I/O power with the core power for an values for port and register switching if
overall power estimate. a complete annotation of all the nets is
To show how power estimates vary us- impractical. This approach delivers the
ing the methods described so far, Figure realistic power-consumption values nec-
1 shows examples based on one block (a essary for today’s SOC designs.왏
high-speed FIR filter) in a DSP design.
This example demonstrates how much Author’s Bio graphy
the accuracy of the information available James P Flynn is a senior IC designer with
in phases of the design and implemen- Synopsys Professional Services (www.
tation cycle affects the power estimates. synopsys.com/sps). He has a master’s de-
gree in analog-IC design. He has a master’s
VECTORLESS POWER ANALYSIS degree in analog-IC design from Florida
The power-analysis methods present- Institute of Technology.
ed here so far derive switching activity
from simulation data, but this approach
has a variety of limitations. Gate-level de- Talk to us
scriptions of the circuit allow the most Post comments via TalkBack at the online
accurate simulations for obtaining version of this article at www.edn.com.
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