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What is Phase Locked Loop (PLL)
PLL is an Electronic Module (Circuit) that locks
the phase of the output to the input.
Locked Vs. Unlocked Phase
Phase-Locked Loop (PLL) generates an output signal whose
phase is related to the phase of the input "reference" signal.

The circuit consists of

- Phase detector
- Low Pass filter
- Voltage controlled Oscillator

This circuit compares the phase of the input signal with the
phase of the signal derived from its output oscillator and
adjusts the frequency of its oscillator to keep the phases
matched.

As frequency is the derivative of phase.

Basic PLL System
Implementation of PD
What is VCO ?
 How are PLL’s Used

• To generate stable high frequency oscillations

• Frequency Synthesis (e.g. generating a 1 GHz clock

from a 100 MHz reference)

• Skew Cancellation (e.g. phase-aligning an internal

clock to the IO clock)

• Extracting a clock from a random data stream

Reference clock enters the chip and drives a phase locked loop (PLL), which then drives
the system's clock distribution.

The clock distribution is usually balanced so that the clock arrives at every endpoint
simultaneously. One of those endpoints is the PLL's feedback input.

The function of the PLL is to compare the distributed clock to the incoming reference
clock, and vary the phase and frequency of its output until the reference and feedback
clocks are phase and frequency matched.
Simple PLL
Locked Condition
Any slight change in the input signal first appears as
a change in phase between the input signal and the
controlled oscillator frequency.

This phase shift then acts as an error signal to

change the frequency of the controlled oscillator to
match the input signal
Without any external signal applied to PLL ,the input Ve to the
VCO is zero and the VCO operates at its free running frequency
f0.

A periodic signal with frequency fS, applied to the input of the

PLL whose frequency is close to VCO frequency.

An error voltage is generated which forces VCO to synchronize

with the input frequency.

When this happens PLL is said to be locked on the input signal

frequency.

When PLL is locked to an input signal, Vco outputs a periodic

signal which is at same frequency as input except a finite phase
difference.
Start with two sinusoids, vin(t) and vo(t) both having same frequency

Let input signal be : v (t)  A sin[st]

in

Let the VCO output be: vo(t )  Bsin[ot o(t )]

Multiply these two signals.
Phase detector

v1(t)
Phase detector functions as a multiplier.

Provides two frequency components

fSUM = fS+f0 and f = f0-fS

The sum frequency signal will be removed by the low-
pass filter.

An error voltage Ve(t) is generated at the filter output

and this forces the VCO frequency to change in a
direction such that ∆f = 0.

Under this condition only a dc voltage remains at the

filter output.
If there is change in input carrier frequency and frequency of VCO:
Vs (t )  A sin  s t
Vo (t )  B sin(0t   )

 sin X sin Y  cos( X  Y )  cos( X  Y )

1
2
 Vs (t )Vo (t )  0.5 AB cos[( s  0 )t   ]  0.5 AB cos[( s  0 )t   ]
after low pass filter :
 Vs (t )Vo (t )  0.5 AB cos[( s  0 )t   ]
1
 Vs (t )Vo (t )  0.5 AB[1  [sin 2 ( s  0 )t   ]] 2

Let ( s  0 )t    0
1
 Vs (t )Vo (t )  Ve (t )  0.5 AB[1  [( s  0 )t   ] ] 2 2

if  s  0
 Vs (t )Vo (t )  Ve (t )  0.5 AB cos( )  0.5 AB cos 
 if   0
 Vs (t )Vo (t )  Ve (t )  0.5 AB[1  [( s  0 )t ]  ........]  Ve , 0  Ve (t )
if  s  0
Vs (t )Vo (t )  Ve (t )  0.5 AB    input for free running frequency
if  s  0 , then ( s  0 )t  ve
 Ve (t )  ve
 Ve (t ) ,  freqency 
if  s  0 , then ( s  0 )t  ve
 Ve (t )  ve
 Ve (t ) ,  freqency 
A dc value at VCO i.e Ve,0 input to give free running frequency ‘0’ i.e. when error
voltage is zero.
VCO
 Ve  L
(-ve gain K0 )
 If the input frequency varies slowly, the PLL can
maintain lock with an input signal.

The range of frequencies over which the PLL can

maintain lock with an input signal is called the lock-
range of the system.

The capture-range is defined as the range of frequencies

over which the PLL can acquire lock with the
incoming signal.

• Capture range is always smaller than the lock range.

• The total time taken by the PLL to establish lock is

pull in time .
If the applied reference signal is within a certain range of
frequencies centered about 0, the PLL will begin to
track the signal.

Once the PLL is locked onto the reference signal, it will

track the signal until the reference signal exceeds the limit
of the PLL’s lock range.

Typically the lock range of a PLL may range from  1% to

 60% of VCO free running frequency.
• Once the PLL is locked, it can track small frequency changes
of the input signal by generating an additional phase error ϕ0
between VCO and the input signal.
• The phase detector converts the phase error into a dc error
voltage Ve which keeps the VCO frequency in steps with the
input signal.
• While the PLL is tracking an input signal, the error voltage is
a direct measure of the frequency difference between fs and fo.
• The maximum error voltage is generated when the phase
difference f0 reaches its limiting value of –pi /2 rad.
• Thus the tracking range (lock-range) of the PLL is given by
, where K0 (Hz/V) is the voltage-to-frequency
conversion gain of the VCO.
 2fC = f3-f1, 2 fL = f2-f4

 Vs (t )Vo (t )  Ve (t )  0.5 AB[1  [(s  0 )t ]  ........]  Ve,0  Ve (t )

 Tracking Characteristics
• PLL does not respond until its frequency reaches f1 ,
corresponding to the lower edge of the capture range.
• Then the loop suddenly locks on to the input signal, causing a
negative jump in Ve .
• As the input frequency continues to increase, the loop tracks
the input signal and Ve continues to increase and goes through
zero at fs= fo.
• The loop tracks fs until the input frequency reaches f2
corresponding to the upper edge of the tracking range.
• As the PLL looses lock, Ve develops zero voltage and VCO
returns to f0 .
• If the input is slowly swept back towards low frequencies, the
cycle repeats itself as shown in Fig. 6.29(b), where the loop
recaptures the signal at fs = f3 and tracks it down to fs = f4 .
The total capture range is :

The total lock range is :

In summary, the PLL exhibits a frequency-selective

frequency-to-voltage conversion characteristics, centred
around the VCO free running frequency, f0.

The PLL can acquire lock or capture with only those

signals that fall within the total capture range 2∆fC ,
centred about f0 .

Once locked, it can track an input signal over a total

lock range of 2∆fL centred about fo .
Once the PLL is in lock, what is the input (or
VCO) frequency range for which it can keep
itself locked is the lock range. When the PLL is
initially not in lock, what frequency range can
make the PLL lock is the capture range
IC PLL,565
• The free running frequency f0 of the VCO is adjusted by
proper choice of R1 and C1 in the following relation

• R1 must have a value between 2 k and 20 k and C1 can be

any value.
• f 0 is normally chosen at the centre of the input frequency
range.
• C2 along with the internal resistance of 3.6 k forms the
low-pass filter. C2 should be chosen large enough to
stabilize the VCO frequency.
• Pins 2 and 3 are the input terminals.
• The input signal can be directly coupled.
• A short between pins 4 and 5 connects the VCO output
f0 to the phase comparator and enables the comparator to
compare f0 with the input signal frequency fs .
 Applications of PLL
• By inserting a frequency divider circuit into the
feedback loop of a PLL between the VCO output
and the phase detector input, the PLL can be
used as a frequency multiplier.
• When the PLL is locked to an external frequency, both the
inputs of the phase detector are at the same frequency

• The desired amount of multiplication can be obtained by

selecting a proper divide-by-N network
 Aplications of PLL

A frequency synthesizer is an electronic system for

generating any of a range of frequencies from a single fixed
oscillator.

 PLL used as a frequency synthesizer.

Frequency dividers use integer values of M and N.

For M=1 frequency synthesizer acts as a frequency multiplier.

f x fout N
 fout  f x
M N M
 Aplications of PLL
 PLL used as a frequency synthesizer.

Frequency dividers use integer values of M and N.

For M=1 frequency synthesizer acts as a frequency multiplier.

f x f out N
 f out  fx
M N M

PLL used in a frequency synthesizer.

If there is only change in phase:
Vo1  A sin(c t )
Vo 2  B sin(c t   )
A B A B
Vo1  Vo 2  Cos  ( Sin sin 2c t  CosCos 2c t )
2 2

After LPF error signal for VCO  Ve,0  Ve

For ,   0
A B A B
Vo1  Vo 2   Cos 2t
2 2
 Ve, 0
A dc value at VCO i.e Ve,0 input to give free running frequency ‘0’
i.e. when error voltage is zero.
VCO
 Ve  L
(-ve gain K0 )