1.

HDL Code to realize all the Logic gates

AIM: To Design and Implement all logic gates using verilog HDL.
TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

TRUTH TABLE:

Input Input Output Output Output Output Output Output Output Output
a b s=0 s=1 s=2 s=3 s=4 s=5 s=6 s=7
0 0 0 0 0 1 1 1 1 1
0 1 0 1 1 0 1 1 0 0
1 0 0 1 1 0 1 0 0 1
1 1 1 1 0 0 0 0 1 0
SOURCE CODE:
module allgates(a,b,y0,y1,y2,y3,y4,y5,y6,y7,);
input a,b;
output y0,y1,y2,y3,y4,y5,y6,y7;
BUF (y0,a);
NOT (y1,a);
AND (y2,a,b);
NAND (y3,a,b);
OR (y4,a,b);
NOR (y5,a,b);
XOR (y6,a,b);
XNOR(y7,a,b);
endmodule

TEST BENCH:
allgates uut (
.a(a),
.b(b),
.y0(y0),
.y1(y1),
.y2(y2),
.y3(y3),
.y4(y4),
.y5(y5),
.y6(y6),
.y7(y7),
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
// Wait 100 ns for global reset to finish
#100;
end
endmodule
SCHEMATIC DIAGRAM
SIMULATION WAVEFORMS:

SYNTHESIS REPORT:
RTL Top Level Output File Name : allgates.ngr
Top Level Output File Name : allgates
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : Yes
Target Technology : Automotive 9500XL
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs : 6
Cell Usage :
# BELS : 56
# AND2 : 18
# INV : 19
# OR2 : 16
# OR3 : 2
# XOR2 : 1
# IO Buffers : 6
# IBUF : 5
# OBUF : 1

CONCLUSION: Hence the all gates design is implemented using verilog HDL.
 2(i).DESIGN OF HALF ADDER

AIM: To Design and Implement full adder using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:
TRUTH TABLE:
Input a Input b Output sum Output carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

SOURCE CODE:
module hadf(a,b,s,c);

output s,c;

input a,b;

s wire s,c,a,b;

assign s=a^b;

assign c=a&b;

endmodule

TEST BENCH:
module HA_v;

// Inputs

reg a;

reg b;

// Outputs

wire s;

wire c;

// Instantiate the Unit Under Test (UUT)

 hadf uut (

.a(a),

.b(b),

.s(s),

.c(c)

);

initial begin

// Initialize Inputs

a = 0;

b = 0;

// Wait 100 ns for global reset to finish

#100;

a = 0;

b = 1;

#100;

a = 1;

b = 0;

#100;

a = 1;

b = 1;

#100

end

endmodule
SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:
SYNTHESIS REPORT:
=====================================================================
* Synthesis Options Summary *
=====================================================================
---- Source Parameters
Input File Name : "hadf.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "hadf"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : hadf
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : hadf.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
CONCLUSION: Hence the half adder has been designed and implemented using
Verilog HDL.
 2(ii).DESIGN OF FULL ADDER

AIM: To Design and Implement full adder using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

TRUTH TABLE:

Input a Input b Input c Output sum Output carry

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

SOURCE CODE:
module fulladderdirect(a,b,c,sum,carry);
output sum,carry;
input a,b,c;
wire sum,carry,a,b,c;
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule

TEST BENCH:
module fulladderdirect_tb;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire sum;
wire carry;
// Instantiate the Unit Under Test (UUT)
fulladderdirect uut (
.a(a),
.b(b),
.c(c),
.sum(sum),
.carry(carry)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;
// Wait 100 ns for global reset to finish
#100;
a = 0;
b = 1;
c = 0;
#100;
a = 0;
b = 1;
c = 1;
#100;
a = 1;
b = 0;
c = 0;
#100;
a = 1;
b = 0;
c = 1;
#100;
a = 1;
b = 1;
c = 0;
#100;
 a = 1;
b = 1;
c = 1;
#100;
end
endmodule
a = 1;
b = 0;
c = 1;
#100;
a = 1;
b = 1;
c = 0;
#100;
a = 1;
b = 1;
c = 1;
#100;
end
endmodule

SCHEMATIC DIAGRAM:
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
RTL Top Level Output File Name : fulladderdirect.ngr
Top Level Output File Name : fulladderdirect
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : Yes
Target Technology : Automotive 9500XL
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs : 5
Cell Usage :
# BELS : 8
# AND2 : 3
# INV : 1
# OR2 : 2
# XOR2 : 2
# IO Buffers : 5
CONCLUSION: Hence the full adder has been designed and implemented
usingVerilog HDL.
 2(iii). Design Of Serial Binary Adder

AIM: To Design and Implement binary adder using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:
SOURCE CODE:
module adder_4bit ( a ,b ,sum ,carry );

output [3:0] sum ;

reg [3:0] sum ;
output carry ;
reg carry ;

input [3:0] a ;
wire [3:0] a ;
input [3:0] b ;
wire [3:0] b ;

integer i;

reg [4:0]s;

always @ (a or b) begin
s[0] = 0;
for (i=0;i<=3;i=i+1) begin
sum [i] = a[i] ^ b[i] ^ s[i];
s[i+1] = (a[i] & b[i]) | (b[i] & s[i]) | (s[i] & a[i]);
end
carry = s[4];
end

endmodule

TEST BENCH:
module add_v;

// Inputs
reg [3:0] a;
reg [3:0] b;

// Outputs
wire [3:0] sum;
wire carry;

// Instantiate the Unit Under Test (UUT)

adder_4bit uut (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
 );

initial begin
// Initialize Inputs
a = 0;
b = 0;

// Wait 100 ns for global reset to finish

#100;
a = 4'b0010;
b = 4'b0011;
#100;
a = 4'b1100;
b = 4'b0101;
#100;

end

endmodule

SCHEMATIC DIAGRAM:
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
===========================================================
* Synthesis Options Summary *
=========================================================
---- Source Parameters
Input File Name : "adder_4bit.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "adder_4bit"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : adder_4bit
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : adder_4bit.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

CONCLUSION: Hence the binary adder has been designed and implemented using
Verilog HDL.
 2(iv).DESIGN OF CARRY LOOK AHEAD ADDER
AIM: To Design and Implement carry look ahead adder using verilog HDL.
TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

SOURCE CODE:
module CLA_4bit(
output [3:0] S,
output Cout,PG,GG,
input [3:0] A,B,
input Cin
);
wire [3:0] G,P,C;
 assign G = A & B; //Generate
assign P = A ^ B; //Propagate
assign C[0] = Cin;
assign C[1] = G[0] | (P[0] & C[0]);
assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);
assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);
assign Cout = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) |(P[3] &
P[2] & P[1] & P[0] & C[0]);
assign S = P ^ C;

assign PG = P[3] & P[2] & P[1] & P[0];

assign GG = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]);
endmodule

TEST BENCH:
module clad_v;

// Inputs
reg [3:0] A;
reg [3:0] B;
reg Cin;

// Outputs
wire [3:0] S;
wire Cout;
wire PG;
wire GG;

// Instantiate the Unit Under Test (UUT)

CLA_4bit uut (
.S(S),
.Cout(Cout),
.PG(PG),
.GG(GG),
.A(A),
.B(B),
.Cin(Cin)
);

initial begin
// Initialize Inputs
A = 0;
B = 0;
Cin = 0;
 // Wait 100 ns for global reset to finish
#100;

A=4'b0001;B=4'b0000;Cin=1'b0;
#10 A=4'b100;B=4'b0011;Cin=1'b0;
#10 A=4'b1101;B=4'b1010;Cin=1'b1;
#10 A=4'b1110;B=4'b1001;Cin=1'b0;
#10 A=4'b1111;B=4'b1010;Cin=1'b0;

end

endmodule

SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:
SYNTHESIS REPORT:
===========================================================
* Synthesis Options Summary *
===========================================================
---- Source Parameters
Input File Name : "CLA_4bit.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "CLA_4bit"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : CLA_4bit
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : CLA_4bit.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

CONCLUSION: Hence the carry look ahead adder has been designed and implemented using
Verilog HDL
 3.DESIGN OF 2 T0 4 DECODER

AIM: To Design and Implement 2 to 4 decoder using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

TRUTH TABLE:
Input E Input Input Output Output Output Output
W1 W0 Y0 Y1 Y2 Y3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
SOURCE CODE:
module dec2to4 (W, Y, En);
input [1:0] W;
input En;
output [0:3] Y;
reg [0:3] Y;

always @(W or En)

begin
case ({En, W})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
end
endmodule

TEST BENCH:
module dec24_v;

// Inputs
reg [1:0] W;
reg En;

// Outputs
wire [0:3] Y;

// Instantiate the Unit Under Test (UUT)

dec2to4 uut (
.W(W),
 .Y(Y),
.En(En)
);

initial begin
// Initialize Inputs
W = 0;
En = 0;

// Wait 100 ns for global reset to finish

#100;
W = 00;
En = 1;
#100;

W = 01;
En = 1;
#100;
W = 10;
En = 1;
#100;
W = 11;
En = 1;
#100;

end

endmodule

SCHEMATIC DIAGRAM:
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
=====================================================================
* Synthesis Options Summary *
=====================================================================

---- Source Parameters

Input File Name : "dec2to4.prj"
Input Format : mixed

---- Target Parameters

Output File Name : "dec2to4"
Output Format : NGC
Target Device : xc3s100e-5-vq100

---- Source Options

Top Module Name : dec2to4
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : dec2to4.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

CONCLUSION: Hence the full adder has been designed and implemented using
Verilog HDL.
 4.DESIGN OF AN 8 TO 3 ENCODER
AIM: To Design and Implement an 8X3encoder using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

TRUTH TABLE:
Input Input Input Input Input Input Input Input Output Output Output
i0 i1 i2 i3 i4 i5 i6 i7 y0 y1 y2
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
SOURCE CODE:
module encoder(i,y);
input [7:0]i;
output [2:0]y;
reg [2:0]y;
always @ (i)
begin
case(i)
8'b00000001:y=3'b000;
8'b00000010:y=3'b001;
8'b00000100:y=3'b010;
8'b00001000:y=3'b011;
8'b00010000:y=3'b100;
8'b00100000:y=3'b101;
8'b01000000:y=3'b110;
8'b10000000:y=3'b111;
default :y=3'b000;
endcase
end
endmodule

TEST BENCH:
module encoder_tb;

// Inputs
reg [7:0] i;
// Outputs
wire [2:0] y;
// Instantiate the Unit Under Test (UUT)
encoder uut (
.i(i),
.y(y)
);
 initial begin
// Initialize Inputs
i = 00000000;
// Wait 100 ns for global reset to finish
#100;
i = 00000010;
#100;
i = 00000100;
#100;
i = 00001000;
#100;
i = 00010000;
#100;
i = 00100000;
#100;
i = 01000000;
#100;
i = 1000000;
#100;

end
endmodule

SCHEMATIC DIAGRAM:
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
RTL Top Level Output File Name : encoder.ngr
Top Level Output File Name : encoder
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : Yes
Target Technology : Automotive 9500XL
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs : 11

Cell Usage :
# BELS : 67
# AND2 : 17
# AND3 : 2
# AND4 : 1
# INV : 25
# OR2 : 20
# OR3 : 2
# IO Buffers : 11
# IBUF : 8
# OBUF : 3

CONCLUSION: Hence an 8X3encoder has been designed and implemented using Verilog HDL.
 5.DESIGN OF 8X1 MULTIPLEXER

AIM: To Design and Implement 8X1 multiplexer using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:
TRUTH TABLE:

Sel S3 Sel S3 Sel S3 Output

0 0 0 A
0 0 1 B
0 1 0 C
0 1 1 D
1 0 0 E
1 0 1 F
1 1 0 G
1 1 1 H

SOURCE CODE:
module MUX8TO1(sel, A,B,C,D,E,F,G,H, MUX_OUT);
input [2:0] sel;
input A,B,C,D,E,F,G,H;
output reg MUX_OUT;
always@(A,B,C,D,E,F,G,H,sel)
begin
case(sel)
3'd0:MUX_OUT=A;
3'd1:MUX_OUT=B;
3'd2:MUX_OUT=C;
3'd3:MUX_OUT=D;
3'd4:MUX_OUT=E;
3'd5:MUX_OUT=F;
3'd6:MUX_OUT=G;
3'd7:MUX_OUT=H;
default:; // indicates null
endcase
end
endmodule
TEST BENCH:
module mux_v;

// Inputs
reg [2:0] sel;
reg A;
reg B;
reg C;
reg D;
reg E;
reg F;
reg G;
reg H;

// Outputs
wire MUX_OUT;

// Instantiate the Unit Under Test (UUT)

MUX8TO1 uut (
.sel(sel),
.A(A),
.B(B),
.C(C),
.D(D),
.E(E),
.F(F),
.G(G),
.H(H),
.MUX_OUT(MUX_OUT)
);

initial begin
// Initialize Inputs
sel = 000;
A = 1;
// Wait 100 ns for global reset to finish
#100;
sel = 001;
B = 0;
 #100;
sel = 010;
C = 1;
#100;
sel = 011;
D = 1;
#100;
sel = 100;
E = 1;
#100;
sel = 101;
F = 1;
#100;
sel = 110;
G = 1;
#100;
sel = 111;
H = 1;
#100;

end

endmodule

SCHEMATIC DIAGRAM:
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
* Synthesis Options Summary *
===========================================================
---- Source Parameters
Input File Name : "MUX8TO1.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "MUX8TO1"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : MUX8TO1
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : MUX8TO1.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

CONCLUSION: Hence the 8X1 multiplexer has been designed and implemented using Verilog
HDL.
 6.DESIGN OF 4 BIT BINARY TO GRAY CODE CONVERTER

AIM: To Design and Implement design of 4 bit binary to gray code converter
using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:
SOURCE CODE:
module GTBmod(out,in);

input [3:0]in;

output [3:0]out;

assign out[3]=in[3];

xor(out[2],out[3],in[2]);

xor(out[1],out[2],in[1]);

xor(out[0],out[1],in[0]);

endmodule

TEST BENCH:
module btg_v;

// Inputs
reg [3:0] in;

// Outputs
wire [3:0] out;

// Instantiate the Unit Under Test (UUT)

GTBmod uut (
.out(out),
.in(in)
);

initial begin
// Initialize Inputs
in = 0000;

// Wait 100 ns for global reset to finish

#100;
in = 0010;
#100;
in = 0011;
#100;
in = 1111;
 #100;

end

endmodule

SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:

SYNTHESIS REPORT:
===========================================================
* Synthesis Options Summary *
===========================================================
---- Source Parameters
Input File Name : "GTBmod.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "GTBmod"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : GTBmod
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : GTBmod.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

CONCLUSION: Hence the4 bit binary to gray code converter has been designed and
implemented using Verilog HDL.
 7(i).DESIGN OF 4:1 MULTIPLEXER

AIM: To Design and Implement 4:1 Multiplexer using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:
SOURCE CODE:
module mux1( select, d, q );

input[1:0] select;
input[3:0] d;
output q;

wire q;
wire[1:0] select;
wire[3:0] d;

assign q = d[select];

end module

TEST BENCH:

module mux_tb;

reg[3:0] d;
reg[1:0] select;
wire q;

Integer i;

mux1 my_mux (select, d, q);

initial
begin
#1 $monitor("d = %b", d, " | select = ", select, " | q = ", q
);

for( i = 0; i <= 15; i = i + 1)

begin
d = i;
select = 0; #1;
select = 1; #1;
select = 2; #1;
select = 3; #1;
$display("-----------------------------------------");
end

end
end module
SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:

SYNTHESIS REPORT:
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "mux1.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "mux1"
Output Format : NGC
Target Device : xa3s400-4-pqg208
- Source Options
Top Module Name : mux1
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : mux1.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

CONCLUSION: Hence the 4 :1 Multiplexer has been designed and implemented using Verilog
HDL.
 7(ii).DESIGN OF 1:4 DEMULTIPLEXER

AIM: To Design and Implement 1:4 Demultiplexer using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

SOURCE CODE:
module demultiplexer1_4 ( din ,x ,y ,a ,b ,c ,d );

output a ;
output b ;
output c ;
output d ;

input din ;
input x ;
input y ;
assign a = din & (~x) & (~y);
assign b = din & (~x) & y;
assign c = din & x & (~y);
assign d = din & x & y;

endmodule

TEST BENCH:
module tb_demux_v;

// Inputs
reg din;
reg x;
reg y;

// Outputs
wire a;
wire b;
wire c;
wire d;
// Instantiate the Unit Under Test (UUT)
demultiplexer1_4 uut (
.din(din),
.x(x),
.y(y),
.a(a),
.b(b),
.c(c),
.d(d)
);
 initial begin
// Initialize Inputs
din = 0; x = 0; y = 0; #100;
din = 0; x = 0; y = 1; #100;
din = 0; x = 1; y = 0; #100;
din = 0; x = 1; y = 1; #100;
din = 1; x = 0; y = 0; #100;
din = 1; x = 0; y = 1; #100;
din = 1; x = 1; y = 0; #100;
din = 1; x = 1; y = 1; #100;

// Add stimulus here

end
endmodule

SCHEMATIC DIAGRAM:

\
SIMULATION WAVEFORM:
SYNTHESIS REPORT:
* Synthesis Options Summary *
=====================================================================
---- Source Parameters
Input File Name : "demultiplexer1_4.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "demultiplexer1_4"
Output Format : NGC
Target Device : xa3s400-4-pqg208
---- Source Options
Top Module Name : demultiplexer1_4
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : demultiplexer1_4.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

CONCLUSION: Hence the 1:4Demultiplexer has been designed and implemented using
Verilog HDL.
 7(iii).DESIGN OF 4 BIT COMPARATOR

AIM: To Design and Implement 4 bit comparator using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:
SOURCE CODE:
module compare (A, B, AeqB, AgtB, AltB);
input [3:0] A, B;
output AeqB, AgtB, AltB;
reg AeqB, AgtB, AltB;

always @(A or B)
begin
AeqB = 0;
AgtB = 0;

AltB = 0;
if(A == B)
AeqB = 1;
else if (A > B)
AgtB = 1;
else
AltB = 1;
end

endmodule

TEST BENCH:

module comp4_v;

// Inputs
reg [3:0] A;
reg [3:0] B;

// Outputs
wire AeqB;
wire AgtB;
wire AltB;

// Instantiate the Unit Under Test (UUT)

compare uut (
.A(A),
.B(B),
.AeqB(AeqB),
.AgtB(AgtB),
.AltB(AltB)
);
 initial begin
// Initialize Inputs
A = 0;
B = 0;

// Wait 100 ns for global reset to finish

#100;
A = 0010;
B = 0001;
#100;
A = 0101;
B = 0101;
#100;
A = 0011;
B = 0101;
#100;
end

endmodule

SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:
SYNTHESIS REPORT:
=====================================================================
* Synthesis Options Summary *
=====================================================================
---- Source Parameters
Input File Name : "compare.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "compare"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : compare
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : compare.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

CONCLUSION: Hence the 4 bit comparator has been designed and implemented using Verilog
HDL.

8.DESIGN OF FULL ADDER USING 3 MODELING STYLES

AIM: To Design and Implement Full adder using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:
SOURCE CODE:
FULL ADDER IN DATA FLOW MODEL

module full_adder ( a ,b ,c ,sum ,carry );

output sum ;
output carry ;
input a ;
input b ;
input c ;
assign sum = a ^ b ^ c;
assign carry = (a&b) | (b&c) | (c&a);
endmodule

FULL ADDER IN STRUCTURAL MODEL

Module half_add(x,y,s,c);

Input x,y;

Output s,c;

Xor sum(s,x,y);
And carry(c,x,y);

endmodule

Module full_add(A,B,CI,S,CO);

Input A,B,CI;

Output S,CO;

Wire S1,C1,C2;

Half_add PARTSUM(A,B,S1,C1);

SUM(S1,C1,SW,C2);

Carry(c0,c2,c1);

Endmodule

FULL ADDER IN STRUCTURAL MODEL

Module fa_bhv(a,b,ci,s,co);

Input a,b,ci;

Output s,co;

always@(a or b or ci)

begin

s=a^b^ci;

co=(a&b) | (a&ci) | (b&ci);

end

endmodule

TEST BENCH:
module full_adder
(in_x, in_y, carry_in, sum_out,
carry_out);

input in_x;
input in_y;
input carry_in;
output sum_out;
output carry_out;

wire w_sum1;
wire w_carry1;
wire w_carry2;

assign carry_out = w_carry1 | w_carry2;

// Instantiate two half-adders to make the circuit. Click here for

half-adder rtl

half_adder u1_half_adder
(
.in_x(in_x),
.in_y(in_y),
.out_sum(w_sum1),
.out_carry(w_carry1)
);
half_adder u2_half_adder
(
.in_x(w_sum1),
.in_y(carry_in),
.out_sum(sum_out),
.out_carry(w_carry2)
);
endmodule

SCHEMATIC DIAGRAM:
SYNTHESIS WAVEFORM:
SYNTHESIS REPORT:
* Synthesis Options Summary *
---- Source Parameters
Input File Name : "full_adder.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "full_adder"
Output Format : NGC
Target Device : Automotive 9500XL

---- Source Options

Top Module Name : full_adder
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : YES
Resource Sharing : YES

---- Target Options

Add IO Buffers : YES
MACRO Preserve : YES
XOR Preserve : YES
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : full_adder.lso
Keep Hierarchy : YES
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Verilog 2001 : YES

---- Other Options

Clock Enable : YES
wysiwyg : NO
======================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : full_adder.ngr
Top Level Output File Name : full_adder
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : YES
Target Technology : Automotive 9500XL
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO

Design Statistics
# IOs : 5

Cell Usage :
# BELS : 8
# AND2 : 3
# INV : 1
# OR2 : 2
# XOR2 : 2
# IO Buffers : 5
# IBUF : 3
# OBUF : 2
=========================================================================
CPU : 1.92 / 2.39 s | Elapsed : 2.00 / 3.00 s

-->

Total memory usage is 116932 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

CONCLUSION: Hence Full adder has been designed and implemented using Verilog HDL.
 9(i).DESIGN OF SR FLIPFLOP

AIM: To Design and Implement SR flipflop using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

TRUTH TABLE:
SOURCE CODE:
module srffdf(s,r,clk,q,qb);

input s,r,clk;

inout q,qb;

wire s1,r1;

assign s1=!(s & clk);

assign r1=!(r&clk);

assign q=!(s1&qb);

assign qb=!(r1&q);

endmodule

TEST BENCH:
module srff_v;

// Inputs
reg s;
reg r;
reg clk;

// Bidirs
wire q;
wire qb;

// Instantiate the Unit Under Test (UUT)

srffdf uut (
.s(s),
.r(r),
 .clk(clk),
.q(q),
.qb(qb)
);
initial begin
// Initialize Inputs
s = 0;
r = 0;
clk = 1;

// Wait 100 ns for global reset to finish

#100;
s = 0;
r = 1;
clk = 1;
#100;
s = 1;
r = 0;
clk = 1;
#100;
s = 1;
r = 1;
clk = 1;
#100;
end

endmodule

SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:
SYNTHESIS REPORT:
===========================================================
* Synthesis Options Summary *
===========================================================
---- Source Parameters
Input File Name : "srffdf.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "srffdf"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : srffdf
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : srffdf.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

CONCLUSION: Hence the SR flipflop has been designed and implemented using Verilog HDL.
 9(ii).DESIGN OF D FLIPFLOP

AIM: To Design and Implement D flipflop using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:
TRUTH TABLE:

SOURCE CODE:
module dflipflopmod(q, d, clk);

output q;

input d;

input clk;

reg q;

always @(posedge clk)

q=d;

endmodule

TEST BENCH:
module dfg_v;

// Inputs
reg d;
reg clk;

// Outputs
 wire q;

// Instantiate the Unit Under Test (UUT)

dflipflopmod uut (
.q(q),
.d(d),
.clk(clk)
);

initial begin
// Initialize Inputs
d = 0;
clk = 0;

// Wait 100 ns for global reset to finish

#100;
d = 1;
clk = 1;
#100;
d = 0;
clk = 1;
#100;
end

endmodule
SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:

SYNTHESIS REPORT:
=====================================================================
* Synthesis Options Summary *
=====================================================================
---- Source Parameters
Input File Name : "dflipflopmod.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "dflipflopmod"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : dflipflopmod
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : dflipflopmod.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

CONCLUSION: Hence the D flipflop has been designed and implemented using
Verilog HDL.
 9(iii).DESIGN OF JK FLIPFLOP

AIM: To Design and Implement JK flipflop using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

TRUTH TABLE:
SOURCE CODE:
module JK_flip_flop ( j ,k ,clk ,reset ,q ,qb );
output q ;
reg q ;
output qb ;
reg qb ;
input j ;
wire j ;
input k ;
wire k ;
input clk ;
wire clk ;
input reset ;
wire reset ;
always @ (posedge (clk)) begin
if (reset) begin
q <= 0;
qb <= 1;
end
else begin
if (j!=k) begin
q <= j;
qb <= k;
end
else if (j==1 && k==1) begin
q <= ~q;
qb <= ~qb;
end
end
end

endmodule
TEST BENCH:
module JK_v;

// Inputs
reg j;
reg k;
reg clk;
reg reset;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
JK_flip_flop uut (
.j(j),
.k(k),
.clk(clk),
.reset(reset),
.q(q),
.qb(qb)
);
initial begin
// Initialize Inputs
j = 0;
k = 0;
clk = 1;
reset = 1;
 // Wait 100 ns for global reset to finish
#100;
j = 0;
k = 1;
clk = 1;
reset = 1;
#100;
j = 1;
k = 0;
clk = 1;
reset = 1;
#100;
j = 1;
k = 1;
clk = 1;
reset = 1;
#100;
end
endmodule

SCHEMATIC DIAGRAM:
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "JK_flip_flop.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "JK_flip_flop"
Output Format : NGC
Target Device : xc3s100e-5-vq100

---- Source Options

Top Module Name : JK_flip_flop
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : JK_flip_flop.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
CONCLUSION: Hence the JKflipflop has been designed and implemented using
Verilog HDL
 9(iv).DESIGN OF T FLIPFLOP

AIM: To Design and Implement T flipflop using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:
TRUTH TABLE:

SOURCE CODE:
module t(t,clk,q,qb);
input t;
input clk;
output reg q,qb;
initial
begin q=0;qb=1; end

always@(posedge clk)
begin
if(clk)
begin
case(t)
1'b0:begin q=q;qb=qb; end
1'b1:begin q=~q;qb=~qb; end
endcase
end
end
endmodule

TEST BENCH:
module tfft_v;

// Inputs
reg t;
reg clk;
// Outputs
wire q;
wire qb;

// Instantiate the Unit Under Test (UUT)

t uut (
.t(t),
.clk(clk),
.q(q),
.qb(qb)
);

initial begin
// Initialize Inputs
t = 0;
clk = 0;

// Wait 100 ns for global reset to finish

#100;
t = 0;
clk = 1;
#100;
t = 1;
clk = 1;
#100;
end
endmodule

SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:

SYNTHESIS REPORT:
===========================================================
* Synthesis Options Summary *
===========================================================
---- Source Parameters
Input File Name : "t.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "t"
Output Format : NGC
Target Device : xc3s100e-5-vq100

---- Source Options

Top Module Name : t
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : t.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

CONCLUSION: Hence the T flipflop has been designed and implemented using
Verilog HDL.
 10(i).DESIGN OF 4 BIT BINARY COUNTER

AIM: To Design and Implement 4 bit binary counter using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:
SOURCE CODE:
module Counter_4Bit ( clk ,reset ,dout );

output [3:0] dout ;

reg [3:0] dout ;

input clk ;
wire clk ;
input reset ;
wire reset ;

initial dout = 0;

always @ (posedge (clk)) begin

if (reset)
dout <= 0;
else
dout <= dout + 1;
end
endmodule

TEST BENCH:
module bc4_v;

// Inputs
reg clk;
reg reset;

// Outputs
wire [3:0] dout;

// Instantiate the Unit Under Test (UUT)

Counter_4Bit uut (
.clk(clk),
.reset(reset),
.dout(dout)
);

initial begin
// Initialize Inputs
clk = 0;
reset = 0;

// Wait 100 ns for global reset to finish

 #100;
clk =0;
reset = 1;
#100;
clk = 1;
reset = 0;
#100;
end

endmodule

SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:
SYNTHESIS REPORT:
=====================================================================
* Synthesis Options Summary *
=====================================================================
---- Source Parameters
Input File Name : "Counter_4Bit.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "Counter_4Bit"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : Counter_4Bit
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : Counter_4Bit.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

CONCLUSION: Hence the 4 bit binary counter has been designed and implemented using
Verilog HDL.
 10(ii).DESIGN OF 4 BIT BCD COUNTER

AIM: To Design and Implement 4 bit BCDcounter using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

SOURCE CODE:
module BCD_Counter ( clk ,reset ,dout );

output [3:0] dout ;

reg [3:0] dout ;
input clk ;
wire clk ;
input reset ;
wire reset ;
initial dout = 0 ;
always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else if (dout<=9) begin
dout <= dout + 1;
end else if (dout==9) begin
dout <= 0;
end
end
endmodule

TEST BENCH:
module bcdc4_v;

// Inputs
reg Clock;
reg Clear;
reg E;

// Outputs
wire [3:0] BCD1;
wire [3:0] BCD0;

// Instantiate the Unit Under Test (UUT)

BCDcountmod uut (
.Clock(Clock),
.Clear(Clear),
.E(E),
.BCD1(BCD1),
.BCD0(BCD0)
);

initial begin
// Initialize Inputs
Clock = 0;
Clear = 0;
E = 0;

// Wait 100 ns for global reset to finish

#100;
Clock = 1;
Clear = 0;
 E =1;
#100;
Clock = 1;
Clear = 1;
E = 1;
#100;
end
endmodule

SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:

SYNTHESIS REPORT:
===========================================================
* Synthesis Options Summary *
===========================================================
---- Source Parameters
Input File Name : "BCD_Counter.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "BCD_Counter"
Output Format : NGC
Target Device : xc3s100e-5-vq100

---- Source Options

Top Module Name : BCD_Counter
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : BCD_Counter.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

CONCLUSION: Hence the 4 bit BCD counter has been designed and implemented using
Verilog HDL.
 Introduction to Cadence User Manual (IC614)

This User Manual is provided by the Cadence Design Systems Support Team and has been
integrated into our lab manual.Objective of this lab is to learn the Virtuoso tool as well learn the
flow of the Full Custom IC design cycle. You will finish the lab by running DRC, LVS and
Parasitic Extraction on the various designs. In the process you will create various components like
inverter, differential amplifier, operational amplifier etc.Start the lab by creating a library called
“myDesignLib” and attach the library to a technology library called “gpdk180”. Attaching a
technology library will ensure that you can do front to back design.

Create a new cell called “Inverter” with schematic view and hence build the inverter
schematic by instantiating various components. Once inverter schematic is done, symbol for
“Inverter” is generated. Now you will create a new cell view called “Inverter_Test”, where you
will instantiate “Inverter” symbol. This circuit is verified by doing various simulations using
spectre. In the process, you will learn to use spectre, waveform window options, waveform
calculator, etc...You will learn the Layout Editor basics by concentrating on designing an
“Inverter” through automatic layout generation. Then you will go ahead with completing the
other layouts. After that, you will run DRC, LVS checks on the layout, Extract parasitics and back-
annotate them to the simulation environment.After completing the parasitic back- annotation flow,
design is ready for generating GDSII.

General Notes
There are a number of things to consider before beginning these lab exercises. Please read
through this section completely, and perform any needed steps in order to ensure a successful
workshop. These labs were designed for use with Incisive Unified Simulator82, IC613 and
Assura32.

Before running any of these labs, ensure that you’ve set up IUS82, IC613, MMSIM71 and
Assura32 correctly:
 %> setenv CDSHOME <IC614-installation-home>

%> setenv MMSIMHOME <MMSIM71-installation-home>

%> setenv PVHOME <Assura32-installation-home>

%> setenv AMSHOME <IUS82-installation-home>

You will also need to ensure that the IUS82 is setup correctly for lab 5.
To setup the lab environment, please perform the following steps:
1. Ensure the software mentioned above is correctly setup.
2. Source the C-Shell related commands file i.e. (cshrc file).
These labs were designed to be run using Cadence Virtuoso tool and Assura tool.

Lab Getting Started

1. Log in to your workstation using the username and password. The home directory has a cshrc
file with paths to the Cadence installation.
2. In a terminal window, type csh at the command prompt to invoke the C shell.
>csh
>source cshrc

3. To verify that the path to the software is properly set in the cshrc file, type the below command
in the terminal window and enter:
>which virtuoso
It gives the complete path of IC614 tool Installation.
>which spectre
It gives the complete path of MMSIM71 tool Installation.
>which assura
It gives the complete path of Assura32 tool Installation.
>which ncsim
It gives the complete path of IUS82 tool Installation.
Starting the Cadence Software
Use the installed database to do your work and the steps are as follows:
1. Change to the course directory by entering this command:
> cd ~/Database/cadence_analog_labs_614
You will start the Cadence Design Framework II environment from this directory because it
contains cds.lib, which is the local initialization file. The library search paths are defined in this
file.
The Cadence_Analog_labs_614 directory contains Solutions folder and also Work folder.
Inside Work folder you can create new cell / modifications of the cell locally without affecting
your Source cell present inside Solutions directory.

Lab directory details:

. /Solution Contains a local copy of all the lab experiments including test circuit for
simulation.
. /libs.cdb Contains a technology library for the design (gpdk180nm).
. /models Contains spectre models of components for simulation in gpdk180nm
technology.
. /stream Contains layer map file for GDSII format
. /pv Containing the Assura and Diva verification files
. /techfiles Contains ASCII versions of the oa22 techfiles

. /dig_source Contains verilog codes for SAR register and clock

. /cds.lib File containing pointer to the Cadence OA22 initialization file.

. /hdl.var File defines the work library for AMS simulation
. /docs Reference manual and user manual for gpdk180nm technology
2. In the same terminal window, enter:
> virtuoso &
The virtuoso or Command Interpreter Window (CIW) appears at the bottom of the screen.

3.If the “What’s New ...” window appears, close it with the File— Close command.
3. 4. Keep opened CIW window for the labs.
 1.Introduction to Layout Design Rules

➢ The physical mask layout of any circuit to be manufactured using a particular

process must conform to a set of geometric constraints or rules, which are
generally called layout design rules.

➢ These rules usually specify the minimum allowable line widths for physical
objects on-chip such as metal and polysilicon interconnects or diffusion areas,
minimum feature dimensions, and minimum allowable separations between two
such features.

➢ The main objective of design rules is to achieve a high overall yield and
reliability while using the smallest possible silicon area, for any circuit to be
manufactured with a particular process.

➢ The layout design rules which are specified for a particular fabrication process
normally represent a reasonable optimum point in terms of yield and density

➢ A layout which violates some of the specified design rules may still result in an
operational circuit with reasonable yield, whereas another layout observing all
specified design rules may result in a circuit which is not functional and/or has
very low yield.

➢ To summarize, we can say, in general, that observing the layout design rules
significantly increases the probability of fabricating a successful product with
high yield.

The design rules are usually described in two ways :

✓ Micron rules, in which the layout constraints such as minimum feature sizes and
minimum allowable feature separations, are stated in terms of absolute dimensions in
micrometers, or,
✓Lambda rules, which specify the layout constraints in terms of a single parameter (?) and,
thus, allow linear, proportional scaling of all geometrical constraints.

Lambda-based layout design rules were originally devised to simplify the industry- standard
micron-based design rules and to allow scaling capability for various processes.

It must be emphasized, however, that most of the submicron CMOS process design
rules do not lend themselves to straightforward linear scaling.

The use of lambda-based design rules must therefore be handled with caution in sub-
micron geometries. In the following, we present a sample set of the lambda-based layout
design rules devised for the MOSIS CMOS process.
 MOSIS Layout Design Rules (sample set)

RULE L-
Description
Number Rule
R1 3L
Minimum active area width

R2 Minimum active area spacing 3L

R3 Minimum poly width 2L

R4 Minimum poly spacing 2L

R5 Minimum gate extension of poly over active 2L

Minimum poly-active edge spacing 1L

R6
(poly outside active area)

Minimum poly-active edge spacing (poly

R7 3L
inside active area)

R8 Minimum metal width 3L

R9 Minimum metal spacing 3L

2 L
R10 Poly contact size

R11 Minimum poly contact spacing 2L

R12 Minimum poly contact to poly edge spacing 1L

R13 Minimum poly contact to metal edge spacing 1L

R14 Minimum poly contact to active edge spacing 3L

R15 Active contact size 2L

R16 Minimum active contact spacing (on 2L

the same active region)

Minimum active contact to active

1L
R17 edge spacing

R18 Minimum active contact to metal edge spacing 1L

R19 Minimum active contact to poly edge spacing 3L
 2(i).CMOS INVERTER
Schematic Capture
 Schematic Entry
Objective: To create a library and build a schematic of an Inverter

Below steps explain the creation of new library “myDesignLib” and we will use the
same throughout this course for building various cells that we going to create in the
next labs. Execute Tools – Library Manager in the CIW or Virtuoso window to open
Library Manager.

Creating a New library

1. In the Library Manager, execute File - New – Library. The new library form
appears.

2.In the “New Library” form, type “myDesignLib” in the Name section.
 3.In the field of Directory section, verify that the path to the library is set
to ~/Database/cadence_analog_labs_613 and click OK.
Note: A technology file is not required if you are not interested to do the layouts
for the design.
4.In the next “Technology File for New library” form, select option Attach to an
existing techfile and click OK.

5.In the “Attach Design Library to Technology File” form, select gpdk180 from the
cyclic field and click OK.

6.After creating a new library you can verify it from the library manager.

7.If you right click on the “myDesignLib” and select properties, you will find
that gpdk180 library is attached as techlib to “myDesignLib”.
 Creating a Schematic Cellview

In this section we will learn how to open new schematic window in the new
myDesignLib” library and build the inverter schematic as shown in the figure at the
start of this lab.

1. In the CIW or Library manager, execute File – New – Cellview.

2.Set up the New file form as follows:

Do not edit the Library path file and the one above might be different from the path
shown in your form.
2. Click OK when done the above settings. A blank schematic window for the
Inverter design appears.

Adding Components to schematic

1. In the Inverter schematic window, click the Instance fixed menu icon to display

the Add Instance form.

Tip: You can also execute Create — Instance or press i.

2.Click on the Browse button. This opens up a Library browser from which you can
select components and the symbol view .

You will update the Library Name, Cell Name, and the property values given in
the table on the next page as you place each component.

3.After you complete the Add Instance form, move your cursor to the schematic
window and click left to place a component.

This is a table of components for building the Inverter schematic.

Library name Cell Name Properties/Comments

gpdk180 pmos For M0: Model name = pmos1, W=

wp, L=180n
gpdk180 nmos For M1: Model name = nmos1, W=
2u, L=180n
If you place a component with the wrong parameter values, use the Edit—
Properties— Objects command to change the parameters.

Use the Edit— Move command if you place components in the wrong location.

You can rotate components at the time you place them, or use the Edit— Rotate
command after they are placed.
2.After entering components, click Cancel in the Add Instance form or press Esc with
your cursor in the schematic window.

Adding pins to Schematic

1. Click the Pin fixed menu icon in the schematic window. You can also
execute

create — Pin or press p.

The Add pin form appears.

2. Type the following in the Add pin form in the exact order leaving space between the
pin names.

Pin Names Direction

Vin Input

Vout Output

Make sure that the direction field is set to input/output/inputOutput when placing the
input/output/inout pins respectively and the Usage field is set to schematic.

3.Select Cancel from the Add – pin form after placing the pins. In the schematic

window, execute Window— Fit or press the f bindkey.

 Adding Wires to a Schematic

Add wires to connect components and pins in the design.

1. Click the Wire (narrow) icon in the schematic window.

You can also press the w key, or execute Create — Wire (narrow).

2. In the schematic window, click on a pin of one of your components as the first
point for your wiring. A diamond shape appears over the starting point of this wire.

3. Follow the prompts at the bottom of the design window and click left on the
destination point for your wire. A wire is routed between the source and destination
points.

4. Complete the wiring as shown in figure and when done wiring press ESC key in
the schematic window to cancel wiring.

Saving the Design

1. Click the Check and Save icon in the schematic editor window.

2. Observe the CIW output area for any errors.

symbol Creation

Objective: To create a symbol for the Inverter

In this section, you will create a symbol for your inverter design so you can place it in
a test circuit for simulation. A symbol view is extremelyimportant step in the design
process. The symbol view must exist for the schematic to be used in a hierarchy. In
addition, the symbol has attached properties (cdsParam) that facilitate the simulation
and the design of the circuit.

1. In the Inverter schematic window, execute Create — Cellview— From Cellview.

The Cellview From Cellview form appears. With the Edit Options function active,
you can control the appearance of the symbol to generate.

2. Verify that the From View Name field is set to schematic, and the To View
Name
field is set to symbol, with the Tool/Data Type set as SchematicSymbol.

3. Click OK in the Cellview From Cellview form.

The Symbol Generation Form appears.

 4. Modify the Pin Specifications as follows:

5. click OK in the Symbol Generation Options form.

6. A new window displays an automatically created Inverter symbol as shown here.
 Editing a Symbol

In this section we will modify the inverter symbol to look like a Inverter gate symbol.

1. Move the cursor over the automatically generated symbol, until the green
rectangle is highlighted, click left to select it.

2. Click Delete icon in the symbol window, similarly select the red rectangle and
delete that.

3. Execute Create – Shape – polygon, and draw a shape similar to triangle.

4. After creating the triangle press ESC key.

5. Execute Create – Shape – Circle to make a circle at the end of triangle.

6. You can move the pin names according to the location.

7. Execute Create — Selection Box. In the Add Selection Box form,

click
Automatic.A new red selection box is automatically added.

8. After creating symbol, click on the save icon in the symbol editor window to save
the symbol. In the symbol editor, execute File — Close to close the symbol view
window.
 Building the Inverter_Test Design
Objective: To build an Inverter Test circuit using your Inverter

Creating the Inverter_Test Cellview

You will create the Inverter_Test cellview that will contain an instance of the Inverter
cellview. In the next section, you will run simulation on this design

1.In the CIW or Library Manager, execute File— New— Cellview.

2.Set up the New File form as follows:

1.Click OK when done. A blank schematic window for the Inverter_Test design
appears.

Building the Inverter_Test Circuit

1. Using the component list and Properties/Comments in this table, build

the

Inverter_Test schematic.

Library name Cellview name Properties/Comments

myDesignLib Inverter Symbol

analogLib vpulse ton=10n,

v1=0, T=20n
v2=1.8,td=0
analogLib vdc, gnd tr=tf=1ns,
vdc=1.8

Note: Remember to set the values for VDD and VSS. Otherwise, your circuit will
have no power.
 2. Add the above components using Create — Instance or by pressing I.

3. Click the Wire (narrow) icon and wire your schematic.

Tip: You can also press the w key, or execute Create— Wire (narrow).

4. Click Create — Wire Name or press L to name the input (Vin) and output (Vout)

wires as in the below schematic.

5. Click on the Check and Save icon to save the design.

6. The schematic should look like this.

7.The schematic should look like this.

8.Leave your Inverter_Test schematic window open for the next section.

Analog Simulation with Spectre

Objective: To set up and run simulations on the Inverter_Test design

In this section, we will run the simulation for Inverter and plot the transient, DC
characteristics and we will do Parametric Analysis after the initial simulation.

Starting the Simulation Environment

Start the Simulation Environment to run a simulation.

1. In the Inverter_Test schematic window, execute
 Launch – ADE L
The Virtuoso Analog Design Environment (ADE) simulation window appears.

Choosing a Simulator
Set the environment to use the Spectre® tool, a high speed, highly accurate analog
simulator. Use this simulator with the Inverter_Test design, which is made-up of
analog components.

1.In the simulation window (ADE), execute

Setup— Simulator/Directory/Host.

1. In the Choosing Simulator form, set the Simulator field to spectre(Not spectreS)
and click OK.
Setting the Model Libraries
The Model Library file contains the model files that describe the nmos and pmos
devices during simulation.

1. In the simulation window (ADE), Execute Setup - Model Libraries. The

Model Library Setup form appears. Click the browse button to add
gpdk.scs if not added by default as shown in the Model Library Setup form.

Remember to select the section type as stat in front of the gpdk.scs file. Your Model
Library Setup window should now looks like the below figure.

To view the model file, highlight the expression in the Model Library File field
and Click Edit File

2. To complete the Model Library Setup, move the cursor and click OK. The Model
Library Setup allows you to include multiple model files. It also allows you to use the
Edit button to view the model file.

Choosing Analyses
This section demonstrates how to view and select the different types of analyses
to complete the circuit when running the simulation.

1. In the Simulation window (ADE), click the Choose - Analyses icon.

You can also execute Analyses - Choose.

The Choosing Analysis form appears. This is a dynamic form, the bottom of the form
changes based on the selection above.
2. To setup for transient analysis
a. In the Analysis section select tran
b. Set the stop time as 200n
c. Click at the moderate or Enabled button at the bottom, and then click

Apply.

3. To set up for DC Analyses:

a. In the Analyses section, select dc.

 b. In the DC Analyses section, turn on Save DC Operating Point.
c. Turn on the Component Parameter.
d. Double click the Select Component, Which takes you to the schematic
window.

e. Select input signal vpulse source in the test schematic window.

f. Select “DC Voltage” in the Select Component Parameter form and click
OK.
g.In the analysis form type start and stop voltages as 0 to 1.8 respectively.
h. Check the enable button and then click Apply.

i. Click OK in the Choosing Analyses Form.

Setting Design Variables

Set the values of any design variables in the circuit before simulating. Otherwise, the
simulation will not run.
In the Simulation window, click the Edit Variables icon.

The Editing Design Variables form appears.

1. Click Copy From at the bottom of the form. The design is scanned and all
variables found in the design are listed. In a few moments, the wp variable appears
in the Table of Design variables section.

2. Set the value of the wp variable: With the wp variable highlighted in the Table of
Design Variables, click on the variable name wp and enter the following:

2u

Value(Expr)

Click Change and notice the update in the Table of Design Variables.
3. Click OK or Cancel in the Editing Design Variables window.

Selecting Outputs for Plotting

1. Execute Outputs – To be plotted – Select on Schematic in the simulation
window.

2. Follow the prompt at the bottom of the schematic window, Click on output net
Vout, input net Vin of the Inverter. Press ESC with the cursor in the schematic after
selecting it.

Does the simulation window look like this?

Running the Simulation
1. Execute Simulation – Netlist and Run in the simulation window to start the
Simulation or the icon, this will create the netlist as well as run the simulation.
2. When simulation finishes, the Transient, DC plots automatically will be popped
up along with log file.

Saving the Simulator State

We can save the simulator state, which stores information such as model library
file, outputs, analysis, variable etc. This information restores the simulation
environment without having to type in all of setting again.
1. In the Simulation window, execute Session – Save State. The Saving State form
appears.

2. Set the Save as field to state1_inv and make sure all options are selected under
what to save field.

3. Click OK in the saving state form. The Simulator state is saved.

Loading the Simulator State

1. From the ADE window execute Session – Load State.

2. In the Loading State window, set the State name to state1_inv as shown
3. Click OK in the Loading State window.
 Parametric Analysis

Parametric Analysis yields information similar to that provided by the Spectre® sweep
feature, except the data is for a full range of sweeps for each parametric step. The
Spectre sweep feature provides sweep data at only one specified condition.

You will run a parametric DC analysis on the wp variable, of the PMOS device of the
Inverter design by sweeping the value of wp.

Run a simulation before starting the parametric tool. You will start by loading
the state from the previous simulation run.
Run the simulation and check for errors. When the simulation ends, a single
waveform in the waveform window displays the DC Response at the Vout node.

Starting the Parametric Analysis Tool

1. In the Simulation window, execute Tools—Parametric Analysis. The Parametric
Analysis form appears.

2. In the Parametric Analysis form, execute Setup—Pick Name For Variable—

Sweep 1.

A selection window appears with a list of all variables in the design that you can
sweep. This list includes the variables that appear in the Design Variables section of
the Simulation window.

3. In the selection window, double click left on wp.

The Variable Name field for Sweep 1 in the Parametric Analysis form is set to wp.

4. Change the Range Type and Step Control fields in the

Parametric Analysis form as shown below:

Range Type From/To From 1u To 10u

Step Control Auto Total Steps 10

These numbers vary the value of the wp of the pmos between 1um and 10um at ten
evenly spaced intervals.

5. Execute Analysis—Start.
The Parametric Analysis window displays the number of runs remaining in the
analysis and the current value of the swept variable(s). Look in the upper right corner
of the window. Once the runs are completed the wavescan window comes up with the
plots for different runs.
Note: Change the wp value of pmos device back to 2u and save the schematic before

proceeding to the next section of the lab. To do this use edit property option.
Creating Layout View of Inverter
1. From the Inverter schematic window menu execute
Launch – Layout XL. A Startup Option form appears.

2. Select Create New option. This gives a New Cell View Form
3. Check the Cellname (Inverter), Viewname (layout).
4. Click OK from the New Cellview form.
LSW and a blank layout window appear along with schematic window.

Adding Components to Layout

1. Execute Connectivity – Generate – All from Source or click the icon in
the layout editor window, Generate Layout form appears. Click OK which imports
the schematic components in to the Layout window automatically.

2. Re arrange the components with in PR-Boundary as shown in the next page.

3. To rotate a component, Select the component and execute Edit –Properties.
Now select the degree of rotation from the property edit form.

4. To Move a component, Select the component and execute Edit -Move command.

Making interconnection

1. Execute Connectivity –Nets – Show/Hide selected Incomplete Nets or click

the icon in the Layout Menu.

2. Move the mouse pointer over the device and click LMB to get the connectivity
information, which shows the guide lines (or flight lines) for the inter connections of
the components.

3. From the layout window execute Create – Shape – Path/ Create wire or Create –
Shape – Rectangle (for vdd and gnd bar) and select the appropriate Layers from the
LSW window and Vias for making the inter connections

Creating Contacts/Vias
You will use the contacts or vias to make connections between two different layers.
1. Execute Create — Via or select command to place different Contacts,
as given in below table
Connection Contact Type

For Metal1-Poly Metal1-Pol

Connection

For Metal1- Psubstrate

Connection

For Metal1-Nwell
Metal1-
Nwell
Connection
 Saving the design

1. Save your design by selecting File — Save or click to save the layout,
and layout should appear as below.
 Physical Verification

Assura DRC

Running a DRC

1. Open the Inverter layout form the CIW or library manger if you have closed that.
Press shift – f in the layout window to display all the levels.
2. Select Assura - Run DRC from layout window. The DRC form appears. The
Library and Cellname are taken from the current design window, but rule file may
be missing. Select the Technology as gpdk180. This automatically loads the rule
file.
Your DRC form should appear like this
3. Click OK to start DRC.
4. A Progress form will appears. You can click on the watch log file to see the
log file.
5. When DRC finishes, a dialog box appears asking you if you want to view
your DRC results, and then click Yes to view the results of this run.
6. If there any DRC error exists in the design View Layer Window (VLW) and
Error Layer Window (ELW) appears. Also the errors highlight in the design
itself.
7. Click View – Summary in the ELW to find the details of errors.
8. You can refer to rule file also for more information, correct all the DRC errors and
Re – run the DRC.

9. If there are no errors in the layout then a dialog box appears with No DRC errors
found written in it, click on close to terminate the DRC run.

ASSURA LVS

In this section we will perform the LVS check that will compare the schematic netlist
and the layout netlist.

Running LVS

1. Select Assura – Run LVS from the layout window. The Assura Run LVS form
appears. It will automatically load both the schematic and layout view of the cell.

2. Change the following in the form and click OK.

3. The LVS begins and a Progress form appears.

4. If the schematic and layout matches completely, you will get the form
displaying
Schematic and Layout Match.
5. If the schematic and layout do not matches, a form informs that the LVS
completed successfully and asks if you want to see the results of this run.
6. Click Yes in the form LVS debug form appears, and you are directed into LVS
debug environment.

7. In the LVS debug form you can find the details of mismatches and you need to
correct all those mismatches and Re – run the LVS till you will be able to match the
schematic with layout.
 Assura RCX

In this section we will extract the RC values from the layout and perform analog
circuit simulation on the designs extracted with RCX. Before using RCX to extract
parasitic devices for simulation, the layout should match with schematic completely
to ensure that all parasites will be backannoted to the correct schematic nets.

Running RCX
1. From the layout window execute Assura – Run RCX.
2. Change the following in the Assura parasitic extraction form. Select output type
under Setup tab of the form.

3. In the Extraction tab of the form, choose Extraction type, Cap Coupling Mode
and specify the Reference node for extraction.
4. In the Filtering tab of the form, Enter Power Nets as vdd!, vss! and Enter
Ground Nets as gnd!

5. Click OK in the Assura parasitic extraction form when done. The RCX progress
form appears, in the progress form click Watch log file to see the output log file.

6.When RCX completes, a dialog box appears, informs you that Assura RCX
run Completed successfully.
7.You can open the av_extracted view from the library manager and view the
parasitic.
 Creating the Configuration View

In this section we will create a config view and with this config view we will run
the Simulation with and without parasitic.
1. In the CIW or Library Manager, execute File – New – Cellview

2. In the Create New file form, set the following:

3. Click OK in create New File form. The Hierarchy Editor form opens and a
New Configuration form opens in front of it.

4. Click Use template at the bottom of the New Configuration form and select
Spectre in the cyclic field and click OK. The Global Bindings lists are loaded from
the template.
 5. Change the Top Cell View to schematic and remove the default entry from the

Library List field.

6. Click OK in the New Configuration form.

The hierarchy editor displays the hierarchy for this design using table format.

6. Click the Tree View tab. The design hierarchy changes to tree format. The
form should look like this:

Save the current configuration.

7. Close the Hierarchy Editor window. Execute File – Close Window.

 To run the Circuit without Parasites

1. From the Library Manager open Inverter_Test Config view.

Open Configuration or Top cellview form appears.

2. In the form, turn on the both cyclic buttons to Yes and click OK.

The Inverter_Test schematic and Inverter_Test config window appears. Notice the
window banner of schematic also states Config: myDesignLib Inverter_Test
config.

3. Execute Launch – ADE L from the schematic window.

4. Now you need to follow the same procedure for running the simulation.
Executing Session– Load state, the Analog Design Environment window loads
the previous state.

5. Click Netlist and Run icon to start the simulation.

The simulation takes a few seconds and then waveform window appears.
6.
7. In the CIW, note the netlisting statistics in the Circuit inventory section.
This list includes all nets, designed devices, source and loads. There are no

parasitic components. Also note down the circuit inventory section.

Measuring the Propagation Delay

134
1. In the waveform window execute Tools – Calculator.

i. The calculator window appears.

2. Place the cursor in the text box for Signal1, select the wave button and
select the input waveform from the waveform window.

3. Repeat the same for Signal2, and select the output waveform.

4. Set the Threshold value 1 and Threshold value 2 to 0.9, this directs the
calculator to calculate delay at 50% i.e. at 0.9 volts.

5. Execute OK and observe the expression created in the calculator buffer.

6. Click on Evaluate the buffer icon to perform the calculation, note

down the value returned after execution.

7. Close the calculator window.

To run the Circuit with Parasites

In this exercise, we will change the configuration to direct simulation of the

av_extracted view which contains the parasites.

1. Open the same Hierarchy Editor form, which is already set for Inverter_Test config.

2. Select the Tree View icon: this will show the design hierarchy in the tree format.

3. Click right mouse on the Inverter schematic.

135
A pull down menu appears. Select av_extracted view from the Set Instance view

menu, the View to use column now shows av_extracted view.

4. Click on the Recompute the hierarchy icon, the configuration is

now updated from schematic to av_extracted view.

5. From the Analog Design Environment window click Netlist and Run to
start the simulation again.

6. When simulation completes, note the Circuit inventory conditions, this time
the list shows all nets, designed devices, sources and parasitic devices as well.

7. Calculate the delay again and match with the previous one. Now you can
conclude how much delay is introduced by these parasites, now our main aim
should to minimize the delay due to these parasites so number of iteration takes
place for making an optimize layout.

136
 Generating Stream Data
Streaming Out the Design

1. Select File – Export – Stream from the CIW menu and Virtuoso Xstream out form
appears change the following in the form.

Click on the Options button.

2. In the StreamOut-Options form select under Layers tab

and click OK.

3. In the Virtuoso XStream Out form, click Translate button to start the
stream translator.

4. The stream file Inverter.gds is stored in the specified location.

Streaming In the Design

1. Select File – Import – Stream from the CIW menu

You need to specify the gpdk180_oa22.tf file. This is the entire technology file
that has been dumped from the design library.

2. Click on the Options button.

3. In the StreamOut-Options form select under Layers tab and
click OK.

4. In the Virtuoso XStream Out form, click Translate button to start the stream
translator.

5. From the Library Manager open the Inverter cellview from the GDS_LIB library
and notice the design.

6. Close all the windows except CIW window, which is needed for the next lab.

137
2(ii).CMOS NAND GATE

Schematic Capture

138
 Schematic Entry

Objective: To create a new cell view and build A NAND gate

Use the techniques learned in the Lab2.1 to complete the schematic of NAND
gate. This is a table of components for building the nand gate schematic.

Library name Cell Name Properties/Comments

gpdk180 Pmos Model Name = pmos1,pmos2;

gpdk180 Nmos Model Name =nmos1,nmos2;

Type the following in the ADD pin form in the exact order leaving space between
the pin names.

Pin Names Direction

Vin1 vin2 Input

vout Output

vdd vss Input

139
 Symbol Creation

Objective: To create a symbol for the NAND gate

Use the techniques learned in the Lab2.1 to complete the symbol of NAND gate

140
 Building the NAND Test Design

Objective: To build NAND_test circuit using your NAND gate

Using the component list and Properties/Comments in the table,

build the cs-amplifier_test schematic as shown below.

Library name Cellview name Properties/Comments

myDesignLib cmos_nand Symbol

Define pulse
specification as In lab
analogLib vpulse 2.1
analogLib vdd,vss,gnd vdd=1.8 ; vss= 1.8

141
 Analog Simulation with Spectre
Objective: To set up and run simulations on the NAND gate
design.
Use the techniques learned in the Lab2.1 to complete the simulation of NAND
gate, ADE window and waveform should look like below.

142
 Creating a layout view of NAND gate
Use the techniques learned in the Lab2.1 to complete the layout of NAND gate.
Complete the DRC, LVS check using the assura tool.
Extract RC parasites for back annotation and Re-simulation.

143
2(iii).CMOS XOR GATE

Schematic Capture

144
 Schematic Entry

Objective: To create a new cell view and build A XOR gate

Use the techniques learned in the Lab2.1 to complete the schematic of XOR
gate. This is a table of components for building the XOR gate schematic.

Library name Cell Name Properties/Comments

gpdk180 Pmos Model Name =

pmos1,pmos2,pmos3,pmos4;
gpdk180 Nmos Model Name
=nmos1,nmos2,nmos3,nmos4;

Type the following in the ADD pin form in the exact order leaving space between
the pin names.

Pin Names Direction

Vin1 vin2 Input

vout Output

vdd vss Input

145
 Symbol Creation
Objective: To create a symbol for the XOR gate

Use the techniques learned in the Lab2.1 to complete the symbol of XOR gate

Building the XOR Gate Test Design

Objective: To build cmos_xor_test circuit using your cmos_xor

Using the component list and Properties/Comments in the table,

build the cs-amplifier_test schematic as shown below.

146
 Library name Cellview name Properties/Comments

myDesignLib cmos_XOR Symbol

Define pulse
specification as In lab
analogLib vpulse 2.1
analogLib vdd,vss,gnd vdd=1.8 ; vss= 1.8

Analog Simulation with Spectre

Objective: To set up and run simulations on the XOR gate

design.

Use the techniques learned in the Lab2.1 to complete the simulation of XOR gate,
ADE window and waveform should look like below.

147
 Creating a layout view of XOR gate

Use the techniques learned in the Lab1 and Lab2 to complete the layout of XOR
gate. Complete the DRC, LVS check using the assura tool.
Extract RC parasites for back annotation and Re-simulation.

148
149
2(iv). CMOS FULL ADDER

Schematic Capture

150
 Schematic Entry

Objective: To create a new cell view and build A FULL ADDER

gate

Use the techniques learned in the Lab2.1 to complete the schematic of FULL
ADDER gate.

This is a table of components for building the FULL ADDER gate schematic.

Library name Cell Name Properties/Comments

gpdk180 Pmos Model Name =

pmos1,pmos2,pmos3,pmos4;
gpdk180 Nmos Model Name
=nmos1,nmos2,nmos3,nmos4;

Type the following in the ADD pin form in the exact order leaving space between
the pin names.

Pin Names Direction

Vin1 vin2 Input

Vout Output

vdd vss Input

151
Analog Simulation with Spectre

Symbol Creation

Objective: To create a symbol for the FULL ADDER

Use the techniques learned in the Lab2.1 to complete the symbol of FULL ADDER

Objective: To build full_adder_test circuit using your full_adder

Using the component list and Properties/Comments in the table,

build the Full adder_test schematic as shown below.
Library name Cellview name Properties/Comments

MyDesignLib cmos_FULL ADDER Symbol

Define pulse
specification as In lab
AnalogLib vpulse 2.1
AnalogLib vdd,vss,gnd vdd=1.8 ; vss= 1.8

152
Analog Simulation with Spectre

Objective: To set up and run simulations on the FULL ADDER design.

Use the techniques learned in the Lab2.1 to complete the simulation of FULL
ADDE, ADE window and waveform should look like below.

153
Analog Simulation with Spectre

154
Creating a layout view of FULL ADDER
Use the techniques learned in the Lab1 and Lab2 to complete the layout of FULL
ADDER.

Complete the DRC, LVS check using the assura tool.

Extract RC parasites for back annotation and Re-simulation.

155
 2(v).LATCH

Schematic capture

156
 Objective: To create a new cell view and build A LATCH

Use the techniques learned in the Lab2.1 to complete the schematic of LATCH.
This is a table of components for building the LATCH schematic.

Library name Cell Name Properties/Comments

gpdk180 Pmos Model Name =

pmos1,pmos2,pmos3,pmos4;
gpdk180 Nmos Model Name
=nmos1,nmos2,nmos3,nmos4;

Type the following in the ADD pin form in the exact order leaving space between
the pin names.

Pin Names Direction

Vin1 vin2 Input

vout Output

vdd vss Input

157
 Symbol Creation

Objective: To create a symbol for the LATCH

Use the techniques learned in the Lab2.1 to complete the symbol of LATCH

158
 Building the latch Test Design

Objective: To build latch_test circuit using your latch

Using the component list and Properties/Comments in the table,

build the latch_test schematic as shown below.

Library name Cellview name Properties/Comments

myDesignLib cmos_LATCH Symbol

Define pulse
specification as In lab
AnalogLib Vpulse 2.1
AnalogLib vdd,vss,gnd vdd=1.8 ; vss= 1.8

159
 Analog Simulation with Spectre

Objective: To set up and run simulations on the LATCH design.

Use the techniques learned in the Lab2.1 to complete the simulation of LATCH,
ADE window and waveform should look like below.

160
 Creating a layout view of LATCH

Use the techniques learned in the Lab1 and Lab2 to complete the layout of LATCH.
Complete the DRC, LVS check using the assura tool.
Extract RC parasites for back annotation and Re-simulation.