Wide Supply Range, Micropower,

Rail-to-Rail Instrumentation Amplifier

Data Sheet AD8420
FEATURES PIN CONFIGURATION
Maximum supply current: 80 μA AD8420
Minimum CMRR: 100 dB NC 1 8 VOUT

Drives heavy capacitive loads: ~700 pF +IN 2 + – 7 FB

–IN 3 – + 6 REF
Rail-to-rail output

09945-001
–VS 4 TOP VIEW 5 +VS
Input voltage range goes below ground (Not to Scale)

Gain set with 2 external resistors Figure 1.

Can achieve low gain drift at any gain
Very wide power supply range
Single supply: 2.7 V to 36 V Table 1. Instrumentation Amplifiers by Category1
Dual supply: ±2.7 V to ±18 V Zero Military Low Digital
Bandwidth (G = 100): 2.5 kHz General Purpose Drift Grade Power Gain
Input voltage noise: 55 nV/√Hz AD8221, AD8222 AD8231 AD620 AD8420 AD8250
High dc precision AD8220, AD8224 AD8290 AD621 AD8235, AD8251
Maximum offset voltage: 125 μV AD8236
Maximum offset drift: 1 μV/°C AD8226, AD8227 AD8293 AD524 AD627 AD8253
Maximum differential input voltage: ±1 V AD8228 AD8553 AD526 AD8226, AD8231
8-lead MSOP package AD8227
AD8295, AD8224 AD8556 AD624 AD623
APPLICATIONS AD8557 AD8223
Bridge amplifiers 1
See www.analog.com for the latest instrumentation amplifiers.
Pressure measurement
Medical instrumentation
Portable data acquisition
Multichannel systems

GENERAL DESCRIPTION
The AD8420 is a low cost, micropower, wide supply range, Single-supply operation, micropower current consumption, and
instrumentation amplifier with a rail-to-rail output and a novel rail-to-rail output swing make the AD8420 ideal for battery-
architecture that allows for extremely flexible design. It is optimized powered applications. Its rail-to-rail output stage maximizes
to amplify small differential voltages in the presence of large dynamic range when operating from low supply voltages. Dual-
common-mode signals. supply operation (±15 V) and low power consumption make
the AD8420 ideal for a wide variety of applications in medical
The AD8420 is based on an indirect current feedback architecture or industrial instrumentation.
that gives it an excellent input common-mode range. Unlike
conventional instrumentation amplifiers, the AD8420 can easily The AD8420 is available in an 8-lead MSOP package. Performance
amplify signals at or even slightly below ground without requiring is specified over the full temperature range of −40°C to +85°C,
dual supplies. The AD8420 has rail-to-rail output, and the output and the part is operational from −40°C to +125°C.
voltage swing is completely independent of the input common-
mode voltage.

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.
AD8420 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1  Gain Accuracy ............................................................................ 20 
Applications....................................................................................... 1  Input Voltage Range................................................................... 20 
Pin Configuration............................................................................. 1  Input Protection ......................................................................... 20 
General Description ......................................................................... 1  Layout .......................................................................................... 21 
Revision History ............................................................................... 2  Driving the Reference Pin......................................................... 21 
Specifications..................................................................................... 3  Input Bias Current Return Path ............................................... 22 
Absolute Maximum Ratings............................................................ 7  Radio Frequency Interference (RFI)........................................ 22 
Thermal Resistance ...................................................................... 7  Output Buffering ........................................................................ 23 
ESD Caution.................................................................................. 7  Applications Information .............................................................. 24 
Pin Configuration and Function Descriptions............................. 8  AD8420 in Electrocardiography (ECG).................................. 24 
Typical Performance Characteristics ............................................. 9  Classic Bridge Circuit ................................................................ 25 
Theory of Operation ...................................................................... 19  4 mA to 20 mA Single-Supply Receiver .................................. 25 
Architecture................................................................................. 19  Outline Dimensions ....................................................................... 26 
Setting the Gain .......................................................................... 19  Ordering Guide .......................................................................... 26 

REVISION HISTORY
3/12—Revision 0: Initial Version

Rev. 0 | Page 2 of 28
Data Sheet AD8420

SPECIFICATIONS
+VS = +5 V, −VS = 0 V, VREF = 0 V, V+IN = 0 V, V−IN = 0 V, TA = 25°C, G = 1 to 1000, RL = 20 kΩ, specifications referred to input, unless
otherwise noted. All Table 2 limits are valid from VS = 3 V to VS = ±5 V, unless otherwise specified.

Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR) VCM = 0 V to 2.7 V
CMRR DC to 60 Hz 100 dB
CMRR at 1 kHz 100 dB
NOISE
Voltage Noise
Spectral Density f = 1 kHz, VDIFF ≤ 100 mV 55 nV/√Hz
Peak to Peak f = 0.1 Hz to 10 Hz, VDIFF ≤ 100 mV 1.5 μV p-p
Current Noise
Spectral Density f = 1 kHz 80 fA/√Hz
Peak to Peak f = 0.1 Hz to 10 Hz 3 pA p-p
VOLTAGE OFFSET
Offset VS = 3 V to VS = 5 V 125 μV
VS = ±5 V 150 μV
Average Temperature Coefficient TA = −40°C to +85°C 1 μV/°C
Offset RTI vs. Supply (PSR) VS = 2.7 V to 5 V 86 dB
INPUTS Valid for REF and FB pair, as well
as +IN and −IN
Input Bias Current 1 TA = +25°C 20 27 nA
TA = +85°C 24 nA
TA = −40°C 30 nA
Average Temperature Coefficient TA = −40°C to +85°C 30 pA/°C
Input Offset Current TA = +25°C 1 nA
TA = +85°C 1 nA
TA = −40°C 1 nA
Average Temperature Coefficient TA = −40°C to +85°C 0.5 pA/°C
Input Impedance
Differential 130||2 MΩ||pF
Common Mode 1000||2 MΩ||pF
Differential Input Operating Voltage TA = –40°C to +85°C −1 +1 V
Input Operating Voltage (+IN, −IN, REF, or FB) TA = +25°C −VS − 0.15 +VS − 2.2 V
TA = +85°C −VS − 0.05 +VS − 1.8 V
TA = –40°C −VS − 0.2 +VS − 2.7 V
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G=1 250 kHz
G = 10 25 kHz
G = 100 2.5 kHz
G =1000 0.25 kHz
Settling Time 0.01% VS = ±5 V
G=1 −1 V to +1 V output step 3 μs
G = 10 −4.5 V to +4.5 V output step 130 μs
G = 100 −4.5 V to +4.5 V output step 1 ms
Slew Rate 1 V/μs

Rev. 0 | Page 3 of 28
AD8420 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
GAIN 2 G = 1 + (R2/R1)
Gain Range 1 1000 V/V
Gain Error
G=1 VOUT = 0.1 V to 1.1 V, VREF = 0.1 V 0.02 %
G = 10 to 1000 VOUT = 0.2 V to 4.8 V 0.05 0.1 %
Gain vs. Temperature TA = −40°C to +85°C 10 ppm/°C
OUTPUT
Output Swing VS = 5 V, RL = 10 kΩ to midsupply
VS = ±5 V, RL = 20 kΩ to ground
TA = +25°C −VS + 0.1 +VS − 0.15 V
TA = +85°C −VS + 0.1 +VS − 0.2 V
TA = −40°C −VS + 0.1 +VS − 0.15 V
Short-Circuit Current 10 mA
POWER SUPPLY
Operating Range Single-supply operation 3 2.7 36 V

Quiescent Current VS = 5 V
TA = +25°C 55 70 80 μA
TA = +85°C 95 μA
TA = −40°C 65 μA
TEMPERATURE RANGE
Specified −40 +85 °C
Operational 4 −40 +125 °C
1
The input stage uses PNP transistors; therefore, input bias current always flows out of the part.
2
For G > 1, errors from External Resistor R1 and External Resistor R2 should be considered in addition to these specifications, including error from FB pin bias current.
3
Minimum supply voltage indicated for V+IN, V−IN, and VREF = 0 V.
4
See the Typical Performance Characteristics section for operation between 85°C and 125°C.

Rev. 0 | Page 4 of 28
Data Sheet AD8420
+VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1 to 1000, RL = 20 kΩ, specifications referred to input, unless otherwise noted.

Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR) VCM = −10 V to +10 V
CMRR DC to 60 Hz 100 dB
CMRR at 1 kHz 100 dB
NOISE
Voltage Noise
Spectral Density f = 1 kHz, VDIFF ≤ 100 mV 55 nV/√Hz
Peak to Peak f = 0.1 Hz to 10 Hz, VDIFF ≤ 100 mV 1.5 μV p-p
Current Noise
Spectral Density f = 1 kHz 80 fA/√Hz
Peak to Peak f = 0.1 Hz to 10 Hz 3 pA p-p
VOLTAGE OFFSET
Offset VS = ±15 V 1 250 μV
Average Temperature Coefficient TA = −40°C to +85°C 1 μV/°C
Offset RTI vs. Supply (PSR) VS = ±15 V 100 dB
INPUTS Valid for REF and FB pair, as well
as +IN and −IN
Input Bias Current 2 TA = +25°C 20 27 nA
TA = +85°C 24 nA
TA = −40°C 30 nA
Average Temperature Coefficient TA = −40°C to +85°C 30 pA/°C
Input Offset Current TA = +25°C 1 nA
TA = +85°C 1 nA
TA = −40°C 1 nA
Average Temperature Coefficient TA = −40°C to +85°C 0.5 pA/°C
Input Impedance
Differential 130||3 MΩ||pF
Common Mode 1000||3 MΩ||pF
Differential Input Operating Voltage TA = −40°C to +85°C −1 1 V
Input Operating Voltage (+IN, −IN, REF, or FB) TA = +25°C −VS − 0.15 +VS − 2.2 V
TA = +85°C −VS − 0.05 +VS − 1.8 V
TA = −40°C −VS − 0.2 +VS − 2.7 V
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G=1 250 kHz
G = 10 25 kHz
G = 100 2.5 kHz
G =1000 0.25 kHz
Settling Time 0.01%
G=1 −1 V to +1 V output step 3 μs
G = 10 −5 V to +5 V output step 130 μs
G = 100 −5 V to +5 V output step 1 ms
Slew Rate 1 V/μs
GAIN 3 G = 1 + (R2/R1)
Gain Range 1 1000 V/V
Gain Error
G=1 VOUT = ±1 V 0.02 %
G = 10 to 1000 VOUT = ±10 V 0.05 0.1 %
Gain vs. Temperature TA = −40°C to +85°C 10 ppm/°C

Rev. 0 | Page 5 of 28
AD8420 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
OUTPUT
Output Swing
RL = 20 kΩ to Ground TA = +25°C −VS + 0.13 +VS − 0.2 V
TA = +85°C −VS + 0.15 +VS − 0.23 V
TA = –40°C −VS + 0.11 +VS − 0.16 V
Short-Circuit Current 10 mA
POWER SUPPLY
Operating Range Dual-supply operation 4 ±2.7 ±18 V
Quiescent Current VS = ±15 V
TA = +25°C 70 85 100 μA
TA = +85°C 120 μA
TA = −40°C 90 μA
TEMPERATURE RANGE
Specified −40 +85 °C
Operational 5 −40 +125 °C
1
See the Typical Performance Characteristics section for the offset voltage vs. supply.
2
The input stage uses PNP transistors; therefore, input bias current always flows out of the part.
3
For G > 1, errors from External Resistor R1 and External Resistor R2 should be considered in addition to these specifications, including error from FB pin bias current.
4
Minimum positive supply voltage indicated for V+IN, V−IN, and VREF = 0 V. With V+IN, V−IN, and VREF = −VS, minimum supply is ±1.35 V.
5
See the Typical Performance Characteristics section for operation between 85°C and 125°C.

Rev. 0 | Page 6 of 28
Data Sheet AD8420

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE
Table 4.
Parameter Rating θJA is specified for a device in free air.
Supply Voltage ±18 V Table 5.
Output Short-Circuit Current Indefinite Package θJA Unit
Maximum Voltage at −IN or +IN −VS + 40 V 8-Lead MSOP, 4-Layer JEDEC Board 135 °C/W
Minimum Voltage at −IN or +IN −VS − 0.5 V
Maximum Voltage at REF or FB +VS + 0.5 V
Minimum Voltage at REF or FB −VS − 0.5 V ESD CAUTION
Storage Temperature Range −65°C to +150°C
ESD
Human Body Model 2.5 kV
Charge Device Model 1.5 kV
Machine Model 0.1 kV

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. 0 | Page 7 of 28
AD8420 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD8420
NC 1 8 VOUT
+IN 2 + – 7 FB
–IN 3 – + 6 REF

09945-002
–VS 4 TOP VIEW 5 +VS
(Not to Scale)

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description
1 NC This pin is not connected internally. For best CMRR vs. frequency and leakage performance, connect this pin to
negative supply.
2 +IN Positive Input.
3 −IN Negative Input
4 −VS Negative Supply.
5 +VS Positive Supply.
6 REF Reference Input.
7 FB Feedback Input.
8 VOUT Output.

Rev. 0 | Page 8 of 28
Data Sheet AD8420

TYPICAL PERFORMANCE CHARACTERISTICS

T = 25°C, +VS = 5 V, RL = 20 kΩ, unless otherwise noted.

MEAN: –34.8195 700 MEAN: 4.63764

700 SD: 31.3406 SD: 1.09498

600
600

500

NUMBER OF HITS
NUMBER OF HITS

500

400
400

300 300

200 200

100 100

0 0

09945-008
09945-003
–150 –100 –50 0 50 100 150 0 2 4 6 8 10
VOS (µV) CMRR, ±15V (µV/V)

Figure 3. Typical Distribution of Input Offset Voltage Figure 6. Typical Distribution of CMRR

MEAN: 22.6643 700 MEAN: 22.706

700 SD: 0.6058 SD: 0.615728

600
600

500
NUMBER OF HITS

NUMBER OF HITS

500

400
400

300
300

200 200

100 100

0 0
09945-004

09945-006
20 21 22 23 24 25 20 21 22 23 24 25
POSITIVE BIAS CURRENT (nA) gm2 POSITIVE BIAS CURRENT (nA)

Figure 4. Typical Distribution of Input Bias Current Figure 7. Typical Distribution of REF, FB Bias Current

1200 MEAN: 0.000646761 1200 MEAN: 0.00144205

SD: 0.111551 SD: 0.112088

1000 1000
NUMBER OF HITS
NUMBER OF HITS

800 800

600 600

400 400

200 200

0 0
09945-005

09945-007

–0.9 –0.6 –0.3 0 0.3 0.6 0.9 –0.9 –0.6 –0.3 0 0.3 0.6 0.9
OFFSET CURRENT (nA) gm2 OFFSET CURRENT (nA)

Figure 5. Typical Distribution of Input Offset Current Figure 8. Typical Distribution of REF, FB Offset Current

Rev. 0 | Page 9 of 28
 AD8420 Data Sheet
3.0 0.5 15 0.6
VS = +5V VS = ±15V
G=1 G = 100
VOUT
2.5 0.4 10 0.4
VOUT IIN
IIN
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

INPUT CURRENT (mA)

INPUT CURRENT (mA)

2.0 0.3 5 0.2

1.5 0.2 0 0

1.0 0.1 –5 –0.2

0.5 0 –10 –0.4

0 –0.1 –15 –0.6

09945-309

09945-312
–5 0 5 10 15 20 25 30 35 40 –20 –15 –10 –5 0 5 10 15 20 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

Figure 9. Input Overvoltage Performance, G = 1 Figure 12. Input Overvoltage Performance, G = 100, VS = ±15 V

3 0.6 15
VS = ±15V
G=1 VOUT –1.0V, +12.3V 0.0V, +12.8V +1.0V, +12.3V

INPUT COMMON-MODE VOLTAGE (V)

10
2 0.4

IIN 5
OUTPUT VOLTAGE (V)

INPUT CURRENT (mA)

1 0.2

0
0 0
–5

–1 –0.2
–10

–2 –0.4 –1.0V, –14.6V +1.0V, –14.6V

–15
0.0V, –15.1V

–3 –0.6 –20
09945-310

09945-313
–20 –15 –10 –5 0 5 10 15 20 25 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 1.2
INPUT VOLTAGE (V) OUTPUT VOLTAGE (V)

Figure 10. Input Overvoltage Performance, G = 1, VS = ±15 V Figure 13. Input Common-Mode Voltage vs. Output Voltage,
G = 1, VS = ±15 V

6 0.5 3.0
VS = 5V
G = 100
VOUT
INPUT COMMON-MODE VOLTAGE (V)

2.5 +4mV, +2.8V

5 0.4
+1.0V, +2.3V
IIN
2.0
OUTPUT VOLTAGE (V)

INPUT CURRENT (mA)

4 0.3

1.5
3 0.2
1.0

2 0.1
0.5 +1.0V, +0.4V
+4mV, –0.1V
1 0
0

0 –0.1 –0.5
09945-314
09945-311

–5 0 5 10 15 20 25 30 35 40 –0.2 0 0.2 0.4 0.6 0.8 1.0 1.2

INPUT VOLTAGE (V) OUTPUT VOLTAGE (V)

Figure 11. Input Overvoltage Performance, G = 100 Figure 14. Input Common-Mode Voltage vs. Output Voltage, G = 1, VS = 5 V

Rev. 0 | Page 10 of 28
Data Sheet AD8420
3.5 3.5
VREF = 2.5V
RL = 10kΩ TO MIDSUPPLY
3.0 +2.5V, +2.8V 3.0
INPUT COMMON-MODE VOLTAGE (V)

INPUT COMMON-MODE VOLTAGE (V)

+44mV, +2.8V +4.8V, +2.78V
2.5 2.5
+3.03V, +2.46V
+1.5V, +2.3V
2.0 2.0

1.5 1.5

1.0 1.0

0.5 +1.5V, +0.4V 0.5

+3.03V, +0.16V
0 0 +44mV, –0.1V +4.8V, –80mV
+2.5V, –0.1V
–0.5 –0.5

09945-315

09945-318
1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)

Figure 15. Input Common-Mode Voltage vs. Output Voltage, Figure 18. Input Common-Mode Voltage vs. Output Voltage,
G = 1, VS = 5 V, VREF = 2.5 V G = 100, VS = 5 V

0.6 3.5
+4mV, +0.5V
0.5 3.0
INPUT COMMON-MODE VOLTAGE (V)

INPUT COMMON-MODE VOLTAGE (V)

+86mV, +2.79V +2.5V, +2.8V +4.8V, +2.79V
0.4 2.5

0.3 2.0

0.2 +0.6V, +0.2V 1.5

0.1 1.0

0 0.5

–0.1 0 +86mV, –90mV +2.5V, –0.1V +4.8V, –90mV

+4mV, –0.1V
–0.2 –0.5
09945-316

09945-319
–0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)

Figure 16. Input Common-Mode Voltage vs. Output Voltage, G = 1, VS = 2.7 V Figure 19. Input Common-Mode Voltage vs. Output Voltage,
G = 100, VS = 5 V, VREF = 2.5 V

20 0.6
+29mV, +0.5V +2.53V, +0.49V
15 –14.9V, +12.7V +14.8V, +12.7V 0.5
INPUT COMMON-MODE VOLTAGE (V)

INPUT COMMON-MODE VOLTAGE (V)

0.0V, +12.8V
10 0.4

5 0.3

0 0.2

–5 0.1

–10 0

0.0V, –15.1V
–15 –0.1
–14.9V, –15.0V +14.8V, –15.0V +29mV, –0.1V +2.53V, –90mV
–20 –0.2
09945-317

09945-320

–20 –15 –10 –5 0 5 10 15 20 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)

Figure 17. Input Common-Mode Voltage vs. Output Voltage, Figure 20. Input Common-Mode Voltage vs. Output Voltage,
G = 100, VS = ±15 V G = 100, VS = 2.7 V

Rev. 0 | Page 11 of 28
AD8420 Data Sheet
40 120
VS = ±15V

35
100
INPUT BIAS CURRENT (nA)

30

POSITIVE PSRR (dB)

–0.2V 80
+2.7V
25
GAIN = 1000
60
20
GAIN = 100
40
15
GAIN = 10
BANDWIDTH
20 LIMIT
10
IBIAS (+IN)
IBIAS (–IN) GAIN = 1
5 0

09945-323
09945-019
–2.0 0 0.5 1.0 1.5 2.0 2.5 3.0 0.1 1 10 100 1k 10k 100k
COMMON-MODE VOLTAGE (V) FREQUENCY (Hz)

Figure 21. Input Bias Current vs. Common-Mode Voltage Figure 24. Positive PSRR vs. Frequency, RTI, VS = ±15 V

400 120
VS = ±15V
SPECIFIED
300 PERFORMANCE RANGE GAIN = 1000
IBIAS (+IN) 100
GAIN = 100
200
INPUT BIAS CURRENT (nA)

NEGATIVE PSRR (dB)

80
100

0 60 BANDWIDTH
LIMIT
–100
40 GAIN = 10
–200
GAIN = 1
IBIAS (–IN)
20
–300

–400 0

09945-324
09945-020

–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 0.1 1 10 100 1k 10k 100k
DIFFERENTIAL INPUT VOLTAGE (V) FREQUENCY (Hz)

Figure 22. Input Bias Current vs. Differential Input Voltage, VS = ±15 Figure 25. Negative PSRR vs. Frequency, RTI, VS = ±15 V

100 70
VS = ±15V
GAIN = 1000
60

80 50
GAIN = 100
40
GAIN = 1000
60 30
PSRR (dB)

GAIN (dB)

GAIN = 10
20
GAIN = 100
40 10
GAIN = 1
GAIN = 10 0
BANDWIDTH
20 LIMIT –10

–20
GAIN = 1
0 –30
09945-500

09945-023

0.1 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k 1M

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 23. PSRR vs. Frequency on 5 V Supply Figure 26. Gain vs. Frequency

Rev. 0 | Page 12 of 28
Data Sheet AD8420
70 120
VS = 2.7V
GAIN = 1000
60
100
50
GAIN = 100
40
80
30

CMRR (dB)
GAIN (dB)

GAIN = 10
20 60

10
GAIN = 1 40
0

–10
20
–20 VS = ±15V
VCM = ±10V
–30 0

09945-329
09945-024
1 10 100 1k 10k 100k 1M 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
FREQUENCY (Hz) DIFFERENTIAL INPUT VOLTAGE (V)

Figure 27. Gain vs. Frequency, 2.7 V Single Supply Figure 30. CMRR vs. Differential Input Voltage

140 120
VS = ±15V BANDWIDTH GAIN = 1000 VS = 5V
LIMIT 110
120
100

100

SUPPLY CURRENT (µA)

90
GAIN = 100
80
CMRR (dB)

80
70
60 GAIN = 10
60

40 GAIN = 1 50

40
20
30

0 20
09945-327

09945-027
0.1 1 10 100 1k 10k 100k –40 –25 –10 5 20 35 50 65 80 95 110 125
FREQUENCY (Hz) TEMPERATURE (°C)

Figure 28. CMRR vs. Frequency, RTI, VS = ±15 V Figure 31. Supply Current vs. Temperature, VS = +5 V

140 30 250
VS = ±15V

120
25 –IN BIAS CURRENT 200
GAIN = 1000

OFFSET CURRENT (pA)

100
BIAS CURRENT (nA)

GAIN = 100 20 150

+IN BIAS CURRENT
CMRR (dB)

80
15 100
60
GAIN = 10
GAIN = 1 10 50
40

5 OFFSET CURRENT 0
20

0 0 –50
09945-328

09945-331

0.1 1 10 100 1k 10k 100k –40 –25 –10 5 20 35 50 65 80 95 110 125

FREQUENCY (Hz) TEMPERATURE (°C)

Figure 29. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance, VS = ±15 V Figure 32. Input Bias Current and Input Offset Current vs. Temperature

Rev. 0 | Page 13 of 28
 AD8420 Data Sheet
30 200 400
NORMALIZED TO 25°C

300
25 –IN BIAS CURRENT 150

200

OFFSET VOLTAGE (µV)

OFFSET CURRENT (pA)
BIAS CURRENT (nA)

20 100
100
+IN BIAS CURRENT

15 50 0

–100
10 0
OFFSET CURRENT –200
5 –50
–300

0 –100 –400

09945-332

09945-031
–40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 33. FB, REF Bias Current and FB, REF Offset Current vs. Temperature Figure 36. Offset Drift

1000 5
VIN = ±1V REPRESENTATIVE DATA VS = ±15V
NORMALIZED AT 25°C
800 VS = ±15V 4

600
3
PART A
400
GAIN ERROR (µV/V)

CMRR (µV/V) 2
200
1
0 PART A: 0.024ppm/°C
PART B 0
–200
–1
–400

–600 –2
PART B: 0.038ppm/°C
–800 –3
REPRESENTATIVE DATA
NORMALIZED TO 25ºC
–1000 –4
09945-333

09945-032
–40 –25 –10 5 20 35 50 65 80 –40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 34. Gain Error vs. Temperature, G = 1, VIN = ±1 V, VS = ±15 V Figure 37. CMRR vs. Temperature, G = 1, VS = ±15 V

1000 +VS
VIN = ±0.1V RL = 20kΩ
800 VS = ±15V
–0.1
REFERRED TO SUPPLY VOLTAGES

600
OUTPUT VOLTAGE SWING (V)

–0.2
400 –40°C
GAIN ERROR (µV/V)

PART A +25°C
–0.3
200 +85°C
+125°C
0

–200
+0.3
–400 PART B
+0.2
–600
+0.1
–800
REPRESENTATIVE DATA
NORMALIZED TO 25ºC
–1000 –VS
09945-334

09945-035

–40 –25 –10 5 20 35 50 65 80 2 4 6 8 10 12 16 18 20

TEMPERATURE (°C) SUPPLY VOLTAGE (±VS)

Figure 35. Gain Error vs. Temperature, G = 1, VIN = ±0.1 V, VS = ±15 V Figure 38. Output Voltage Swing vs. Supply Voltage, RL = 20 kΩ

Rev. 0 | Page 14 of 28
Data Sheet AD8420
+VS +VS

–0.2 –0.2
REFERRED TO SUPPLY VOLTAGES

REFERRED TO SUPPLY VOLTAGES

–0.4 –0.4
OUTPUT VOLTAGE SWING (V)

OUTPUT VOLTAGE SWING (V)

–0.6 –0.6

–0.8 –0.8 –40°C

–40°C
+25°C
+25°C
+85°C
+85°C
+125°C
+0.8 +125°C
+0.8

+0.6 +0.6
VS = 5V
+0.4 VREF = 2.5V +0.4

+0.2 +0.2

–VS –VS

09945-340
09945-338
1k 10k 100k 1M 0.1 1
LOAD RESISTANCE (Ω) OUTPUT CURRENT (mA)

Figure 39. Output Voltage Swing vs. Load Resistance, VS = 5 V Figure 42. Output Voltage Swing vs. Output Current, VS = ±15

+VS 2k

–0.2
1k
REFERRED TO SUPPLY VOLTAGES

–0.4
OUTPUT VOLTAGE SWING (V)

–0.6

–0.8 –40°C NOISE (nV/ Hz)

+25°C
+85°C
+0.8 +125°C
100 GAIN = 1
+0.6 GAIN = 10
VS = 5V
+0.4 VREF = 2.5V
+0.2
GAIN = 100
–VS 20
09945-501

09945-042
0.1 1 0.1 1 10 100 1k 10k 100k
OUTPUT CURRENT (mA) FREQUENCY (Hz)

Figure 40. Output Voltage Swing vs. Load Resistance, VS = 5 V Figure 43. Voltage Noise Spectral Density vs. Frequency, RTI

15

10
OUTPUT VOLTAGE SWING (V)

–5

–40°C
–10 +25°C
09945-043

+85°C
0.4µV/DIV 1s/DIV
+125°C
–15
09945-339

1k 10k 100k 1M
LOAD RESISTANCE (Ω)

Figure 41. Output Voltage Swing vs. Load Resistance, VS = ±15 V Figure 44. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1

Rev. 0 | Page 15 of 28
AD8420 Data Sheet
1k
VS = ±5V
NOISE (fA/ Hz)

1V/DIV
1.78µs TO 0.1%
100 3.31µs TO 0.01%

0.02%/DIV

09945-149
20µs/DIV
10

09945-348
1 10 100 1k 10k 100k
FREQUENCY (Hz)

Figure 45. Current Noise Spectral Density vs. Frequency Figure 48. Large Signal Pulse Response and Settling Time, G = 1

VS = ±5V

4.5V/DIV
67µs TO 0.1%
138µs TO 0.01%

0.02%/DIV

09945-150
09945-147

1.5pA/DIV 1s/DIV 200µs/DIV

Figure 46. 0.1 Hz to 10 Hz Current Noise Figure 49. Large Signal Pulse Response and Settling Time, G = 10

30
VS = ±15V, G = 15V/V VS = ±5V
27

24
OUTPUT VOLTAGE (V p-p)

21

18 4.5V/DIV
600ms TO 0.1%
15 1.04ms TO 0.01%

12
0.02%/DIV
9

6
09945-151

3 VS = +5V, G = 5V/V
20ms/DIV
0
09945-148

1 10 100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 47. Large Signal Frequency Response Figure 50. Large Signal Pulse Response and Settling Time, G = 100

Rev. 0 | Page 16 of 28
Data Sheet AD8420

09945-051

09945-054
20mV/DIV 4µs/DIV 20mV/DIV 2ms/DIV

Figure 51. Small Signal Pulse Response, G = 1, RL = 20 kΩ, CL = 100 pF Figure 54. Small Signal Pulse Response, G = 1000, RL = 20 kΩ, CL = 100 pF

NO LOAD
220pF
470pF
780pF
09945-052

09945-055
20mV/DIV 20µs/DIV 20mV/DIV 5µs/DIV

Figure 52. Small Signal Pulse Response, G = 10, RL = 20 kΩ, CL = 100 pF Figure 55. Small Signal Response with Various Capacitive Loads,
G = 1, RL = ∞

90

85

80
SUPPLY CURRENT (µA)

75

70

65

60
09945-053

55
20mV/DIV 200µs/DIV
50
09945-057

0 5 10 15 20 25 30 35 40
SUPPLY VOLTAGE (V)

Figure 53. Small Signal Pulse Response, G = 100, RL = 20 kΩ, CL = 100 pF Figure 56. Supply Current vs. Supply Voltage

Rev. 0 | Page 17 of 28
 AD8420 Data Sheet
90
TESTED WITH DUAL SUPPLIES
CENTERED AT 0V
–20

–40
OFFSET VOLTAGE (µV)

–60

–80

–100

–120

–140

–160

–180

–200

09945-502
0 4 8 12 16 20 24 28 32 36
SUPPLY VOLTAGE (V)
Figure 57. Offset Voltage vs. Supply Voltage

Rev. 0 | Page 18 of 28
Data Sheet AD8420

THEORY OF OPERATION
+VS
AD8420 –

A VOUT
+
I3 –VS
Vb +VS R2
–
ESD
+IN PROTECTION FB

gm1 gm2 –VS

R1
+VS
I1 I2 +
ESD
–IN PROTECTION REF

09945-058
–VS

Figure 58. Simplified Schematic

ARCHITECTURE Table 7. Suggested Resistors for Various Gains, 1% Resistors

The AD8420 is based on an indirect current feedback topology R1 (kΩ) R2 (kΩ) Gain
consisting of three amplifiers: two matched transconductance None Short 1.00
amplifiers that convert voltage to current and one integrator 49.9 49.9 2.00
amplifier that converts current to voltage. 20 80.6 5.03
For the AD8420, assume that all initial voltages and currents are 10 90.9 10.09
zero until a positive differential voltage is applied between the 5 95.3 20.06
inputs, +IN and −IN. Transconductance Amplifier gm1 converts this 2 97.6 49.8
input voltage into a current, I1. Because the voltage across gm2 is 1 100 101
initially zero, I2 is zero and I3 equals I1. 1 200 201
1 499 500
I3 is integrated to the output, making the output voltage, VOUT,
1 1000 1001
increase. This voltage continues to increase until the same differ-
ential input voltage across the inputs of gm1 is replicated across While the ratio of R2 to R1 sets the gain, the designer determines
the inputs of gm2, generating a current (I2) equal to I1. This reduces the absolute value of the resistors. Larger values reduce power
the Difference Current I3 to zero so that the output remains at a consumption and output loading; smaller values limit the FB input
stable voltage. The gain in the configuration shown in Figure 58 is bias current and offset current error. For best output swing and
set by R2 and R1. distortion performance, keep (R1 + R2) || RL ≥ 20 kΩ.
In traditional instrumentation amplifiers, the input common- A method that allows large value feedback resistors while limiting
mode voltage can limit the available output swing, typically FB bias current error is to place a resistor of value R1 || R2 in
depicted in a hexagon plot. Because the AD8420 converts the series with the REF terminal, as shown in Figure 59. At higher
input differential signals to current, this limit does not apply. This gains, this resistor can simply be the same value as R1.
is particularly important when amplifying a signal with a common-
+IN
mode voltage near one of the supply rails.
IB+ VOUT
To improve robustness and ease of use, the AD8420 includes AD8420
IB– FB
overvoltage protection on its inputs. This protection scheme
–IN REF IBF
allows wide differential input voltages without damaging the part.
IBR
SETTING THE GAIN +
R1||R2
The transfer function of the AD8420 is – R1 R2
R2
G=1+
R1
09945-059

VOUT = G(V+IN − V−IN) + VREF VREF

where:
Figure 59. Cancelling Out Error from FB Input Bias Current
R2
G =1+
R1

Rev. 0 | Page 19 of 28
AD8420 Data Sheet
GAIN ACCURACY INPUT PROTECTION
Unlike most instrumentation amplifiers, the relative match of The current into the AD8420 inputs is limited internally. This
the two gain setting resistors determines the gain accuracy of ensures that the diodes that limit the differential voltage seen by
the AD8420 rather than a single resistor. For example, if two the internal amplifier do not draw excessive current when they
resistors have exactly the same absolute error, there is no error turn on. The part can handle large differential input voltages,
in gain. Conversely, two 1% resistors can cause approximately 2% regardless of the amount of gain applied, without damage. As a
maximum gain error at high gains. Temperature coefficient result, the AD8420 inputs are protected from voltages beyond
mismatch of the gain setting resistors increases the gain drift the positive rail. If voltages beyond the negative rail are expected,
of the instrumentation amplifier circuit. Because these external external protection must be used.
resistors do not have to match any on-chip resistors, resistors Keep all of the AD8420 terminals within the voltage range specified
with good TC tracking can achieve excellent gain drift. in the Absolute Maximum Ratings section. All terminals of the
When the differential voltage at the inputs approaches the AD8420 are protected against ESD.
differential input limit, the diodes start to conduct, limiting Input Voltages Beyond the Rails
the voltage seen by the inputs. This can look like increased gain For applications that require protection beyond the negative rail,
error at large differential inputs. Performance of the AD8420 is one option is to use an external resistor in series with each input
specified for ±1 V differential from −40°C to +85°C. However, to limit current during overload conditions. In this case, size the
at higher temperatures, the reduced forward voltage of the diodes resistors to limit the current into the AD8420 to 6 mA.
limits the differential input to a smaller voltage. Figure 60 tracks RPROTECT ≥ (Negative Supply − VIN)/6 mA
1% error across the operating temperature range to show the
Although the AD8420 inputs must still be kept within the −VS +
effect of temperature on the input limit.
40 V limitation, the I × R drop across the protection resistor
2.0
NEGATIVE VOLTAGE VS = ±15V increases the protection on the positive side to approximately
1.8
MAXIMUM INPUT VOLTAGE (1% ERROR)

(40 V + Negative Supply) + 300 μA × RPROTECT

1.6
POSITIVE VOLTAGE An alternate protection method is to place diodes at the AD8420
1.4
inputs to limit voltage and resistors in series with the inputs to
1.2 limit the current into these diodes. To keep input bias current at
1.0 a minimum for normal operation, use low leakage diode clamps,
0.8 such as the BAV199. The AD8420 also combines well with TVS
diodes, such as the PTVSxS1UR.
0.6
+VS
0.4 +VS +VS
RPROTECT RPROTECT
0.2 + + I
VIN+ VIN+
– – –VS
0 AD8420 AD8420
09945-503

–40 –25 –10 5 20 35 50 65 80 95 110 125 +VS

TEMPERATURE (°C) RPROTECT RPROTECT

Figure 60. Differential Input Limit vs. Temperature + +

VIN– –VS VIN– –VS
– – –VS
INPUT VOLTAGE RANGE
09945-160
SIMPLE METHOD ALTERNATE METHOD
The allowed input range of the AD8420 is much simpler than
Figure 61. Protection for Voltages Beyond the Rails
traditional architectures. For the transfer function of the AD8420
to be valid, the input voltage should follow two rules: Large Differential Input Voltage
• Keep the differential input voltage within ±1 V. The AD8420 is able to handle large differential input voltage
• Keep the voltage on the +IN, −IN, REF, and FB pins in the without damage to the part. Refer to Figure 9, Figure 10,
specified input voltage range. Figure 11, and Figure 12 for overvoltage performance. The
AD8420 differential voltage is internally limited with diodes to
Because the output swing is completely independent of the ±1 V. If this limit is exceeded, the diodes start to conduct and
input common-mode voltage, there are no hexagonal figures draw current, as shown in Figure 22. This current is limited
or complicated formulas to follow, and no limitation for the internally to a value that is safe for the AD8420, but if the input
output swing the amplifier has for input signals with changing current cannot be tolerated in the system, place resistors in
common mode. series with each input with the following value:

1⎛ V −1V ⎞
RPROTECT ≥ ⎜ DIFF ⎟
⎜
2⎝ I MAX ⎟
⎠

Rev. 0 | Page 20 of 28
Data Sheet AD8420
LAYOUT Reference
Common-Mode Rejection Ratio over Frequency The output voltage of the AD8420 is developed with respect to
Poor layout can cause some of the common-mode signal to be the potential on the reference terminal. Take care to tie REF to the
converted to a differential signal before reaching the in-amp. This appropriate local ground. The differential voltage at the inputs is
conversion can occur when the path to the positive input pin reproduced between the REF and FB pins; therefore, it is important
has a different frequency response than the path to the negative to set VREF so that the voltage at FB does not exceed the input range.
input pin. For best CMRR vs. frequency performance, the input DRIVING THE REFERENCE PIN
source impedance and capacitance of each path should be closely
Traditional instrumentation amplifier architectures require the
matched. This includes connecting Pin 1 to −VS, which matches the
reference pin to be driven with a low impedance source. In these
parasitic capacitance and the leakage between the inputs and
architectures, impedance at the reference pin degrades both CMRR
adjacent pins. Place additional source resistance in the input
and gain accuracy. With the AD8420 architecture, resistance at
path (for example, for input protection) close to the in-amp inputs
the reference pin has no effect on CMRR.
to minimize their interaction with the parasitic capacitance from
the printed circuit board (PCB) traces. +IN

VOUT
Power Supplies
AD8420
Use a stable dc voltage to power the instrumentation amplifier. FB

Noise on the supply pins can adversely affect performance. For –IN REF

more information, see the PSRR performance curves in Figure 24 R1 R2

RREF
and Figure 25. R2 + RREF
G=1+
R1

09945-062
VREF
Place a 0.1 μF capacitor as close as possible to each supply pin.
As shown in Figure 62, a 10 μF tantalum capacitor can be used
Figure 63. Calculating Gain with Reference Resistance
farther away from the part. This capacitor, which is intended to
be effective at low frequencies, can usually be shared by other Resistance at the reference pin does affect the gain of the AD8420,
precision integrated circuits. Keep the traces between these but if this resistance is constant, the gain setting resistors can be
integrated circuits short to minimize interaction of the trace adjusted to compensate. For example, the AD8420 can be driven
parasitic inductance with the shared capacitor. with a voltage divider as shown in Figure 64.
+VS
+IN

VOUT
0.1µF 10µF AD8420
FB
+IN –IN REF
VOUT VS R1 R2
AD8420 R3
R2 + R3||R4
R1 R2 G=1+

09945-063
–IN R1 R4

Figure 64. Using Resistor Divider to Set Reference Voltage

0.1µF 10µF
09945-060

–VS

Figure 62. Supply Decoupling, REF, and Output Referred to Local Ground

Rev. 0 | Page 21 of 28
AD8420 Data Sheet
INCORRECT CORRECT
+VS +VS

VOUT VOUT
AD8420 AD8420

–VS –VS

TRANSFORMER TRANSFORMER

+VS +VS

VOUT VOUT
AD8420 AD8420

10MΩ

–VS –VS

THERMOCOUPLE THERMOCOUPLE

+VS +VS

C C

VOUT 1 VOUT
fHIGH-PASS = 2πRC R
AD8420 AD8420
C C

09945-061
–VS –VS

CAPACITIVELY COUPLED CAPACITIVELY COUPLED

Figure 65. Creating an IBIAS Path

+VS
INPUT BIAS CURRENT RETURN PATH
0.1µF 10µF
The input bias current of the AD8420 must have a return path R CC
20kΩ 330pF
to ground. When the source, such as a thermocouple, cannot 1% 5%
provide a return current path, create one, as shown in Figure 65. +IN
VOUT
R CD
RADIO FREQUENCY INTERFERENCE (RFI) 20kΩ 3300pF AD8420
1%
–IN
All instrumentation amplifiers can rectify high frequency out-of- CC
R1 R2
330pF
band signals. Once rectified, these signals appear as dc offset errors 5%
at the output. High frequency signals can be filtered with a low-pass 0.1µF 10µF
09945-064

RC network placed at the input of the instrumentation amplifier, as

–VS
shown in Figure 66. The filter limits the input signal bandwidth
according to the following relationship: Figure 66. Suggested RFI Suppression Filter

1 CD affects the differential signal and CC affects the common-mode

FilterFrequency DIFF = signal. Values of R and CC are chosen to minimize out of band
2πR(2C D + C C )
RFI at the expense of reduced signal bandwidth. Mismatch
1 between the R × CC at the positive input and the R × CC at the
FilterFrequency CM =
2πRC C negative input degrades the CMRR of the AD8420. By using a
value of CD that is at least one magnitude larger than CC, the
where CD ≥ 10 CC.
effect of the mismatch is reduced and performance is improved.

Rev. 0 | Page 22 of 28
Data Sheet AD8420
OUTPUT BUFFERING Because the ADA4692-2 is a dual op amp, another op amp is
The AD8420 is designed to drive loads of 20 kΩ or greater but now free for use as an active filter stage or to buffer another
can deliver up to 10 mA to heavier loads at lower output voltage AD8420 output on the same PCB. Figure 68 shows another
swings (see Figure 42). If more output current is required, buffer suggestion for how to use this second op amp. In this circuit,
the AD8420 output with a precision op amp. Figure 67 shows the voltage from the wiper of a potentiometer is buffered by the
the recommended configuration using the ADA4692-2 as a single ADA4692-2, allowing a variable level shift of the output. Resistors
supply. This low power op amp can swing its output from 1 V to above and below the potentiometer reduce the total range of the
4 V on a single 5 V supply while sourcing or sinking more than level shift but increase the precision. If the potentiometer were
30 mA of current. When using this configuration, the load seen connected directly to the REF pin of the AD8420, gain error would
by the AD8420 is approximately R1 + R2. be introduced from the variable resistance. The potentiometer can
be tuned in hardware or software, depending on the type of
+5V
potentiometer chosen. For a list of digital potentiometers made
+VS 0.1µF
by Analog Devices, Inc., visit www.analog.com/digipots/.
+VS 0.1µF +5V

0.1µF
VIN AD8420
ADA4692-2 VOUT
R1 R2 0.1µF
–VS VREF
VIN AD8420 VOUT

–VS R
09945-065

CW
R1 R2 W
Figure 67. Output Buffering REF
ADA4692-2 CCW
R

SUGGESTION FOR SECOND

09945-066
AMPLIFIER: VARIABLE
LEVEL SHIFT WITHOUT
AFFECTING GAIN

Figure 68. Variable Level Shift

Rev. 0 | Page 23 of 28
AD8420 Data Sheet

APPLICATIONS INFORMATION
AD8420 IN ELECTROCARDIOGRAPHY (ECG) architecture, the offset can be accounted for in the input stage
by unbalancing the transconductance amplifier at the REF and
A high-pass filter is commonly used in ECG signal conditioning FB pins. In the steady state, the offset at the input is not gained
circuitry to remove electrode offset and motion artifacts. To avoid to the output, and higher frequency signals can be gained and
degrading the input impedance and CMRR of the system, this passed through. Using the AD8420 in this way, the offset tolerance
filtering is typically implemented after the instrumentation is nearly the differential input range of the part (±1 V).
amplifier, which limits the gain that can be applied with the
instrumentation amplifier. Figure 69 shows an ECG front end that applies a gain of 100 to
the signal while rejecting dc and high frequencies. This circuit
With a 3-op-amp instrumentation amplifier, gain is applied in the combines the AD8420 with the AD8657, which is a low power,
first stage. Because of this, the electrode offset is gained and then low cost, dual, precision CMOS op amp.
must be removed afterward with a high-pass filter. In the AD8420

INSTRUMENTATION THREE-POLE LPF,

AMPLIFIER BESSEL RESPONSE
G = +100 FC = 50Hz
200pF
+5V
402kΩ
A B 100kΩ
110kΩ 200kΩ 0.015μF
2000pF AD8420
FB 100kΩ
500kΩ 0.022μF 200kΩ
100kΩ +5V
REF 1kΩ
200pF –5V
3.3μF
8200pF
C
10MΩ
+5V
–5V

AD8657-1 AD8657-2

09945-072
–5V INTEGRATOR PROVIDES
HIGH-PASS POLE AT 0.5Hz

Figure 69. AD8420 in an ECG Front End

Rev. 0 | Page 24 of 28
Data Sheet AD8420
CLASSIC BRIDGE CIRCUIT 4 mA TO 20 mA SINGLE-SUPPLY RECEIVER
Figure 70 shows the AD8420 configured to amplify the signal from The 80 μA maximum supply current, input range that goes
a classic resistive bridge. This circuit works in dual-supply mode or below ground, and low drift characteristics make the AD8420 a
single-supply mode. Typically, the same voltage that powers the very good candidate for use in a 4 mA to 20 mA loop. Figure 71
instrumentation amplifier excites the bridge. Connecting the shows how a signal from a 4 mA to 20 mA transducer can be
bottom of the bridge to the negative supply of the instrumentation interfaced to the AD8420. The signal from a 4 mA to 20 mA
amplifier sets up an input common-mode voltage that is located transducer is single-ended, which initially suggests the need for
midway between the supply voltages. The voltage on the REF pin a simple shunt resistor to ground to convert the current to a voltage.
can be varied to suit the application. For example, the REF pin However, any line resistance in the return path (to the transducer)
is tied to the VREF pin of an analog-to-digital converter (ADC) adds a current-dependent offset error; therefore, the current must
whose input range is (VREF ± VIN). With an available output swing be sensed differentially.
on the AD8420 of (−VS + 100 mV) to (+VS − 150 mV), the In this example, a 5 Ω shunt resistor generates a differential voltage
maximum programmable gain is simply this output range divided at the inputs of the AD8420 between 20 mV (for 4 mA in) and
by the input range. 100 mV (for 20 mA in) with a very low common-mode value.
+VS
With the gain resistors shown, the AD8420 amplifies the 100 mV
0.1µF input voltage by a factor of 40 to 4.0 V.

VDIFF AD8420 VOUT

VREF
0.1µF
09945-069

–VS

Figure 70. Classic Bridge Circuit

5V

0.1µF

4mA TO 20mA LINE 4mA TO 20mA 5Ω AD8420

AD627 0.8V TO 4.0V
TRANSDUCER IMPEDANCE G = 40
+
+ –
POWER R2 = 97.6kΩ R1 R2
09945-073

SUPPLY R1 = 2.49kΩ

Figure 71. 4 mA to 20 mA Receiver Circuit

Rev. 0 | Page 25 of 28
AD8420 Data Sheet

OUTLINE DIMENSIONS
3.20
3.00
2.80

8 5 5.15
3.20 4.90
3.00 4.65
2.80 1
4

PIN 1
IDENTIFIER

0.65 BSC

0.95 15° MAX

0.85 1.10 MAX
0.75
0.80
0.15 6° 0.23
0.40 0.55
0.05 0° 0.09 0.40
COPLANARITY 0.25

10-07-2009-B
0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 72. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)
Dimensions shown in millimeters

ORDERING GUIDE
Package
Model 1 Temperature Range Package Description Option Branding
AD8420ARMZ −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP], Tube RM-8 Y3Y
AD8420ARMZ-R7 −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP], 7-Inch Tape and Reel RM-8 Y3Y
AD8420ARMZ-RL −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP], 13-Inch Tape and Reel RM-8 Y3Y
1
Z = RoHS Compliant Part.

Rev. 0 | Page 26 of 28
Data Sheet AD8420

NOTES

Rev. 0 | Page 27 of 28
AD8420 Data Sheet

NOTES

©2012 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D09945-0-3/12(0)

Rev. 0 | Page 28 of 28