Meena et al.

Nanoscale Research Letters 2014, 9:526

http://www.nanoscalereslett.com/content/9/1/526

NANO REVIEW Open Access

Overview of emerging nonvolatile memory

technologies
Jagan Singh Meena, Simon Min Sze, Umesh Chand and Tseung-Yuen Tseng*

Abstract
Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor
(FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling
limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in
consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks
(SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data
centers. The integration limit of Flash memories is approaching, and many new types of memory to replace
conventional Flash memories have been proposed. Emerging memory technologies promise new memories to
store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including
digital cameras, cell phones and portable music players. They are being investigated and lead to the future as
potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies
such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM),
ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory
(RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access
memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for
future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and
plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity
in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate
commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review
is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures
based on an investigation of recent progress in advanced Flash memory devices.
Keywords: Emerging nonvolatile memory technologies; Magnetic storage; Market memory technologies;
Memristors; Phase change memories; Random-access storage; Flash memory technologies; Three-dimensional
memory; Transparent memory, Unified memory

Review since a 64-bit bipolar RAM chip to be used in the cache

Background memory of an IBM computer was reported in 1969 [2].
General overview Semiconductor memory has always been an indispensable
The idea of using a floating gate (FG) device to obtain a component and backbone of modern electronic systems.
nonvolatile memory device was suggested for the first All familiar computing platforms ranging from handheld
time in 1967 by Kahng D and Sze SM at Bell Labs [1]. devices to large supercomputers use storage systems for
This was also the first time that the possibility of nonvol- storing data temporarily or permanently [3]. Beginning
atile MOS memory device was recognized. From that day, with punch card which stores a few bytes of data, storage
semiconductor memory has made tremendous contribu- systems have reached to multiterabytes of capacities in
tions to the revolutionary growth of digital electronics comparatively less space and power consumption. Regard-
ing application aspects, the speed of storage systems needs
* Correspondence: [email protected] to be as fast as possible [4]. Since Flash memory has be-
Department of Electronics Engineering and Institute of Electronics, National come a common component of solid-state disks (SSDs),
Chiao Tung University, Hsinchu 30010, Taiwan

© 2014 Meena et al.; licensee Springer. This is an Open Access article distributed under the terms of the Creative Commons
Attribution License (http://creativecommons.org/licenses/by/4.0), which permits unrestricted use, distribution, and reproduction
in any medium, provided the original work is properly credited.
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the falling prices and increased densities have made it high density for large data storage applications [8].
more cost-effective for many other applications [5]. Mem- Since the inception of Flash memory, there has been an
ory devices and most SSDs that use Flash memory are exponential growth in its market driven primarily by
likely to serve very different markets and purposes. Each cell phones and other types of consumer electronic
has a number of different attributes which are opti- equipment. While, today, integration of a silicon chip is
mized and adjusted to best meet the needs of particular not economical, toys, cards, labels, badges, value paper,
users. Because of natural inherent limitations, the long- and medical disposables could be imagined to be
established memory devices have been shorted out equipped with flexible electronics and memory. With
according to their inventions to match with portable growing demands for high-density digital information
electronic data storage systems. Today, the most prom- storage, memory density with arriving technology has
inent one is the limited capacity for continued scaling been increased dramatically from the past couple of
of the electronic device structure. Research is moving years. The main drive to develop organic nonvolatile
along the following paths for embedded Flash devices: memory is currently for applications of thin-film, flexible,
(i) scaling down the cell size of device memory, (ii) low- or even printed electronics. One needs a technology to tag
ering voltage operation, and (iii) increasing the density everything to electronic functionality which can be fore-
of state per memory cell by using a multilevel cell. To seen in a very large quantity and at a very low cost on sub-
sustain the continuous scaling, conventional Flash de- strates such as plastic and paper. Accessible popularization
vices may have to undergo revolutionary changes. Ba- of roll-to-roll memory commercialization is a way to make
sically, it is expected that an entire DVD collection be an encounter interesting and challenging to have charge
in the palm of a hand. Novel device concepts with new storage devices of choice for applications with enormous
physical operationing principles are needed. It is worth- flexibility and strength. Recently, polymer (plastic memory)
while to take a look at semiconductor memories against and organic memory devices have significant consideration
the background of digital systems. The way semicon- because of their simple processes, fast operating speed, and
ductor devices are used in a systems environment de- excellent switching ability [9,10]. One significant advantage
termines what is required of them in terms of density, polymer memory has over conventional memory de-
speed/power, and functions. It is also worthwhile to signs is that it can be stacked vertically, yielding a
look into the economic significance of semiconductor three-dimensional (3-D) use of space [11]. This means
memories and the relative importance of their various that in terabyte solid-state devices with extremely low
types. For the past three and a half decades in exist- transistor counts such as drives about the size of a
ence, the family of semiconductor memories has ex- matchbook, the data persists even after power is re-
panded greatly and achieved higher densities, higher moved. The NAND Flash market is continually growing
speeds, lower power, more functionality, and lower by the successive introduction of innovative devices
costs [3,6,7]. At the same time, some of the limitations and applications. To meet the market trend, 3-D NVMs
within each type of memory are also becoming more are expected to replace the planar ones, especially for
realized. As such, there are several emerging technolo- 10-nm nodes and beyond. Moreover, simple-structure
gies aiming to go beyond those limitations and poten- organic bistable memory exhibiting superior memory
tially replace all or most of the existing semiconductor features has been realized by employing various nano-
memory technologies to become a universal semicon- particles (NPs) blended into a single-layered organic
ductor memory (USM). In addition, the rewards for material sandwiched between two metal electrodes
achieving such a device would be to gain control of an [12,13]. The NPs act as traps that can be charged and
enormous market, which has expanded from computer discharged by suitable voltage pulses. NP blends show
applications to all of consumer electronic products. promising data retention times, switching speed, and
Looking forward to the future, there are wide ranges of cycling endurance, but the on-state current is too low
emerging memory applications for automation and in- to permit scaling to nanometer dimensions [10,14]. A
formation technology to health care. The specification lot of these great ideas tend to die before reaching this
of nonvolatile memory (NVM) is based on the floating point of development, but that is not to say that we will
gate configuration, which is the feature of an erased be seeing plastic memory on store shelves next year.
gate put into many cells to facilitate block erasure. There are still many hurdles to get over; software alone
Among them, designed Flash memories such as NOR is a big task, as is the manufacturing process, but it
and NAND Flash have been developed and then pro- does bring this technology one step closer to reality
posed as commercial products into bulk market. They [15]. It is not an exaggeration to say that the equivalent
have been considered as the most important products. of 400,000 CDs, 60,000 DVDs, or 126 years of MPG
NOR has high operation speed for both code and data music may be stored on a polymer memory chip the
storage applications; on the other hand, NAND has size of a credit card.
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The vision of this review (SRAM) and dynamic random-access memory (DRAM),
In this review, we focus on electrically programmable need voltage supply to hold their information while non-
nonvolatile memory changes from silicon nanocrystal volatile memories, namely Flash memories, hold their in-
memory scaling to organic and metallic NP memory de- formation without one. DRAM (dynamic stands for the
vices. Further, the scaling trend move towards the emer- periodical refresh) is needed for data integrity in contrast
ging NVM to flexible and transparent redox-based to SRAM. The basic circuit structures of DRAM, SRAM,
resistive switching memory technologies. This review is and Flash memories are shown in Figure 1. DRAM,
intended to give an overview to the reader of storage SRAM, and Flash are today's dominant solid-state mem-
systems and components from conventional memory de- ory technologies, which have been around for a long time,
vices that have been proposed in the past years of recent with Flash the youngest, at 25 years. DRAM is built using
progress in current NVM devices based on nanostruc- only one transistor and one capacitor component, and
tured materials to redox-based resistive random-access SRAM is usually built in CMOS technology with six tran-
memory (RRAM) to 3-D and transparent memory de- sistors. Two cross-coupled inverters are used to store the
vices. We describe the basics of Flash memory and then information like in a flip-flop. For the access control, two
highlight the present problems with the issue of scaling further transistors are needed. If the write line is enabled,
tunnel dielectric in these devices. We briefly describe a then data can be read and set with the bit lines. The Flash
historical change, how the conventional FG nonvolatile memory circuit works with the FG component. The FG is
memory suffers from a charge loss problem as the fea- between the gate and the source-drain area and isolated
ture size of the device continues to shrink. A discrete by an oxide layer. If the FG is uncharged, then the gate
polysilicon-oxide-nitride-oxide-silicon (SONOS) mem- can control the source-drain current. The FG gets filled
ory is then proposed as a replacement of the conven- (tunnel effect) with electrons when a high voltage at the
tional FG memory. The NC memory is expected to gate is supplied, and the negative potential on the FG
efficiently preserve the trapped charge due to the works against the gate and no current is possible. The FG
discrete charge storage node while also demonstrating can be erased with a high voltage in reverse direction of
excellent features such as fast program/erase speeds, low the gate. DRAM has an advantage over SRAM and Flash
programming potentials, and high endurance. We also of only needing one MOSFET with a capacitor. It also has
discuss current ongoing research in this field and the so- the advantage of cheap production as well as lower power
lutions proposed to solve the scaling problems by dis- consumption as compared to SRAM but slower than
cussing a specific solution in detail which would be the SRAM. On the other hand, SRAM is usually built in
centerpiece in recent memory work progress. Moreover, CMOS technology with six transistors and two cross-
this review makes distinct emerging memory concepts with coupled inverters, and for the access control, two further
more recent molecular and quantum dot programmable transistors are needed. SRAM has the advantage of being
nonvolatile memory concepts, specifically using charge quick, easy to control, integrated in the chip, as well as
trapping in conjugated polymers and metal NPs. We clas- fast because no bus is needed like in DRAM. But SRAM
sify several possible devices, according to their operating has the disadvantages of needing many transistors and
principle, and critically review the role of π-conjugated ma- hence expensive, higher power consumption than DRAM.
terials in the data storage device operation. We describe In comparison to DRAM and SRAM, Flash memory has
specifications for applications of emerging NVM de- FG between the gate and the source-drain area and iso-
vices as well as already existing NAND memory and re- lated with an oxide layer. Flash memory does not require
view the state of the art with respect to these target power to store information but is slower than SRAM and
specifications in the future. Conclusions are drawn re- DRAM.
garding further work on materials and upcoming mem- Both types of memories can be further classified based
ory devices and architectures. on the memory technology that they use and based on
data volatility as shown in the classification flow chart
Classification of solid-state memory technologies depicted in Figure 2. Volatile memories consist mostly
Data storage devices can be classified based on many of DRAM [17], which can be further classified into
functional criteria. Of them, silicon-based semiconductor SDRAM and mobile RAM which only retain informa-
memories are categorized into two: volatile and nonvola- tion when current is constantly supplied to the device
tile [3,16]. In volatile memories, the information eventu- [18]. Another small but very important memory device
ally fades while power supply is turned off unless the is SRAM. The market for DRAM devices far exceeds the
devices used to store data will be periodically refreshed. market for SRAM devices, although a small amount of
On the other hand, nonvolatile memories retain the stored SRAM devices is used in almost all logic and memory
information even when the power supply is turned off. chips. However, DRAM uses only one transistor and one
Volatile memories, such as static random-access memory capacitor per bit, allowing it to reach much higher
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Figure 1 The circuitry structures of DRAM, SRAM, and Flash memories.

densities and, with more bits on a memory chip, be Flash is further divided into two categories: NOR, char-
much cheaper per bit. SRAM is not worthwhile for desk- acterized by a direct write and a large cell size, and
top system memory, where DRAM dominates, but is NAND, characterized by a page write and small cell size.
used for its cache memories. SRAM is commonplace in Nonvolatile memory is a computer memory that can re-
small embedded systems, which might only need tens of tain the stored information even when not powered
kilobytes or less. Forthcoming volatile memory technolo- [3,19,20]. Nonvolatile semiconductor memories are gen-
gies that hope to replace or compete with SRAM and erally classified according to their functional properties
DRAM include Z-RAM, TTRAM, A-RAM, and ETA with respect to the programming and erasing operations,
RAM. In the industry, new universal and stable memory as shown in the flow chart described in Figure 2. These
technologies will appear as real contenders to displace are floating gate, nitride, ROM and fuse, Flash, emerging,
either or both NAND Flash and DRAM. Flash memory and other new next-generation memory technologies.
is presently the most suitable choice for nonvolatile ap- Today, these nonvolatile memories are highly reliable and
plications for the following reasons: Semiconductor non- can be programmed using a simple microcomputer and
volatile memories consist mostly of the so-called ‘Flash’ virtually in every modern electronic equipment, which are
devices and retain their information even when the expected to replace existing memories.
power is turned off. Other nonvolatile semiconductor Among them, emerging nonvolatile memories are now
memories include mask read-only memory (MROM), very captivating. The next-generation memory market
antifuse-based one-time programmable (OTP) memory, will cover up these emerging memory technologies [21].
and electrically erasable read-only memory (EEPROM). There are mainly five types of nonvolatile memory

Figure 2 Flow chart for the semiconductor memory classification according to their functional criteria.
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technology: Flash memory, ferroelectric random-access memristor technology and should be considered as po-
memory (FeRAM), magnetic random-access memory tentially a strong candidate to challenge NAND Flash.
(MRAM), phase-change memory (PCM), and RRAM. Currently, FRAM, MRAM, and PCM are in commercial
Nonvolatile memory, specifically ‘Flash’ memory, which production but still, relative to DRAM and NAND Flash,
is characterized by a large-block (or ‘sector’) erasing remain limited to niche applications. There is a view that
mechanism, has been the fastest growing segment of the MRAM, STT-RAM, and RRAM are the most promising
semiconductor business for the last 10 years. Some of emerging technologies, but they are still many years
these newer emerging technologies include MRAM, away from competing for industry adoption [23]. Any
FeRAM, PCM, spin-transfer torque random-access new technology must be able to deliver most, if not all,
memory (STT-RAM), RRAM and memristor. MRAM is of the following attributes in order to drive industry
a nonvolatile memory [10,22]. Unlike DRAM, the data is adoption on a mass scale: scalability of the technology,
not stored in an electric charge flow, but by magnetic speed of the device, and power consumption to be better
storage elements. The storage elements are formed by than existing memories. The NVSM is in inspiring
two ferromagnetic plates, each of which can hold a mag- search of novel nonvolatile memories, which will suc-
netic field, separated by a thin insulating layer. One of cessfully lead to the realization and commercialization of
the two plates is a permanent magnet set to a particular the unified memory.
polarity; the other's field can be changed to match that In progress, another new class of nonvolatile memory
of an external field to store memory. STT-RAM is an technologies will offer a large increase in flexibility com-
MRAM (nonvolatile) but with better scalability over pared to disks, particularly in their ability to perform
traditional MRAM. The STT is an effect in which the fast, random accesses. Unlike Flash memory, these new
orientation of a magnetic layer in a magnetic tunnel technologies will support in-place updates, avoiding the
junction or spin valve can be modified using a spin- extra overhead of a translation layer. Further, these new
polarized current. Spin-transfer torque technology has nonvolatile memory devices based on deoxyribonucleic
the potential to make MRAM devices combining low acid (DNA) biopolymer and organic and polymer mate-
current requirements and reduced cost possible; how- rials are one of the key devices for the next-generation
ever, the amount of current needed to reorient the memory technology with low cost. Nonvolatile memory
magnetization is at present too high for most commer- based on metallic NPs embedded in a polymer host has
cial applications. PCM is a nonvolatile random-access been suggested as one of these new cross-point memory
memory, which is also called ovonic unified memory structures. In this system, trap levels situated within the
(OUM), based on reversible phase conversion between bandgap of the polymer are introduced by the NPs
the amorphous and the crystalline state of a chalcogen- [24,25]. Memory devices play a massive role in all emer-
ide glass, which is accomplished by heating and cooling ging technologies; as such, efforts to fabricate new or-
of the glass. It utilizes the unique behavior of chalcogen- ganic memories to be utilized in flexible electronics are
ide (a material that has been used to manufacture CDs), essential. Flexibility is particularly important for future
whereby the heat produced by the passage of an electric electronic applications such as affordable and wearable
current switches this material between two states. The electronics. Much research has been done to apply the
different states have different electrical resistance which flexible electronics technology to practical device areas
can be used to store data. The ideal memory device or such as solar cells, thin-film transistors, photodiodes,
the so-called unified memory would satisfy simultan- light-emitting diodes, and displays [26-28]. Research on
eously three requirements: high speed, high density, and flexible memory was also initiated for these future elec-
nonvolatility (retention). At the present time, such mem- tronic applications. In particular, organic-based flexible
ory has not been developed. The floating gate nonvola- memories have merits such as a simple, low-temperature,
tile semiconductor memory (NVSM) has high density and low-cost manufacturing process. Several fabrication
and retention, but its program/erase speed is low. results of organic resistive memory devices on flexible
DRAM has high speed (approximately 10 ns) and high substrates have been reported [29,30]. In addition, with
density, but it is volatile. On the other hand, SRAM has growing demand for high-density digital information stor-
very high speed (approximately 5 ns) but limited from age, NAND Flash memory density has been increased dra-
very low density and volatility. It is expected that PCM matically for the past couple of decades. On the other
will have better scalability than other emerging tech- hand, device dimension scaling to increase memory dens-
nologies. RRAM is a nonvolatile memory that is similar ity is expected to be more and more difficult in a bit-cost
to PCM. The technology concept is that a dielectric, scalable manner due to various physical and electrical lim-
which is normally insulating, can be made to conduct itations. As a solution to the problems, NAND Flash
through a filament or conduction path formed after ap- memories having stacked layers are under developing ex-
plication of a sufficiently high voltage. Arguably, this is a tensions [31,32]. In 3-D memories, cost can be reduced by
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building multiple stacked cells in vertical direction with- storage networking industry association (SNIA) technical
out device size scaling. As a breakthrough for the scaling working group [33,34]. The Flash memory marketplace
limitations, various 3-D stacked memory architectures are is one of the most vibrant and exciting in the semicon-
under development and expecting the huge market of 3-D ductor industry, not to mention one of the most com-
memories in the near future. With lots of expectation, petitive. The continuous invention of new memory
future-generation memories have potential to replace technologies and their applications in the memory mar-
most of the existing memory technologies. The new and ket also increase performance demands. These new clas-
emerging memory technologies are also named to be a ses of memories with the latest technology increase the
universal memory; this may give rise to a huge market for vertical demand in the future memory market. In the
computer applications to all the consumer electronic next coming years, cumulative price reductions should be-
products. come disruptive to DVDs and hard disk drives (HDDs),
stimulate huge demand, and create new Flash markets.
Market memory technologies by applications The nonvolatile memories offer the system a different
The semiconductor industry has experienced many opportunity and cover a wide range of applications, from
changes since Flash memory first appeared in the early consumer and automotive to computer and communica-
1980s. The growth of consumer electronics market urges tion. Figure 3 shows NVSM memory consumption by
the demand of Flash memory and helps to make it a various applications in the electronics industry by mar-
prominent segment within the semiconductor industry. ket in 2010 extending upwards from computers and
The Flash memories were commercially introduced in communication to consumer products [22]. It is noticed
the early 1990s, and since that time, they have been able that there is a faster growth rate of the digital cellular
to follow Moore's law and the scaling rules imposed by phone since 1990; the volume of production has in-
the market. There are expected massive changes in the creased by 300 times, e.g., from 5 million units per year
memory market over the next couple of years, with to about 1.5 billion units per year. Nowadays, flexibility
more density and reliable technologies challenging the and transparency are particularly of great significance
dominant NAND Flash memory now used in SSDs and for future electronic applications such as affordable and
embedded in mobile products. Server, storage, and appli- wearable electronics. Many advanced research technolo-
cation vendors are now working on new specifications gies are applied to flexible technology to be used in a
to optimize the way their products interact with NVM - real electronics area [35]. Although silicon-based semi-
moves that could lead to the replacement of DRAM and conductor memories have played significant roles in
hard drives alike for many applications, according to a memory storage applications and communication in

Figure 3 Various NVSM applications in the electronics industry by market size in 2010. Reprinted from ref. [22].
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consumer electronics, now, the recent focus is turning In recent years, IDTechEx finds that the total market
from rigid silicon-based memory technology into a soft for printed, flexible, and organic electronics will grow
nonvolatile memory technology for low-cost, large-area, from $16.04 billion in 2013 to $76.79 billion in 2023 and
and low-power flexible electronic applications. Further, this growing trend is expected to continue in the coming
the memory market for the long term is continuously years (see Figure 5a). The majority of that is OLEDs
growing, even if with some ups and downs, and this is (only organic, not printed) and conductive ink used for a
expected to continue in the coming years [36]. Since wide range of applications. On the other hand, stretch-
innovation drives the semiconductor industry, a new able electronics, logic and memory, and thin-film sen-
trend with transparency as well as flexibility and 3-D sors are much smaller ingredients but having huge
technologies will be attractive and move towards con- growth potential as they emerge from R&D [38]. The re-
tinuous growth in the near future. port specifically addresses the big picture that over 3,000
Successive creation of new mobile devices leads to the organizations are pursuing printed, organic, flexible elec-
continual growth of NAND products as shown in tronics, including printing, electronics, materials, and
Figure 4. To meet this market demand, early this year, 30- packaging companies. While some of these technologies
nm node technologies are in ramping-up phase, 20-nm are in use now - indeed there are main sectors of busi-
node technologies are in the phase of transition to mass ness which have created billion-dollar markets - others
production, and a 10-nm node technology is under de- are commercially embryonic.
velopment. In addition, the future market requires high- Another key potential market for printed/flexible elec-
speed operation even up to approximately 1,500 MB/s in tronics is next-generation transparent conductive film to
order to satisfy a large amount of data correspondence replace brittle and expensive indium tin oxide (ITO) in
[37]. However, high-speed operations cause high power touch screens and displays, lighting, and photovoltaics.
consumption and chip temperature increase, which can Touch display research says that the market for non-ITO
deteriorate NAND reliability. Hence, reduction of ope- transparent conductors will be about $206 million this year
rating voltage is inevitable to achieve the future NAND. and grow to some $4 billion by 2020 as shown in Figure 5b.
Opportunities for the use of 3-D as well as polymer mem- ‘High demand for touchscreens for notebook and PC size
ory design in modern electronic circuits are rapidly displays has created a shortage of ITO touch sensors since
expanding, based on the very high performance and the end of last year to drive more interest in these tech-
unique functionality. However, their practical implementa- nologies, and the more flexible and potentially cheaper re-
tion in electronic applications will ultimately be decided placement technologies are getting more mature, notes
by the ability to produce devices and circuits at a cost that Jennifer Colegrove, president and analyst, who will speak
is significantly below that needed to manufacture conven- at the FlexTech workshop on transparent conductors. She
tional electronic circuits based on, for example, silicon. If notes that Atmel, Fujifilm, Unipixel and Cambrios are all
successful, these low-cost fabrication processes will ultim- in some phase of production’ [39]. A large amount of the
ately result in the printing of large-area organic electronic semiconductor market (approximately 20%) is given by the
circuits on a sheet of plastic paper using a roll-to-roll semiconductor memories; thus, the market for chips will
method, where low-temperature deposition of organics is develop in the next few years. This study reports that there
followed by metal deposition and patterning in a continu- is an analysis of the production process and the subsequent
ous, high-speed process analogous, perhaps, to processes value chain, which comprises a benchmark analysis of the
used in the printing of documents or fabrics. main segments of the semiconductor industry.

Figure 4 Growth of NAND Flash market up to 2014 (iSuppli) and the interface speed of various NAND applications. Reproduced from ref. [37].
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Figure 5 Market volume (a) and global flexible display market shipment forecast (b). Reproduced from refs. [38,39].

Recently, the 3-D nonvolatile memory structure has also integration promises to be an excellent replacement of
attracted considerable attention due to its potential to re- current technologies for the development of NAND Flash
place conventional Flash memory in next-generation memory. Time is running out for planar NAND technol-
NVM applications [37,40]. 3-D memories are gathering ogy. It will not be long that planar NAND will be com-
increasing attention as future ultra-high-density memory pletely replaced by 3-D NAND. 3-D NAND promises to
technologies to keep a trend of increasing bit density and satisfy the growing need of NAND memory [37].
reducing bit cost. The NAND Flash market is continu- Finally, NVM technologies have a bright future since
ously growing by the successive introduction of innovative every end-use application needs to store some parame-
devices and applications. To meet the market trend, 3-D ters or some amount of an application program in the
NVMs are expected to replace the planar one, especially on-board NVM to enable it to function. The upcoming
for 10-nm nodes and beyond. Therefore, the fundamentals NVMs are the big hope for a semiconductor memory
and current status of the 3-D NAND Flash memory are market, which provides memories for systems to run
reviewed and future directions are discussed [41]. 3-D with flexibility, reliability, high performance, and low
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power consumption in a tiny footprint in nearly every products address the urgent need in some specific and
electronic application. Recent market trends have indi- small-form devices. Therefore, emerging nonvolatile
cated that commercialized or near-commercialized cir- memory products provide market data about the size of
cuits are optimized across speed, density, power efficiency, growth of the application segments and the developments
and manufacturability. Flash memory is not suited to all of business opportunities. Until now, only FeRAM, PCM,
applications, having its own problems with random-access and MRAM were industrially produced and available in
time, bit alterability, and write cycles. With the increasing low-density chips to only a few players. Thus, the market
need to lower power consumption with zero-power was quite limited and considerably smaller than the vola-
standby systems, observers are predicting that the time tile DRAM- and nonvolatile Flash NAND-dominant mar-
has come for alternative technologies to capture at least kets (which enjoyed combined revenues of $50+ billion in
some share in specific markets such as automotive smart 2012). However, in the next 5 years, the scalability and
airbags, high-end mobile phones, and RFID tags. An chip density of those memories will be greatly improved
embedded nonvolatile memory with superior perform- and will spark many new applications with NVM market
ance to Flash could see widespread adoption in system- drivers explained in more detail.
on-chip (SoC) applications such as smart cards and Accompanied by the adoption of STT-MRAM and
microcontrollers. PCM cache memory, enterprise storage will be the lar-
gest emerging NVM market. NVM will greatly improve
Emerging NVM technologies for applications the input/output performance of enterprise storage sys-
The new emerging nonvolatile random-access memory tems whose requirements will intensify with the growing
products address the urgent need in some specific and need for web-based data supported by floating mass
small-form devices. Therefore, iRAP felt a need to do a servers. In addition, mobile phones will increase their
detailed technology update and market analysis in this adoption of PCM as a substitute to Flash NOR memory
industry [42]. Recently, Yole Développement reports de- in MCP packages to 1-gigabyte (GB) chips made avail-
scribe that emerging memory technologies have great able by Micron in 2012. Higher-density chips, expected
potential to improve future memory devices to be in- in 2015, will allow access to smart phone applications
creasingly used in various markets of industry and trans- that are quickly replacing entry-level phones. STT-
portation, enterprise storage, mobile phones, mass MRAM is expected to replace SRAM in SoC applica-
storage, and smart cards [43]. Emerging NVM applica- tions, thanks to lower power consumption and better
tions in various markets are shown in Figure 6. But there scalability. Smart cards and microcontrollers (MCU) will
are numerous opportunities existing for novel architec- likely adopt MRAM/STT-MRAM and PCM as a substi-
tures and applications that these emerging memory tute to embed Flash. Indeed, Flash memory cell size re-
technologies can enable. These new emerging NVM duction is limited in the future. The NVM could reduce

Figure 6 Emerging NVM applications in various markets.

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the cell size by 50% and thus be more cost-competitive. market for emerging nonvolatile random-access memory
Additional features like increased security, lower power products was projected to have reached $200 million in
consumption, and higher endurance are also appealing 2012. This market is expected to increase to $2,500
NVM attributes. The mass storage markets served by million by 2018 at an average annual growth at a CAGR
Flash NAND could begin using 3-D RRAM in 2017 to of +46% through the forecast period with mobile
2018, when 3-D NAND will slow down its scalability as phones, smart cards, and enterprise storage as main growth
predicted by all of the main memory players. If this hap- drivers (Figure 7). Market adoption of memory is strongly
pens, then a massive RRAM ramp-up will commence in dependent on its scalability. This Yole Développement re-
the next decade that will replace NAND; conditional 3- port provides a precise memory roadmap in terms of
D RRAM cost-competitiveness and chip density are technological nodes, cell size, and chip density for each
available. It is expected surely that the emerging NVM emerging NVM such as FeRAM, MRAM/STT-MRAM,
business will be very dynamic over the next 5 years, PCM, and RRAM. A market forecast is provided for each
thanks to improvements in scalability/cost and density technology by application, units, revenues, and also market
of emerging NVM chips [44]. growth as given a detailed account of emerging NVM mar-
According to a recently published report from Yole ket forecast (Figure 7). PCM devices, the densest NVM in
Développement, Emerging Non-volatile Memory Tech- 2012 at 1 GB, will reach 8 GB by 2018, which are expected
nologies, Industry Trends and Market Analysis, the global to replace NOR Flash memory in mobile phones and will

Figure 7 Emerging NVM market forecast by applications from 2012 to 2018 (in M$). Reproduced from ref. [43].
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also be used as a storage class memory in enterprise stor- popularity over conventional secondary storage devices
age. MRAM/STT-MRAM chips will reach 8 to 16 GB in like hard disks. The Flash memory fabrication process is
2018. They will be widely sold as a storage class memory compatible with the current CMOS process and is a suit-
and possibly as a DRAM successor in enterprise storage able solution for embedded memory applications. A Flash
after 2018. By 2018, MRAM/STT-MRAM and PCM will memory cell is simply a MOSFET cell, except that a poly-
surely be the top two NVM on the market. Combined, they silicon floating gate [46] (or a silicon nitride charge trap
will represent a $1.6 billion business by 2018, and their layer) is sandwiched between a tunnel oxide and an inter-
sales will almost double each year, with double-density polyoxide to form a charge storage layer [47]. Although
chips launched every 2 years. FeRAM will be more stable Flash memory is likely the standard charge storage device
in terms of scalability, with 8- to 16-MB chips available by for the next generation, scaling may eventually be limited
2018; the development of a new FRAM material could by the tunnel oxide limit [8]. In terms of the operation
raise scalability, but we do not expect it to be widely indus- speed of program and erase, Flash memory requires a thin
trialized and commercialized before 2018. FeRAM will tunnel oxide to enhance the carrier transport between the
grow at a steady growth rate (10% per year) and will focus floating gate and the silicon substrate. However, the very
on industrial and transportation applications because of thin tunnel oxide suffers from many reliability issues like
the low-density availability, whereas RRAM revenues reduction in operation voltage, and after a considerable
would not really surge by 2018, with the availability of number of program and erase cycles, the tunnel oxide
high-density chips of several tens of gigabytes that could undergoes deterioration loss [48]. Thus, researchers have
replace NAND technology. Meanwhile, it has also been focused on possible solutions and proposed alternate tech-
considered by memory technologist experts that for large- nologies, including nitride-based memory, nanocrystal
volume markets like mass storage NAND, only one tech- memory, and switching memory. All other nonvolatile
nology will be adopted in order to reduce production cost memories require integration of new materials that are
and RRAM seems to be the best candidate. But the real not as compatible as the conventional CMOS process.
massive adoption of emerging NVM as a replacement for
NAND and DRAM will happen after 2020. NOR and NAND Flash memory technologies
NOR and NAND Flash, two major Flash types, are dom-
Advances in Flash memory technologies inant in the memory market. NOR Flash has lower dens-
Flash memory is basically a MOSFET nonvolatile device ity but a random-access interface, while NAND Flash
that can be electrically erased and reprogrammed [3,45]. has higher density and interface access through a com-
It is a technology that is primarily used in memory cards mand sequence [49]. Their corresponding structures are
and Flash drives for general storage and transfer of data shown in Figure 8. NOR and NAND Flash come from
between computers and other digital products. Since the the structure used for the interconnections between
invention of the transistor, NVSM had been the most memory cells. Intel is the first company to introduce a
important invention in the electron device field. The commercial (NOR type) Flash chip in 1988, and Toshiba
floating gate memory was used to store the information released the world's first NAND Flash in 1989 [50]. De-
and a tunneling current for programming and erasing pending on how the cells are organized in the matrix, it
operations. The charge is injected into or removed from is possible to distinguish between NAND Flash memor-
the floating gate and the floating gate remains in that ies and NOR Flash memories. In NOR Flash, cells are
state, even after power is removed, which means that connected in parallel to the bit lines, which notably
Flash memory is nonvolatile. The invention of NVSM allow the cells to be read and programmed individually.
further gave rise to a new class of memory devices and The parallel connection of NOR Flash cells resemble the
hence broadened its applications to become ubiquitous. parallel connection of transistors in a CMOS NOR gate
There are a large number of products in the market now architecture. On the other hand, in NAND Flash, the
which use Flash devices exclusively as secondary storage. cells are connected in series, resembling a NAND gate.
Few examples of their applications include medical diag- The series connections consume less space than the par-
nostic systems, notebook computers, digital audio players, allel ones, reducing the cost of NAND Flash. It does not,
digital cameras, mobile phones, personal digital assistants, by itself, prevent NAND cells from being read and pro-
digital televisions, universal serial bus (USB) Flash per- grammed individually. Most of the engineers and scien-
sonal disks, Global Positioning Systems, and many more. tists are not so familiar with the differences between
Semiconductor storage devices store data in tiny memory these two technologies. Generally, they usually refer to
cells made of very small transistors and capacitors made the NOR architecture as ‘Flash’ and are unaware of the
of semiconductor materials such as silicon. Each cell can NAND Flash technology and its many benefits over
hold 1 bit of information and an array of cells stores a NOR [51]. This could be due to the fact that most Flash
large chunk of information. Flash devices are gaining devices are used to store and run codes (usually small),
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applications. However, more processors include a direct

NAND interface and can boot directly from NAND
(without NOR). However, NAND cannot perform read
and write operations simultaneously; it can accomplish
these at a system level using a method called shadowing,
which has been used on PCs for years by loading the
BIOS from the slower ROM into the high-speed RAM.
Table 1 highlights the major differences between NOR
and NAND. It shows that NAND is ideal for high-
capacity data storage while NOR is best used for code
storage and execution, usually in small capacities. There
are many other differences between these two technolo-
gies which will be further discussed individually. How-
ever, those listed in the table are enough to strongly
differentiate the types of applications using them: NOR
is typically used for code storage and execution. This,
mainly in capacities up to 4 MB, is common in applica-
tions such as simple consumer appliances, low-end cell
phones, and embedded applications, while raw NAND is
Figure 8 Comparison of NOR Flash array and NAND Flash used for data storage in applications such as MP3
array architectures. players, digital cameras, and memory cards [55-57]. The
codes for raw NAND-based applications are stored in
NOR devices.
for which NOR Flash is the default choice, although we
are providing some major differences between NOR and Scaling and challenges of Flash memory technologies
NAND Flash technologies by their architecture and the Currently, there have been increasing demands on redu-
internal characteristic features of the individual Flash. cing the feature size in microelectronic products and
NOR Flash is slower in erase operation and write op- more interest in the development of Flash memory de-
eration compared to NAND Flash [52]. This means that vices to meet the growing worldwide demand. A conven-
NAND Flash has faster erase and write times. Moreover, tional FG memory device must have a tunnel oxide layer
NAND Flash has smaller erase units, so fewer erases are thickness of 8 nm to prevent charge loss and to make
needed. NOR Flash can read data slightly faster than 10 years' data retention certain. This necessity will limit
NAND Flash. NOR Flash offers complete address and scalability for Flash memory devices [8,58]. Thus, in
data buses to randomly access any of its memory loca- order to meet technology scaling in the field of memory
tions (addressable to every byte). This makes it a suitable and data storage devices, mainstream transistor-based
replacement for older ROM BIOS/firmware chips, which Flash technologies will be developed gradually to incorp-
rarely needs to be updated. Its endurance is 10,000 to orate material and structural innovations [59]. Dielectric
1,000,000 erase cycles. NOR Flash is highly suitable for
storing codes in embedded systems. Most of today's Table 1 Comparison between NOR and NAND Flash
microcontrollers come with built-in Flash memory [53]. memories [55-57]
NAND Flash occupies a smaller chip area per cell. Features NOR NAND
This makes NAND Flash available in greater storage Memory size ≤512 Mbit 1 to 8 Gbit
densities and at lower costs per bit than NOR Flash. It Sector size Approximately 1 Mbit Approximately 1 Mbit
also has up to ten times the endurance of NOR Flash. Program time 9 μs/word 400 μs/page
NAND is more fit as storage media for large files includ- Erase time 1 s/sector 1 ms/sector
ing video and audio. USB thumb drives, SD cards, and
Read access time <80 ns 20 μs
MMC cards are of NAND type [54]. NAND's advantages
are fast write (program) and erase operations, while Write parallelism 8 to 16 words 2 Kbyte
NOR's advantages are random access and byte write Output parallelism Byte/word/dword Byte/word
capability. NOR's random access ability allows for exe- Read parallelism 8 to 16 words 2 Kbyte
cute in place (XiP) capability, which is often a require- Access method Random Sequential
ment in embedded applications. NAND is slow random Price High Very low
accessible, while NOR is hampered by having slow write
Reliability Standard Low
and erase performance. NAND is better suited for filing
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scaling in nonvolatile memories has been reached near also increase. Electrical stress can increase the number
to the point where new approaches will be required to of these traps. So it becomes an important limitation of
meet the scaling requirements while simultaneously scaling down the memory device [62]. For EOT < 8 nm,
meeting the reliability and performance requirements a single oxide trap will cause to complete the charge loss
for future products. High-dielectric-constant materials in the FG Flash cell. The scaling of the gate stacks and
are being explored as possible candidates to replace both operation voltages are often related to each other. A tun-
the traditional SiO2 and oxide/nitride/oxide (ONO) films nel oxide thickness of more than 8 nm is currently used
used in Flash memory cells. Flash cell scaling has been in the commercial Flash memory chip to meet the
demonstrated to be really possible and to be able to fol- 10 years' data retention time requirement. If the tunnel
low Moore's law down to the 90-nm technology genera- oxide were to be scaled below 2 nm, the operation volt-
tions. The technology development and the consolidated age could be reduced from more than 10 V to below 4 V
know-how are expected to sustain the scaling trend [63]. Unfortunately, the retention time would also be re-
down to the 50-nm technology node and below as fore- duced, from 10 years to several seconds. This physical
casted by the International Technology Roadmap for damage to the tunnel oxide during the cycling process
Semiconductors (ITRS) in Figure 9, which indicates that causes data retention problems, program disturbance,
the silicon MOSFET was already in the nanoscale. The read disturbance, and erratic characteristic behavior of
minimum feature size of an individual CMOSFET has the FG memory cell. Such problems severely limit the
shrunk to 15 nm with an equivalent gate oxide thickness reliability and multilevel cell operation. This basic limita-
(EOT) of 0.8 nm in 2001 [13]. However, semiconductor tion of the tunnel oxide thickness becomes increasingly
Flash memory scaling is far behind CMOS logic device important with scaling. New storage node concepts are
scaling. For example, the EOT of the gate stack in semi- also becoming attractive as an alternative approach to
conductor Flash memory is still more than 10 nm. address some of the dielectric scaling limitations. Flash
Moreover, semiconductor Flash memory still requires memory adopts a charge stored in a silicon nitride as
operation voltages of more than 10 V, which is still far the trapping layer, which exhibits significantly reduced
from the operation voltage of CMOS logic devices. It is defect-related leakage current and very low SILC as
important to scale the EOT of the gate stack to achieve compared to SiO2 with a similar EOT [64]. Such a relent-
a small memory cell size and also prolong battery life. less reduction of device dimensions has many challenges
Another limitation of FG technology is that tunnel like retention, endurance, reduction in the number of elec-
oxide scaling is limited by stress-induced leakage current trons in the FG, dielectric leakage, cell-to-cell cross talk,
(SILC) related to charge transfer problem as indicated in threshold voltage shift, and reduction in memory window
Figure 10 [60,61]. The SILK increases with decreasing margins [65,66]. The key concept of real scaling issues
oxide thickness. This can be attributed to tunneling such as material and structural changes in Flash memory
assisted by the traps in the bulk of the dielectric. Trap- technologies is provided in detail in the next distinct part.
assisted tunneling can take place at very low electric
fields. If the density of traps is increased, the leakage will FG Flash memory technology
The FGNV memory is a basic building block of Flash
memory, which is based on FG thin-film storage (TFS)
memories that have been developed with the addition of
an erase gate configuration. The conventional FG mem-
ory (Figure 11a) consists of a MOSFET configuration
that is modified to include polysilicon as a charge stor-
age layer surrounded by an insulated inner gate (floating
gate) and an external gate (control gate). This what makes
Flash memory nonvolatile and all floating gate memories
to have the same generic cell structure. Charge is trans-
ferred to or from the floating gate through a thin (8 to
10 nm) oxide [1,67]. Because the floating gate is electric-
ally isolated by the oxide layer, any electrons placed on it
are trapped there. Flash memory works by adding (char-
ging) or removing (discharging) electrons to and from a
floating gate. A bit's 0 or 1 state depends upon whether or
not the floating gate is charged or discharged. When elec-
Figure 9 The trend of MOSFET scaling from ITRS. Reproduced
trons are present on the floating gate, current cannot flow
from ITRS Corp.
through the transistor and the bit state is ‘0’. This is the
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Figure 10 Schematic plots of a Flash memory cell and the degradation of its tunnel oxide. The degradation leads to the formation of
percolation paths responsible for the FG charge loss, hence the loss of the stored information. The presence of traps in the energy barrier yields
the trap-assisted tunneling mechanism and originates the stress-induced leakage current (SILC).

normal state for a floating gate. When electrons are re- cell's tunneling oxide layer is below 10 nm [70]. More-
moved from the floating gate, current is allowed to flow over, the SONOS memory exhibits many advantages, e.g.,
and the bit state is ‘1’. The FG memory has achieved high easy to fabricate, high program/erase (P/E) speed, low pro-
density, good program/erase speed, good reliability, and gramming voltage and power consumption, and better po-
low operating voltage and promotes endurance for Flash tential for scalability below the 70-nm node, according to
memory application. the ITRS [71]. The charge, holes or electrons, are injected
into the nitride layer using direct tunneling through the
SONOS memory technology tunnel oxide layer. The nitride layer is electrically isolated
In order to solve the scaling issue of the FG memory, from the surrounding transistor, although charges stored
the SONOS memory has been proposed as a Flash on the nitride directly affect the conductivity of the under-
technology since the 1980s [68,69]. The acronym lying transistor channel. Since the SONOS memory pos-
SONOS is derived from the structure of the device as sesses spatially isolated deep-level traps, a single defect in
shown in Figure 11b. The SONOS device is basically a the tunneling oxide will not cause discharge of the mem-
MOSFET, where the gate has been replaced by an ory cell. The thickness of the top oxide is important to
ONO dielectric. The SONOS memory has a better prevent the Fowler-Nordheim tunneling of electrons from
charge retention than the FG memory when the FG bit the gate during erase. When the polysilicon control gate is

Figure 11 Schematics of the conventional FG memory and SONOS. Schematics of (a) floating gate and thin-film storage-based embedded
nonvolatile memory bit cells, depending on the charge stored inside the gate dielectric of a MOSFET, and (b) the nitride traps (SONOS), embedded
into the gate oxide of a MOSFET.
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biased positively, electrons from the transistor source and problem. Many studies have shown that the charge reten-
drain regions tunnel through the oxide layer and get tion characteristics in scaled SONOS nonvolatile memory
trapped in the silicon nitride. This results in an energy devices with a low gate oxide thickness and at high
barrier between the drain and the source, raising the temperature are problematic with shallow-level traps
threshold voltage Vth (the gate-source voltage necessary [48,77,78]. For the conventional SONOS memory, erase
for current to flow through the transistor). Moreover, the saturation and vertical stored charge migration [79,80] are
nitride layer is electrically isolated from the surrounding the two major drawbacks; the most challenging tasks are
transistor, although charges stored on the nitride directly how to maintain an acceptable charge capability of the
affect the conductivity of the underlying transistor chan- discrete storage nodes and how to fabricate nanocrystals
nel. The oxide/nitride sandwich typically consists of a 2- with constant size, high density, and uniform distributions
nm-thick oxide lower layer, a 5-nm-thick silicon nitride [81]. When the trap energy level is shallow, erase satur-
middle layer, and a 5- to 10-nm-thick oxide upper layer ation and vertical migration occur and the electron charge
[72,73]. However, SONOS-type Flash memories have sev- decay rate increases due to low tunnel oxide thickness,
eral drawbacks such as shallow trap energy level, erase sat- issues that impact SONOS-type memories as shown in
uration, and vertical stored charge migration [74]. The Figure 12. This erase saturation makes SONOS erase
programming speed and operating voltage problems can less as the erase voltage or the tunnel oxide thickness is
be solved by reducing the tunnel oxide thickness. At low increased. Since the SONOS memory uses silicon ni-
tunnel oxide thickness, the issues that impact SONOS- tride as a charge trapping layer, the electrons in the Si
type memories include erase saturation and vertical sub-conduction band will tunnel through the tunneling
charge migration, which seriously degrade the retention oxide and a portion of the nitride, and this conse-
capability of the memory [75]. Thus, many concerns still quently degrades the program speed. Besides this, the
remain for the SONOS type of memories, which will be conduction band offset of nitride is only 1.05 eV and
discussed in the next section. back-tunneling of the trapped electron may also occur.
Although applying a very high electric field may accel-
Limitations of FG and SONOS memory technologies erate the de-trapping rate, the gate electron injection
Scaling demands very thin gate insulators in order to current exceeds the de-trapping but resulting in prac-
keep short channel effects and control the shrinkage of tically an increase in charge and no erasing. Using an
the device size and maximize the performance. When ultra-thin (<2 nm) tunnel oxide offers an efficient
the tunneling oxide thickness is below 10 nm, the stor- charge direct tunneling erase and opens a memory win-
aged charge in the FG is easy to leak due to a defect in dow. However, the direct tunneling cannot be turned
the tunneling oxide formed by repeated write/erase cy- off at a low electric field, leading to poor retention and
cles or direct tunneling current. read disturb. Thus, the SONOS memory cannot be
The tunneling gate oxide thickness in a conventional used for NAND Flash without further innovation of
Flash memory cannot be scaled down to sub-7 nm be- new memory technologies. The main reason for the
cause of charge retention [76]. The SONOS Flash mem- growth of emerging NVM technologies is that scaling
ory can relieve the problem but still has a relatively thick has now become a serious issue for the memory indus-
gate dielectric thickness of about 7 nm. Therefore, con- try. Not only are many of these new technologies inher-
ventional SONOS Flash memory also has a scaling-down ently more scalable, but also they seem well suited to

Figure 12 Fowler-Nordheim (FN) tunneling of electrons from the gate during erase and erase saturation in SONOS nonvolatile memory.
This indicates the reduced memory window as the erase voltage is increased. Reproduced from ref. [74].
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the next generation of mobile computing and commu- technologies will be briefly outlined and discussed in the
nications that will demand high-capacity memories following sections. In view of the commercial production,
capable of storing and rapidly accessing video and a currently, MRAM, FeRAM, and PCM are in commercial
large database without overburdening battery power production but still remain limited to niche applications
sources. relative to DRAM and NAND Flash. There is a prospect
Many alternate device structures are proposed to that among the emerging memory technologies, MRAM,
hopefully circumvent these scaling challenges and to im- STT-RAM, and RRAM are the most promising ones, but
prove the device performance. In an effort to continue they are still many years away from competing for indus-
Moore's law and overcome the ultimate limitations of try adoption [84]. It is necessary for any new technology
MOS-based memory devices, other storage concepts to be able to deliver most for industry adoption. For in-
have been proposed in search of the ‘unified memory’. dustry adoption on a mass scale, some parameters must
The ideal memory device or the so-called ‘unified mem- be matched with existing memory technologies. In consid-
ory’ would satisfy simultaneously three requirements: eration of new technology for industry application, the
high speed, high density, and nonvolatility. At the scalability of the technology, speed of the device, power
present time, such an ideal memory has not been devel- consumption to be better than existing memories, endur-
oped. FGNVSM has high density and nonvolatility, but ance, densities, better than existing technologies and most
its P/E speed is low. DRAM has high speed (approxi- importantly the cost; if the emerging technology can only
mately 10 ns) and relatively high density, but it is vola- run one or two of these attributes, then, at most desirable,
tile. SRAM has very high speed (approximately 5 ns), it is likely to be resigned to niche applications.
but it suffers from very low density and volatility. Many
nonvolatile memory devices have been proposed on the MRAM
basis of changing charge storage materials and new de- MRAM or magnetic RAM is a nonvolatile RAM tech-
vice concepts for the ‘unified memory’. These structures nology under development since the 1990s. RRAM
will be considered in the next sections. In light of such methods of storing data bits use magnetic charges in-
issues, emerging memory solutions seem to be a key stead of the electrical charges used by DRAM and
technology. SRAM technologies. MRAM, first developed by IBM in
the 1970s [85], is expected to replace DRAM as the
Current emerging memory technologies memory standard in electronics. MRAM is basically
Recent studies have revealed that there is a close correl- based on memory cells having two magnetic storage ele-
ation among existing and emerging memory technolo- ments, one with a fixed magnetic polarity and another
gies in view of scalability. The scaling trend of memory with a switchable polarity. These magnetic elements are
transition leads to smaller and smaller memory devices, positioned on top of each other but separated by a thin
which have been routinely observed. To further support insulating tunnel barrier as shown in the cell structure
this assertion, another set of current progress in memory in Figure 13. Moreover, scientists define a metal as mag-
technology is described to the increasing importance of netoresistive if it shows a slight change in electrical re-
memory to users' experience and the importance of sistance when placed in a magnetic field. By combining
memory to system performance. There are many emer- the high speed of static RAM and the high density of
ging memory technologies which are trying to replace DRAM, proponents say that MRAM could be used to
existing memory technologies in the market. These new
memory devices such as RRAM, PCM, and STT-RAM
have read/write/retention/endurance characteristics dif-
ferent from those of conventional SRAM, DRAM, and
Flash [82]. But the ideal characteristics of new emerging
memory technologies have to be meeting the perform-
ance of SRAM and the density of NAND Flash in terms
of stability, scalability, and switching speed. Thus, going
beyond the traditional bistable memory, the possibilities
of multilevel, high-performance memory devices suitable
for market must be explored. Currently, there are several
technologies that show some promise; some of these
new emerging technologies are MRAM, FeRAM, PCM,
STT-RAM, nano-random-access memory (NRAM), race-
track memory, RRAM and memristor, molecular mem-
Figure 13 Basic MRAM cell structure.
ory, and many others [10,83]. Each of these memory
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significantly improve electronic products by storing

greater amounts of data, enabling it to be accessed faster
while consuming less battery power than existing elec-
tronic memories. Technically, it works with the state of
the cell, which is sensed by measuring the electrical resist-
ance while passing a current through the cell. Because of
the magnetic tunnel effect [86], if both magnetic moments
are parallel to each other, then the electrons will be able to
tunnel and the cell is in the low resistance ‘ON’ state.
However, if the magnetic moments are antiparallel, the
cell resistance will be high. The memory characteristics of
MRAM of writing and erasing are fulfilled by passing a
current through the write line to induce a magnetic field
across the cell. MRAM has been slowly getting off the Figure 14 Basic STT-RAM cell structure.
ground but has now entered the market and will become
increasingly available for mass production in the couple of polarized by aligning the spin direction of the electrons
years and beyond. Currently, it has reached some level of flowing through a magnetic tunnel junction (MTJ)
commercial success in niche applications [87]. Various element. Data writing is performed by using the spin-
companies such as Samsung, IBM, Hitachi and Toshiba, polarized current to change the magnetic orientation of
and TSMC are actively developing variant technologies of the information storage layer in the MTJ element [94].
MRAM chips. In view of power consumption and speed, The resultant resistance difference of the MTJ element
MRAM competes favorably than other existing memories is used for information readout. STT-RAM is a more
such as DRAM and Flash, with an access time of a few appropriate technology for future MRAM produced
nanoseconds [88-90]. Although it has some limitation using ultra-fine processes and can be efficiently embed-
during the ‘write’ operation, the smaller cell size could be ded in subsequent generations of such semiconductor
limited by the spread of the magnetic field into neighbor- devices as FPGAs, microprocessors, microcontrollers,
ing cells and need an amendment to compete completely and SoC. A special bonus for embedded designers is
as a universal memory. The price of MRAM is also an- the fact that the internal voltage STT-RAM requires is
other issue and considered a limiting factor, with prices only 1.2 V. The difference between STT-MRAM and a
far in excess of all the currently established memories at conventional MRAM is only in the writing operation
approximately £2 to £3 ($3 to $5) per megabyte [91]. Ac- mechanism; the read system is the same. The memory
cording to this price level, MRAM is in excess of 1,000 cell of STT-MRAM is composed of a transistor, an
times the price of Flash memory and over 10,000 times MTJ, a word line (WL), a bit line (BL), and a source
the price of hard disk drives. It is expected that of the line (SL) [95]. Currently, STT-RAM is being developed
next-generation memory technologies, MRAM, in the fu- in companies including Everspin, Grandis, Hynix, IBM,
ture, will have the biggest market, followed by FeRAM, Samsung, TDK, and Toshiba. However, for STT-RAM
PCRAM, and memristors. to be adopted as a universal mainstream semiconductor
memory, some key challenges should be resolved: the
STT-MRAM simultaneous achievement of low switching current and
STT-MRAM is a magnetic memory technology that exerts high thermal stability. It must be dense (approximately
the base platform established by an existing memory 10 F2), fast (below 10 ns of read and write speeds), and
called MRAM to enable a scalable nonvolatile memory so- operating at low power [96].
lution for advanced process nodes [92,93]. It is a new kind
of magnetic RAM with the following features: fast read FeRAM
and write times, small cell sizes, potentially even smaller, FeRAM is a nonvolatile RAM that combines the fast
and compatibility with existing DRAM and SRAM. As we read and write access of DRAM cells, consisting of a
have discussed in the previous section, MRAM stores data capacitor and transistor structure as shown in Figure 15.
according to the magnetization direction of each bit The cell is then accessed via the transistor, which en-
and the nanoscopic magnetic fields set the bits in con- ables the ferroelectric state of the capacitor dielectric to
ventional MRAM. On the other hand, STT-MRAM be sensed. In spite of its name, FeRAM does not contain
uses spin-polarized currents, enabling smaller and less iron. The polarization properties of a ferroelectric sub-
energy-consuming bits. The basic cell structure of STT- stance are used as a memory device. Today's FeRAM
RAM is depicted in Figure 14. In addition, STT-RAM uses lead zirconate titanate (PZT); other materials are
writing is a technology in which an electric current is being considered. The main developer of FeRAM is
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Figure 15 Basic structure of a FeRAM cell. The crystal structure of a ferroelectric and an electric polarization-electric field hysteresis curve are
also shown.

Ramtron International. FeRAM is the most common PCRAM

kind of personal computer memory with the ability to PCRAM, also known as PCM, perfect RAM (PRAM),
retain data when power is turned off as do other nonvol- OUM, and chalcogenide RAM (CRAM), is a type of
atile memory devices such as ROM and Flash memory nonvolatile RAM based on a class of material called
[97]. In a DRAM cell, the data periodically need refresh- chalcogenide glasses that can exist in two different phase
ing due to the discharging of the capacitor, whereas states (e.g., crystalline and amorphous) [102,103]. The
FeRAM maintains the data without any external power basic PCRAM cell structure is depicted in Figure 16.
supply. It achieves this by using a ferroelectric material Most phase-change materials contain at least one elem-
in the place of a conventional dielectric material be- ent from group 6 of the periodic table, and the choice of
tween the plates of the capacitor. When an electric field available materials can be further widened by doping
is applied across dielectric or ferroelectric materials, it these materials [104-107]. In particular, the most prom-
will polarize, and while that field is removed, it will ising are the GeSbTe alloys which follow a pseudobinary
depolarize. But the ferroelectric material exhibits hyster- composition (between GeTe and Sb2Te3), referred to as
esis in a plot of polarization versus electric field, and it GST. These materials are in fact commonly used as the
will retain its polarization. One disadvantage of FeRAM data layer in rewritable compact disks and digital versa-
is that has a destructive read cycle. The read method in- tile disks (CD-RW and DVD-RW) where the change in
volves writing a bit to each cell; if the state of the cell optical properties is exploited to store data. The struc-
changes, then a small current pulse is detected by indi- ture of the material can change rapidly back and forth
cating that the cell was in the OFF state. However, it is between amorphous and crystalline on a microscopic
a fast memory that can endure a high number of cycles
(e.g., 1014) [98], meaning that the requirement for a
write cycle for every read cycle will not result in short
product lives with a very low power requirement. It is
expected to have many applications in small consumer
devices such as personal digital assistants (PDAs),
handheld phones, power meters, and smart cards, and
in security systems. FeRAM is faster than Flash mem-
ory. It is also expected to replace EEPROM and SRAM
for some applications and to become a key component
in future wireless products. Even after FeRAM has
achieved a level of commercial success, with the first
devices released in 1993 [99,100], current FeRAM chips
offer performance that is either comparable to or ex-
Figure 16 Basic PCRAM cell structure. Reproduced from
ceeding current Flash memories [98,101], but still
IBM-Macronix-Qimonda.
slower than DRAM.
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scale. The material has low electrical resistance in the Brand-new concepts such as RRAM, molecular, organic/
crystalline or ordered phase and high electrical resist- polymer, and other nanowire-based memory technologies
ance in the amorphous or disordered phase. This allows have also been proposed. These are discussed in detail in
electrical currents to be switched ON and OFF, repre- the following section.
senting digital high and low states. This process has
been demonstrated to be on the order of a few tens of RRAM
nanoseconds [108], which potentially makes it compat- RRAM is a disruptive technology that can revolutionize
ible with Flash for the read operation, but several orders the performance of products in many areas, from con-
of magnitude faster for the write cycle. This makes it sumer electronics and personal computers to automo-
possible for PCM to function many times faster than tive, medical, military, and space. Among all the current
conventional Flash memory while using less power. In memory technologies, RRAM is attracting much atten-
addition, PCM technology has the potential to provide tion since it is compatible with the conventional semi-
inexpensive, high-speed, high-density, high-volume non- conductor processes. Memristor-based RRAM is one of
volatile storage on an unprecedented scale. The physical the most promising emerging memory technologies and
structure is three-dimensional, maximizing the number has the potential of being a universal memory technol-
of transistors that can exist in a chip of fixed size. PCM ogy [111]. It offers the potential for a cheap, simple
is sometimes called perfect RAM because data can be memory that could compete across the whole spectrum
overwritten without having to erase it first. Possible of digital memories, from low-cost, low-performance ap-
problems facing PCRAM concern the high current dens- plications up to universal memories capable of replacing
ity needed to erase the memory; however, as cell sizes all current market-leading technologies, such as hard
decrease, the current needed will also decrease. PCM disk drives, random-access memories, and Flash memor-
chips are expected to last several times as long as cur- ies [112]. RRAM is a simple, two-terminal metal-
rently available Flash memory chips and may prove insulator-metal (MIM) bistable device as shown in the
cheaper for mass production. Working prototypes of basic configuration in Figure 17. It can exist in two dis-
PCM chips have been tested by IBM, Infineon, Samsung, tinct conductivity states, with each state being induced
Macronix, and others. Also, the production of PCM has by applying different voltages across the device termi-
been announced recently by both collaborations between nals. RRAM uses materials that can be switched between
Intel and STMicroelectronics as well as with Samsung two or more distinct resistance states. Many companies
[109,110]. are investing metal oxide nanolayers switched by voltage
pulses. Researchers generally think that the pulses' elec-
Comparison of primary contenders for MRAM, STT-RAM, tric fields produce conducting filaments through the in-
FeRAM, and PCM technologies sulating oxide. HP Labs plans to release prototype chips
Before going to other emerging memories, we herein pro- this year based on ‘memristors’ in which migrating oxygen
vide a comparison among MRAM, FeRAM, and PCM. atoms change resistance [113]. Xu et al. have also defined
The specific features of these memory devices are pro- that among all the technology candidates, RRAM is con-
vided in Table 2. Relatively mature, new-material memor- sidered to be the most promising as it operates faster than
ies such as MRAM, STT-RAM, FeRAM, and PCM can PCRAM and it has a simpler and smaller cell structure
offer a variety of features that have potential to be the can- than magnetic memories (e.g., MRAM or STT-RAM)
didates for next-generation nonvolatile memory devices. [114]. In contrast to a conventional MOS-accessed
Table 2 Summary of primary contenders for MRAM, FeRAM, STT-RAM, and PCM technologies
Features FeRAM MRAM STT-RAM PCM
Cell size (F2) Large, approximately 40 to 20 Large, approximately 25 Small, approximately 6 to 20 Small, approximately 8
Storage mechanism Permanent polarization of a Permanent magnetization Spin-polarized current applies Amorphous/polycrystal
ferroelectric material (PZT or SBT) of a ferromagnetic material torque on the magnetic moment phases of chalcogenide alloy
in a MTJ
Read time (ns) 20 to 80 3 to 20 2 to 20 20 to 50
Write/erase time (ns) 50/50 3 to 20 2 to 20 20/30
Endurance 1012 >1015 >1016 1012
Write power Mid Mid to high Low Low
Nonvolatility Yes Yes Yes Yes
Maturity Limited production Test chips Test chips Test chips
Applications Low density Low density High density High density
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measured at high temperatures and a memory endurance

of over 106 cycles [126]. Therefore, a statistical study of re-
liability, availability, and maintainability is essential for the
future development of RRAM.

Polymer memory
Throughout the last few years, polymers have found
growing interest as a result of the rise of a new class of
nonvolatile memories. In a polymer memory, a layer
consists of molecules and/or nanoparticles in an organic
polymer matrix is sandwiched between an array of top
and bottom electrodes as illustrated in Figure 18. More-
over, polymer memory has the advantage of a simple
Figure 17 Basic RRAM cell structure. A schematic diagram of the fabrication process and good controllability of materials
mechanism of the resistive switching in a metal/oxide/metal-structured [127]. Polymer memory could be called digital memory
memory cell is also shown. Reproduced from ref. [123]. with the latest technology. It is not possible for a silicon-
based memory to be established in less space, but it is
memory cell, a memristor-based RRAM has the potential possible for polymer memory. Ling et al. explained that
of forming a cross-point structure without using access polymer materials have simplicity in structure, free read
devices, achieving an ultra-high density. This device is and write capability, better scalability, 3-D stacking abil-
based on the bistable resistance state found for almost any ity, low-cost potential, and huge capacity of data storage
oxide material, including NiO, ZrO2, HfO2, SrZrO3, and [128]. They revealed that a polymer memory stores in-
BaTiO3 [115-119]. Currently, Samsung and IBM are ac- formation in a manner that is entirely different from that
tively investigating RRAM. of silicon-based memory devices. Rather than encoding
Kamiya et al. have revealed by a theoretical mechanism ‘0’ and ‘1’ from the number of charges stored in a cell, a
that RRAM shows filamentary-type resistive switching, polymer memory stores data on the basis of high and
where the oxygen vacancy is considered to form con- low conductivity while responding to an applied voltage.
ductive filaments in the resistive material as shown in Among the large number of emerging memory tech-
Figure 17 [120]. The formation and disruption of these nologies, polymer memory is the leading technology. It
filaments are thus the mechanisms responsible for the is mainly because of its expansion capability in 3-D
ON-OFF switching in RRAM devices. The key issue is, space [129] since most polymers are organic materials
therefore, to reveal electronic roles in the formation and consisting of long chains of single molecules. Prior to
disruption of the vacancy filaments. RRAM can be polymer memory fabrication, deposition of an organic
switched between the low resistance state (LRS) and the layer is usually done by the sol-gel spin coating tech-
high resistance state (HRS) of the resistive material by nique. All the other necessary constituent materials are
applying voltages to the electrodes. Lee has explained dissolved in a solvent which is then spin-coated over a
that during the SET process, the current level increases substrate. When the solvent is evaporated, a thin film of
from HRS to LRS as the voltage increases from 0 V to material with 10- to 100-nm thickness is successfully de-
the critical point which is called the set voltage (V set), posited at bottom electrodes. Top electrodes are depos-
while the current level abruptly decreases from LRS to ited as the final step. The conductivity of the organic
HRS at the reset voltage (V reset) under the RESET
process. The SET and RESET processes are repeatedly
carried out by sweeping the gate voltage with the binary
states LRS and HRS [121]. Wang and Tseng and Lin
et al. have indicated that the interface plays an important
role in enhancing the performances of RRAM [122,123].
Recently, Goux et al. have explained that using a stacked
RRAM structure has been shown to be one of the most
promising methods to improve the memory characteris-
tics [124]. Although being a most promising memory
element, critical issues for the future development of
RRAM devices are reliable, such as data retention and
memory endurance [125]. A data retention time of over
Figure 18 Structure of a polymer memory device.
10 years can be extrapolated from retention characteristics
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layer is then changed by applying a voltage across the depending on the direction of the current. A separate
memory cell, allowing bits of data to be stored in the nanowire perpendicular to the U-shaped ‘racetrack’
polymer memory cell. When the polymer memory cell writes data by changing the polarity of the magnetic re-
becomes electrically conductive, the electrons are intro- gions. A second device at the base of the track reads the
duced and removed. Even the polymer is considered as a data. Data can be written and read in less than a nano-
‘smart’ material to the extent that functionality is built second. A racetrack memory using hundreds of millions
into the material itself of switchability and charge store. of nanowires would have the potential to store vast
This will open up tremendous opportunities in the elec- amounts of data [133,134]. In this way, the memory re-
tronics world, where tailor-made memory materials rep- quires no mechanical moving of parts and it has a
resent an unknown territory. The nonvolatileness and greater reliability and higher performance than HDDs,
other features are inbuilt at the molecular level and of- with theoretical nanosecond operating speeds. For a de-
fers very high advantages in terms of cost. But turning vice configuration where data storage wires are fabricated
polymer memory into a commercial product would not in rows on the substrate, conventional manufacturing
be easy. Memory technologies compete not only on stor- techniques are adequate. However, for the maximum pos-
age capacity but on speed, energy consumption, and reli- sible memory density, the storage wires are proposed to
ability. ‘The difficulty is in meeting all the requirements be configured rising from the substrate in a ‘U’ shape, giv-
of current silicon memory chips,’ says Thomas, the Dir- ing rise to a 3-D forest of nanowires. While this layout
ector of Physical Sciences at IBM's Watson Research does allow high data storage densities, it also has the dis-
Center in Yorktown Heights, NY. They are likely to be advantage of complex fabrication methods, with so far,
limited to niche applications [130]. only 3-bit operation of the devices demonstrated [133]. As
the access time of the data is also dependent on the
Racetrack memory position of the data on the wire, these would also be
In a racetrack memory, information is stored on a U- performance losses if long wires are used to increase
shaped nanowire as a pattern of magnetic regions with the storage density further. The speed of operation of
different polarities. The U-shaped magnetic nanowire is the devices has also been an issue during development,
an array of keys, which are arranged vertically like trees with much slower movement of the magnetic domains
in a forest as shown in Figure 19. Achieving capacities than originally predicted. This has been attributed to
comparable to vertical RM or hard drives would require crystal imperfections in the permalloy wire, which in-
stacks of these arrays. The nanowires have regions with hibit the movement of the magnetic domains. By elim-
different magnetic polarities, and the boundaries be- inating these imperfections, a data movement speed of
tween the regions represent 1 or 0 s, depending on the 110 m/s has been demonstrated [133].
polarities of the regions on either side [131,132]. The
magnetic information itself is then pushed along the
wire, past the write and read heads by applying voltage Other new memory technologies
pulses to the wire ends. The magnetic pattern to speed Researchers are already working hard on several emer-
along the nanowire, while applying a spin-polarized ging technologies, as discussed in previous sections, to
current, causes the data to be moved in either direction, pursue storage-class memories with a more traditional

Figure 19 Racetrack memory diagram showing an array of U-shaped magnetic nanowires. The nanowires are arranged vertically like trees
in a forest and a pair of tiny devices that read and write the data. Adopted from IBM.
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design than that of the racetrack memory, which places removed some of the constraints of the shape and num-
the bits in horizontal arrays. ber of layers of the molecule sheets which intend to con-
vey that two of the biggest barriers are taken away.
Molecular memory Thus, molecular memory requires strong attention to
A molecular memory is a nonvolatile data storage mem- work over such issues and needs immediate amendment
ory technology that uses molecular species as the data to see the possibility of a universal memory in the
storage element, rather than, e.g., circuits, magnetics, in- future.
organic materials, or physical shapes [135]. In a molecu-
lar memory, a monolayer of molecules is sandwiched MNW
between a cross-point array of top and bottom elec- In the last two decades, an increasing interest is ob-
trodes as shown in Figure 20. The molecules are packed served for electronics-related devices and the search for
in a highly ordered way, with one end of the molecule a universal memory data storage device that combines
electrically connected to the bottom electrode and the rapid read and write speeds, high storage density, and
other end of the molecule connected to the top elec- nonvolatility is driving the investigation of new materials
trode, and this molecular component is described as a in the nanostructured form [140]. As an alternative to
molecular switch [136]. Langmuir-Blodgett (LB) depos- the current Flash memory technology, a novel transistor
ition is ideally suited for depositing the molecular layer for architecture using molecular-scale nanowire memory
the fabrication of molecular memory devices [137,138]. cells holds the promise of unprecedently compact data
Then, regarding the molecular memory operation, by ap- storage. The molecular nanowire array (MNW) memory
plying a voltage between the electrodes, the conductivity is fundamentally different from other semiconductor
of the molecules is altered, enabling data to be stored in a memories; information storage is achieved through the
nonvolatile way. This process can then be reversed, and channel of a nanowire transistor that is functionalized
the data can be erased by applying a voltage to the oppos- with redox-active molecules rather than through ma-
ite polarity of the memory cell. The increasing demand for nipulation of small amounts of charge. It is relatively
nonvolatile electronic memories will grow rapidly in order slow and lacks the random access capability, wherein
to keep pace with the requirements for subsystems in- data that can be randomly read and written at every byte
volved in flight demonstration projects and deep space op- are being actively pursued. Figure 21 shows the sche-
erations. At the same time, mass, volume, and power matic design of a MNW memory cell. Lieber, and Agar-
must be minimized for mission affordability concerning wal and Lieber have revealed that the nanowire-based
these requirements; molecular memory could be a very memory technology is a powerful approach to assemble
promising candidate to fill this need. electronic/photonic devices at ultra-small scales owing to
Recently, Plafke has revealed clearly via an article that their sub-lithographic size, defect-free single-crystalline
like most experimental technology that sounds so amaz- structure, and unique geometry [141,142]. Nanowires syn-
ing that we want it right now, the molecular memory thesized by chemical or physical processes are nearly per-
cell does not provide enough power for a commercial fect single-crystal structures with a small geometry and
device [139]. This is currently only able to produce a perfect surface. The channel of a nanowire transistor is
20% jump in conductivity. However, the area of molecu- functionalized with redox-active molecules. During pro-
lar switching memory is promising, having eliminated gramming, control of the voltage acting on the substrate
the need for near-absolute zero temperatures and is possible to change the oxidation and reduction states of

Figure 20 Cell structure of a molecular memory device. Figure 21 A MNW memory cell structure.
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the active molecules. Finally, by measurement of the con- SNW memory shows high mobility, less power dissipation,
ductance of the nanowire with the gate bias fixed at 0 V and high performance. Moreover, being 3-D-stacked, the
or a small voltage and from the hysteresis, the two states SNW memory enhances cell density and data capacity
can be defined as a high-conductance ON state and a low- without relying on advances in process technology. The
conductance OFF state. The MNW memory has advan- nanowire-based memory device can store data electrically
tages of low power dissipation, ultra-high density, simple and is nonvolatile, meaning it retains data when the power
fabrication process, 3-D structure, and multilevel storage, is turned off, like the silicon-based Flash memory found in
and it functions at the nanoscale with a few electrons but smart phones and memory cards [148], with minimal in-
limited by low retention time parameter [143,144]. More- crease in chip size. In addition, the SNW device exhibits re-
over, the deposition of metals onto a monolayer of mo- liable write/read/erase operations with a large memory
lecular wires can lead to low device yield, and this window and high on-to-off current ratio, which are highly
problem remains a major challenge [145]. However, men- advantageous for applications in nonvolatile memory [149].
tioning the term emerging class memory, it could be ex- The SNW memory cannot hold data as long as the existing
pected that the MNW memory represents an important Flash, but it is slower and has fewer rewrite cycles and it
step towards the creation of molecular computers that are could potentially be made smaller and packed together
much smaller and could be more powerful than today's more densely. And its main advantage is that it can be
silicon-based computers. made using simple processes at room temperature, which
means that it can be deposited even on top of flexible plas-
SNW tic substrates [150]. The SNW could, for instance, be built
Semiconductor memory is essential for information pro- into a flexible display and could be packed into smaller
cessing as a key part of silicon technology; semicon- spaces inside cell phones, MP3 players, plastic RFID tags,
ductor memory has been continuously scaled to achieve and credit cards.
a higher density and better performance in accordance
with Moore's law [146]. Flash memory may reach funda- NRAM
mental scaling limits, however, because a thick tunneling NRAM is a carbon nanotube (CNT)-based memory,
oxide is required to prevent charge leakage and achieve which works on a nanomechanical principle, rather than
10 years' retention. As Flash memory approaches its scal- a change in material properties [151]. NRAM uses car-
ing limit, several alternative strategies have been proposed bon nanotubes for the bit cells, and the 0 or 1 is deter-
to extend or replace the current Flash memory technology mined by the tube's physical state: up with high
[147]. These approaches are revolutionary, but major chal- resistance, or down and grounded. NRAM is expected
lenges must be overcome to achieve small memory size and to be faster and denser than DRAM and also very scal-
aggressive technology design architecture. In addition to able, able to handle 5-nm bit cells whenever CMOS fab-
the engineering of trapping layers, the device performance rication advances to that level. It is also very stable in its
can also be improved by using innovative nonplanar chan- 0 or 1 state. Produced by Nantero, these memories con-
nel geometries. Among the various nanostructure materials, sist of the structure shown in Figure 23a with an array
semiconductor nanowire memory (SNW) has induced of bottom electrodes covered by a thin insulating spacer
great scientific interest as possible building blocks for future layer [152]. CNTs are then deposited on the spacer layer,
nanoelectronic circuitry. In a SNW memory device, nano- leaving them freestanding above the bottom electrodes.
wires are integrated with SONOS technology. The basic Unwanted CNTs are removed from the areas around the
schematic design of SNW is depicted in Figure 22. The electrode, with top contacts and interconnects deposited
on top of the patterned CNT layer. During the time that
the CNTs are freestanding, there is no conduction path
between the bottom and top electrodes and hence the
memory cell is in the OFF state. However, if a large
enough voltage is applied over the cell, the nanotubes
are attracted to the bottom electrode where they are
held in place by van der Waals forces [153]. Due to the
conductive nature of the CNTs, the electrodes are now
connected and the cell reads the low conductivity ON
state as shown in Figure 23b. The OFF state can be
returned by repelling the nanotubes with the opposite
electrode polarity. Nonvolatility is achieved due to the
Figure 22 A bottom-gate FET-based nonvolatile SNW
strength of the van der Waals forces overcoming the
memory device.
mechanical strain of the bent nanotubes, hence holding
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Figure 23 NRAM structure with (a) OFF state and (b) ON state.

the cell in the ON state. NRAM offers the possibility of stamp-sized surface and could enable 10 GB of storage
a simple cell architecture, which could operate at much capacity on a cell phone. Millipede uses thousands of
higher speeds than the conventional Flash and with low tiny sharp points (hence the name) to punch holes in a
power use. Cui et al. reported CNT memory devices thin plastic film. Each of the 10-nm holes represents a
exhibiting an extraordinarily high charge storage stability single bit. The pattern of indentations is a digitized ver-
of more than 12 days at room temperature [154]. How- sion of the data. The layout of the millipede cantilever/
ever, as NRAM is based on CNTs, it suffers from fabrica- tip in contact with the data storage medium is shown in
tion problems that are inherent in carbon nanotube-based Figure 24. According to IBM, Millipede can be thought
devices. The issues include the cost and fabrication com- of as a nanotechnology version of the punch card data
plexity of producing the CNTs, ensuring uniform disper-
sions of nanotubes, and difficulties in removing nanotubes
from the unwanted positions on the substrate.

Millipede memory
In 2002, IBM developed a punch card system known as
Millipede, which is a nonvolatile computer memory
stored in a thin polymer sheet with nanoscopic holes to
provide a simple way to store binary data [155]. It can
store hundreds of gigabytes of data per square centi-
meter. However, the polymer reverts to its pre-punched
form over time, losing data in the process. Millipede
storage technology is being pursued as a potential re-
placement for magnetic recording in hard drives, at the
same time reducing the form factor to that of Flash
Figure 24 Schematic layout of the millipede cantilever/tip in
media. The prototype's capacity would enable the stor-
contact with the data storage medium. Adopted from ref. [157].
age of 25 DVDs or 25 million pages of text on a postage
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processing technology developed in the late nineteenth readies the system for data encoding. For some particu-
century [156]. However, there are significant differences: lar instance, the team has found that using DNA may
Millipede is rewritable, and it may eventually enable be less expensive to process into storage devices than
storage of over 1.5 GB of data in a space no larger than using traditional, inorganic materials like silicon, the re-
a single hole in the punch card. Storage devices based searchers say [161,162]. They said that when no voltage
on IBM's technology can be made with existing manu- or low voltage is applied through the electrodes to the
facturing techniques, so they will not be expensive to UV-irradiated DNA, only a low current is able to pass
make. According to P. Vettiger, head of the Millipede through the composite; this corresponds to the ‘OFF’
project, there is not a single step in fabrication that state of the device. But the UV irradiation makes the
needs to be invented. Vettiger predicts that a nanosto- composite unable to hold a charge under a high electric
rage device based on IBM's technology could be avail- field, so when the applied voltage exceeds a certain
able as early as 2005 [155]. Now, researchers at IBM's threshold, an increased amount of charge is able to pass
Zurich Research Laboratory in Switzerland have clocked through. This higher state of conductivity corresponds
the rate of data loss. They have calculated that at 85°C, a to the ‘ON’ state of the device. The team found that this
temperature often used to assess data retention, it would change from low conductivity (‘OFF’) to high conduct-
lose just 10% to 20% of information over a decade, com- ivity (‘ON’) was irreversible: once the system had been
parable to Flash memory [157]. turned on, it stayed on, no matter what voltage the
team applied to the system. Once information is writ-
WORM memory based on DNA biopolymer nanocomposite ten, the device appears to retain that information indef-
The use of DNA is well known as a good model for initely. The researchers hope that the technique will be
metal NP synthesis due to its affinity to the metal ions useful in the design of optical storage devices and sug-
[158]. In recent years, DNA has also been shown to be a gest that it may have plasmonic applications as well.
promising optical material with the material processing Consequently, WORM memories based on DNA a bio-
fully compatible with conventional polymer for thin-film polymer nanocomposite have emerged as an excellent
optoelectronic applications [159,160]. Researchers from candidate for next-generation information storage media
National Tsing Hua University in Taiwan and the Karlsruhe because of their potential application in flexible memory
Institute of Technology in Germany have created a devices. This work combines new advances in DNA nano-
DNA-based memory device, that is, write-once-read- technology with a conventional polymer fabrication plat-
many-times (WORM), that uses ultraviolet (UV) light form to realize a new emerging class of DNA-based
to encode information [161]. The device consists of a single memory.
biopolymer layer sandwiched between electrodes, in
which electrical bistability is activated by in situ formation QD memory
of silver nanoparticles embedded in a biopolymer upon Memory made from tiny islands of semiconductors -
light irradiation (Figure 25). The device functionally known as quantum dots - could fill a gap left by today's
works when shining UV light on the system, which en- computer memory, allowing storage that is fast as well
ables a light-triggered synthesis process that causes the as long lasting. Researchers have shown that they can
silver atoms to cluster into nanosized particles and write information into quantum dot memory in just nano-
seconds. Memory is divided into two forms: DRRAM and
Flash [163,164]. Computers use DRAM, for short-term
memory, but data does not persist for long and must be
refreshed over 100 times per second to maintain its mem-
ory. On the other hand, Flash memory, like that used in
memory cards, can store data for years without refreshing
but writes information about 1,000 times slower than
DRAM. New research shows that memory based on
quantum dots can provide the best of both: long-term
storage with write speeds nearly as fast as DRAM. A
tightly packed array of tiny islands, each around 15 nm
across, could store 1 terabyte (1,000 GB) of data per
square inch, the researchers say. Dieter Bimberg and col-
Figure 25 Schematic design of a memory device consisting of a leagues at the Technical University of Berlin, Germany,
thin DNA biopolymer film sandwiched between electrodes. The with collaborators at Istanbul University, Turkey, demon-
memory switching effect is activated upon light irradiation. Adopted
strated that it is possible to write information to the
from ref. [161].
quantum dots in just 6 ns [165,166]. The key advantages
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of quantum dot (QD) NVMs are the high read/write technology has brought to high volume an NVM where
speed, small size, low operating voltage, and, most import- arrays of memory cells are stacked above control logic
antly, multibit storage per device. However, these features circuitry in the third dimension, and stacking 3-D mem-
have not been realized due to variations in dot size and ory directly over CMOS allows for high array efficiency
lack of uniform insulator cladding layers on the dots and very small die size [172]. The 3-D technology uses
[167]. Incorporating QDs into the floating gate results in a no new materials, processes, or fabrication equipment,
reduction in charge leakage and power dissipation with which control logic circuitry composed of typical CMOS.
enhanced programming speed. Researchers in India and The memory construction uses typical back-end process-
Germany have now unveiled the memory characteristics ing tools, and each memory layer is a repeat of the layers
of silicon and silicon-germanium QDs embedded in epi- below it. The basic design of the 3-D cell consists of a ver-
taxial rare-earth oxide gadolinium oxide (Gd2O3) grown tical diode in series with a memory element as shown in
on Si (111) substrates as shown in the DQM structure in Figure 27. Building integrated circuits vertically allows for
Figure 26. Multilayer Si as well as single-layer Si1 − xGex a reduced chip footprint when compared to a traditional
(where x = 0.6) QDs show excellent memory characteris- 2-D design, by an approximate factor of the number of
tics, making them attractive for next-generation Flash- layers used. This offers significant advantages in terms of
floating-gate memory devices [168,169]. reduced interconnect delay when routing to blocks that
otherwise would have been placed laterally. The process
3-D cross-point memory for the 2-D cross-point array can be built into a multilayer
Memory producers are also trying to develop alternative 3-D architecture. Traditionally, a 3-D integrated circuit
technologies that may be scalable beyond 20-nm lithog- (3-D-IC) has used more than one active device layer.
raphy. For true scalability beyond 20-nm technology While resistance-change memory cells are not active de-
nodes, it is necessary to design a cross-point memory vices, they function as rectifying devices in design. Further
array which does not require diodes for access elements characterization of the resistance-change material is also
[170]. The cross-point memory architecture could be de- necessary in order to guarantee that the 3-D cross-point
signed such that it can be easily fabricated in multiple memory will be practical for data storage. Also, the scal-
layers to form a stacked 3-D memory [171]. The 3-D ability of metal-oxide resistance-change materials beyond
20-nm technology nodes still needs to be studied. More-
over, the programming operation is expected to be com-
petitive with both NAND and NOR Flash in terms of
speed because of the relatively low voltage requirements
of resistance-change materials. If the peripheral circuitry
for accommodating the write operation can be made suffi-
ciently compact, then the 3-D cross-point memory will in-
deed be a viable replacement for NAND and NOR Flash
in future process generations.

TFM
Transparent and flexible electronics (TFE) is, today, one
of the most advanced topics for a wide range of device
applications, where the key component is transparent
conducting oxides (TCOs), which are unique materials
that oxides of different origin play an important role, not
only as a passive component but also as an active com-
ponent [173]. TFE is an emerging technology that em-
ploys materials (including oxides, nitrides, and carbides)
and a device for the realization of invisible circuits for
implementing next-generation transparent conducting
oxides in an invisible memory generation [174]. In gen-
eral, the TF-RRAM device is based on a capacitor-like
structure (e.g., ITO/transparent resistive material/ITO/
transparent and flexible substrate), which provides trans-
mittance in the visible region [175]. For such new class
Figure 26 Structure of quantum dot memory. Adopted from
of memory technology, data retention is expected to be
ref. [168].
about 10 years. The basic structural design of the new
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Figure 27 The basic design of a 3-D cell that consists of a vertical diode in series. (top) Side view, (bottom right) top view, and (bottom
left) 3-D view.

memory chips is configured, namely with two terminals satisfy the dual requirements of resistance to repeated
per bit of information on a transparent and flexible sub- bending stress and transparent properties. Thus, it is sup-
strate rather than the standard three terminals per bit posed that an achievement of such TF-RRAM device will
on a rigid and opaque substrate (Figure 28). They are be the next step towards the realization of transparent and
much better suited for the next revolution in electronic flexible electronic systems. We hope that FT-RRAM
3-D memory than Flash memory. These new memory
chips that are transparent, are flexible enough to be
folded like a sheet of paper, shrug off 1,000°F tempera-
tures twice as hot as the max in a kitchen oven, and survive
other hostile conditions could usher in the development of
next-generation Flash-competitive memory for tomorrow's
keychain drives, cell phones, and computers, a scientist re-
ported today. Speaking at the 243rd National Meeting and
Exposition of the American Chemical Society, the world's
largest scientific society, he said that devices with these
chips could retain data despite an accidental trip through
the drier or even a voyage to Mars. And with a unique 3-D
internal architecture, the new chips could pack extra giga- Figure 28 A schematic design of FT-RRAM and a flexible,
transparent memory chip image created by researchers at Rice
bytes of data while taking up less space [176]. Despite the
University. Reproduced from Tour Lab/Rice University.
recent progress in TF-RRAM, it needs lots of work to
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devices will mark a milestone in the current progress of MTM, PFRAM, SPBMM, and CMORRAM - future alternate
such unique and invisible electronic systems in the near NVMs
future. Other potential emerging classes of memory technologies,
we are describing in short, are molecular tunnel memory
(MTM), polymeric ferroelectric RAM (PFRAM), spin-
1T1R-RRAM polarized beam magnetic memory (SPBMM), light mem-
One-transistor one-resistor (1T1R)-RRAM is also one ory, and complex metal-oxide RRAM (CMORRAM). We
class of emerging memory technology with impressive can say that these are sister memory technologies of mo-
characteristics. It meets the demands for next-generation lecular memory, ferroelectric/polymer memory, magnetic
memory systems. It is expected that 1T1R-RRAM could memory, and metal-oxide RRAM, respectively. Although
be able to meet the demand of high-speed (e.g., perform- these new technologies will almost certainly result in more
ance) memory technology. The 1T1R structure is chosen complex memory hierarchies than their family memories,
because the transistor isolates current to cells, which are they are likely to allow the construction of memory chips
selected from cells which do not. The basic cell structure that are nonvolatile, have low energy, and have density
of 1T1R is depicted in Figure 29. 1T1R-RRAM consists of and development close to or better than those of DRAM
an access transistor and a resistor as a storage element. chips, with improved performance and allowing memory
Zangeneh and Joshi have also mentioned that the 1T1R systems to continue to scale up.
cell structure is similar to that of a DRAM cell in that the
data is stored as the resistance of the resistor and the tran- Conclusions
sistor serves as an access switch for reading and writing This article reviewed the historical development to the
data [177,178]. In reference to this, they revealed the recent advancement on memory architecture and scaling
1T1R cell as the basic building block of a NVRRAM array trend of several conventional types of Flash within the
as it avoids sneak path problem to ensure reliable oper- MOS family and projected their future trends. With
ation. Moreover, the 1T1R structure is more compact and great progress being made in the emerging memory
may enable vertically stacking memory layers, ideally technologies, current trends and limitations were dis-
suited for mass storage devices. But, in the absence of any cussed before leading to some insight into the next gen-
transistor, the isolation must be provided by a ‘selector’ de- eration of memory products. For the past three and a
vice, such as a diode, in series with the memory element, half decades in existence, the family of semiconductor
or by the memory element itself. Such kinds of isolation memories has expanded greatly and achieved higher
capabilities have been inferior to the use of transistors, densities, higher speeds, lower power, more functional-
limiting the ability to operate very large RRAM arrays in ity, and lower costs. In the past 40 to 50 years, NVSM
1T1R architecture. 1T1R memory polarity can be either has grown from the FG concept to FAMOS, SAMOS,
binary or unary. Bipolar effects cause polarity to reverse Flash memory, multilevel cells, RRAM, 3-D structures,
reset operation to set operation. Unipolar switching leaves and TF-RRAM. Since 1990, NVSM is an inspired tech-
polarity unaffected but uses different voltages. nology, which has ushered in the digital age, enabled the
development of all modern electronic systems, and
brought unprecedented benefit to humankind. At the
same time, some of the limitations within each type of
memory are also becoming more realized. As the device
dimension is reduced to the deca-nanometer regime,
NVSM faces many serious scaling challenges such as the
interface of neighboring cells, reduction of stored
charges, and random telegraph noise. As such, we hope
and are confident that there are several emerging tech-
nologies aiming to go beyond those limitations and poten-
tially replace all or most of the existing semiconductor
memory technologies to become a USM. Despite these
limitations, the field of conventional semiconductor mem-
ories would continue to flourish and memory device sci-
entists will find the way to meet these challenges and may
even develop a ‘unified memory’ with low cost, high per-
formance, and high reliability for future electronic sys-
tems. Progress towards a viable new resistive memory
Figure 29 The basic cell structure of 1T1R-RRAM.
technology relies on fully understanding the mechanisms
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responsible for switching and charge transport, the failure TYT is now a Lifetime Chair Professor in the Department of Electronics
mechanisms, and the factors associated with materials re- Engineering, National Chiao Tung University. He was the Dean of the College
of Engineering and Vice Chancellor of the National Taipei University of
liability. Moreover, the development of current redox- Technology. He received numerous awards, such as the Distinguished
based resistive switching will help to improve our old Research Award from the National Science Council, Academic Award of the
technologies, and further research will produce more im- Ministry of Education, National Endowed Chair Professor, and IEEE CPMT
Outstanding Sustained Technical Contribution Award.
pressive results that will benefit industries and society to
improve the quality of life for billions of people around
Acknowledgements
the world. First of all, the authors would like to thank and gratefully acknowledge all
corresponding publishers for the kind permission to reproduce their figures
Competing interests and related description, used in this review article. This work was supported
The authors declare that they have no competing interests. by the National Science Council, Taiwan, under Project No. NSC 102-2221-E-
009-134-MY3.
Authors' contributions
JSM designed the structure and modified the manuscript. SMS and TYT Received: 5 August 2014 Accepted: 17 September 2014
participated in the sequence alignment and editing the manuscript. UC Published: 25 September 2014
participated in its design and coordination and helped to draft the
manuscript. All authors read and approved the final manuscript.
References
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doi:10.1186/1556-276X-9-526
Cite this article as: Meena et al.: Overview of emerging nonvolatile
memory technologies. Nanoscale Research Letters 2014 9:526.

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