Real Time Hardware Co-simulation of Edge

Detection for Video Processing System

Yahia Said, Taoufik Saidani, Fethi Smach and Mohamed Atri
Laboratory of Electronics and Microelectronics (EμE)
Faculty of Sciences
Monastir, 5000 TUNISIA
E-mail: [email protected]

Abstract—A methodology for implementing real-time DSP presents a study case which is Sobel Edge Detector
applications on a field programmable gate arrays (FPGA) Application. In Section 4, Hardware/Software Co-Design in
using Xilinx System Generator (XSG) for Matlab is presented System Generator and experimental results are detailed.
in this paper. Section 5 shows some discussion and comparison .This
It presents architecture for Edge Detection using Sobel Filter
paper is concluded in Section 6.
for image processing using Xilinx System Generator. The
design was implemented targeting a Spartan3A DSP 3400 II. SYSTEM GENERATOR DESIGN FLOW FOR
device (XC3SD3400A-4FGG676C) then a Virtex 5 (xc5vlx50-
IMPLEMENTATION ON FPGA
1ff676). The Edge Detection method has been verified
successfully with no visually perceptual errors in the resulted The algorithms and concepts used to define the system
images. are modeled using high level software languages like
Matlab, Simulink and C. The Xilinx’s System Generator for
DSP is a new tool, which comes with a predefined block set
I. INTRODUCTION along with Matlab Simulink software packet and can be
used to implement the algorithms [1]. These high level
The emerging market for video processing systems languages can also be used to verify the accuracy of the
requires high-performance digital signal processing as well algorithms.
as low device costs appropriate for a volume application. Matlab is a high-level technical computing language and
Xilinx FPGA devices provide a platform with which to meet interactive environment for algorithm development, data
these two contrasting requirements. visualization, data analysis, and numeric computation [4]. In
A Xilinx tool, the System Generator for DSP [1], offers addition to the intellectual property functions provided in
an efficient and straightforward method for transitioning Matlab, the software packet is uniquely adept with vector-
from a PC-based model in Simulink to a real-time FPGA and array based waveform data at the core of algorithms,
based hardware implementation. which is suitable for applications such as image and video
The system model can be simulated in the Simulink processing.
environment. This higher abstraction level reduces the Matlab-Simulink is an environment for multidomain
analysis and debugging time. For real hardware testing, simulation and Model-Based Design for dynamic and
Xilinx System Generator supports the possibility to perform embedded systems. It provides an interactive graphical
hardware in-the-loop co-simulation [2]. environment, event-driven simulator, and extensive library
This methodology provides easier hardware verification of parameterizable functions that allow design, simulate,
and implementation compared to HDL based approach. The implement, and test a variety of time-varying systems,
Simulink simulation and hardware-in-the loop approach including communications, controls, signal processing,
presents a far more cost efficient solution than other image and video processing [4]. Matlab-Simulink is used in
methodologies. The ability to quickly and directly realize a this application as the high level development tool in the
control system design as a real-time embedded system design process.
greatly facilitates the design process [3]. Xilinx System Generator [1], is a system-level modeling
The goal of this project was to implement an image- tool from Xilinx that facilitates FPGA hardware design. It
processing algorithm applicable to Edge Detection system in extends Simulink in many ways to provide a modeling
a Xilinx FPGA using System Generator for DSP, with a environment well suited for hardware design. The software
focus on achieving overall high performance, low cost and automatically converts the high level system DSP block
short development time. diagram to RTL. The result can be synthesized to Xilinx
The remainder of this paper is divided into five sections. FPGA technology using ISE tools. All of the downstream
After introducing, a description of System Generator design FPGA implementation steps including synthesis and place
flow for implementation on FPGA is presented, section 3

978-1-4673-0784-0/12/$31.00 ©2012 IEEE 852

and route are automatically performed to generate an FPGA order derivative methods. First order derivative based
programming file. techniques depend on computing the gradient several
“Fig. 1” presents the design flow of XSG. System directions and combining the result of each gradient. The
Generator automates the design process, debugs, value of the gradient magnitude and orientation is estimated
implements and verifies the Xilinx-based FPGAs. using two differentiation masks [6].
It provides a high-speed HDL co-simulation interface, The Sobel edge detection algorithm uses a 3 x 3 table of
system-level resource estimation, and accelerated simulation pixels to store a pixel and its neighbors while calculating the
through hardware in the loop co-simulation interfaces which derivatives. The 3 x 3 table of pixels is called a convolution
give up to a 1000x simulation performance increase [8]. table, because it moves across the image in a convolution-
It also provides a system integration platform for the style algorithm.
design of DSP FPGAs that allows the RTL, Simulink, For a given image I, horizontal and vertical gradient of
MATLAB and C/C++ components of a DSP system to come each pixel (x, y), are calculated as shown in “(1)” and “(2)”.
together in a single simulation and implementation
environment. System Generator supports a black box block 1 0 1
that allows RTL to be imported into Simulink and co- G x, y 2 0 2 I x, y (1)
simulated with either ModelSim or Xilinx ISE Simulator. 1 0 1

1 2 1
G x, y 0 0 0 I , (2)
1 2 1

In each pixel (x,y), the approximations of the horizontal and

vertical gradients are combined as follows, to obtain an
approximation of the gradient value:

G x, y G x, y G x, y (3)

Typically, an approximate magnitude is computed using:

G x, y |G x, y | G x, y (4)

The orientation of gradient is calculated as follows:

G ,
θ x, y Arctan (5)
G ,

The reason for using Sobel operator is that it is

insensitive to noise and it has relatively small masks than
other operator such as Robert operator, two-order Laplacian
operator and others [7]. It is the one of the simplest
Figure 1: System Generator design flow [3] operators which gives however corrects results.
IV. HARDWARE/SOFTWARE CO-SIMULATION IN
III. STUDY CASE: SOBEL EDGE DETECTOR SYSTEM GENERATOR
Edge detection is a fundamental tool used in most image Sometimes it is important to add one or more existing
processing applications to obtain information from the HDL modules to a System Generator design. The System
frames as a precursor step to feature extraction and object Generator Black Box block allows VHDL, Verilog, and
segmentation. This process detects outlines of an object and EDIF to be brought into a design. The Black Box block
boundaries between objects and the background in the behaves like other System Generator blocks – it is wired
image. An edge-detection filter can also be used to improve into the design, participates in simulations, and is compiled
the appearance of blurred or anti-aliased video streams [5]. into hardware. When System Generator compiles a Black
Commonly used method for detecting edges is to apply Box block, it automatically wires the imported module and
derivative operators on images. Derivative based approaches associated files into the surrounding netlist [1].
can be categorized into two groups, namely first and second

853
 The Black Box block provides a way to incorporate System Generator provides a generic interface that uses
hardware description language (HDL) models into System JTAG and a Xilinx programming cable (e.g., Parallel Cable
Generator. IV or Platform Cable USB) to communicate with FPGA
The design of our architecture with Xilinx System hardware. “Fig. 4” shows the model with the JTAG-based
Generator is shown in “Fig. 2”.The Black Box contains our hardware co-simulation block implemented on Virtex 5
defined VHDL description for sobel operator. The platform.
subsystems in the simulation model allow serialization and Point-to-point Ethernet co-simulation provides a
the reconstruction of the image when the pixel output is straightforward high-performance co-simulation
generated by the hardware model. environment using a direct, point-to-point Ethernet
connection between a PC and FPGA platform.
The target FPGA chip is Xilinx Spartan 3A DSP 3400
In
Step RST

R uint 8 In1 Out1 In

XC3SD3400A-4FGG676C and Virtex 5 xc5vlx50-1ff676.
Data Type
Conversion Subsystem
Red
RST The optimization setting is for maximum clock speed.
Table 1 details the resource requirements of the design.
red
lena .jpg G uint 8 In1 Out1 In Note that in practice, additional blocks are needed for
Green o_Y Out In1
Data Type
Conversion 1 Subsystem1
green
o_Y

Y2
input/output interfaces, and synchronization.
“Fig. 5” shows the software and hardware simulation for the
B uint 8

Data Type
In1 Out1 In
Blue
blue Sobel Edge Detection design for the input image.
Conversion 2 Subsystem2
Black Box
ModelSim

Image From File

ModelSim

System
Generator

Figure 2: System Generator project for simulation R uint 8

Data Type
In1 Out1 In
Red

Conversion Subsystem
Blue

System Generator simulates black boxes by automatically

launching an HDL simulator, generating additional HDL as lena .jpg G uint 8

Data Type
In1 Out1 In
Green
Green
JTAG
o_Y1 Out In1

needed (analogous to an HDL testbench), compiling HDL,

Conversion 1 Subsystem1
Co-sim o_Y

Red Y2

scheduling simulation events, and handling the exchange of B uint 8 In1 Out1 In

data between the Simulink and the HDL simulator. This is Data Type
Conversion 2 Subsystem2
Blue
RST

called HDL co-simulation. Image From File

Step
In
RST
sg Black Box hw Co-sim

System Generator provides hardware co-simulation,

making it possible to incorporate a design running in an System
Generator

FPGA directly into a Simulink simulation. "Hardware Co- Figure 4: System Generator project for hardware-in-the-loop testing on
Simulation" compilation targets automatically create a Virtex 5 Platform
bitstream and associate it to a block. (“Fig. 3”)
When the system design is simulated in Simulink, results
for the compiled portion are calculated in actual FPGA
hardware, often resulting in significantly faster simulation
times while verifying the functional correctness of the
hardware. System Generator for DSP supports Ethernet as
well as JTAG communication between a hardware platform
and Simulink.

Figure 3: FPGA based Hardware-Software (HW-SW) co- simulation

environment [1] Figure 5: Outputs from different implementation

854
 Table 1: FPGA RESOURCES USED IN THE IMPLEMENTATION FOR THE SOBEL EDGE DETECTOR
Spartan 3A DSP 3400 Virtex 5 xc5vlx50-1ff676
Used Available % Used Available %
Number of Slice Registers 2302 23872 9% 1798 28800 6%
Number of Slice LUTs 1755 47744 3% 2299 28800 7%
Number of LUT-FF pairs 3023 47744 6% 370 3727 9%
Number of bonded IOBs 34 469 7% 34 440 7%
Number of BUFG/BUFGCT 1 24 4% 1 32 3%
Number of DSP48s 3 126 2% - - -
Maximum Frequency 59.552 MHz 103.616 MHz
Table 2: PERFORMANCE COMPARISON
Our Design Design [9]
Used Available % Used Available %
Number of Slices 177 768 23 % 204 768 26 %
Number of Slice Flip Flop 401 1536 26 % 280 1536 18 %
Number of 4 input LUTs 277 1536 18 % 202 1536 13%
Number of bonded IOBs 34 124 27 % 81 124 65 %
Number of GCLKS 1 8 12 % 1 8 12 %
Maximum Frequency 54.505 MHz 134.756MHz

V. DISCUSSON
To provide a proper performance evaluation, the frequency and uses 177 CLB slices with 23% utilization, so
implemented Sobel Edge Detector architecture using low there is possibility of implementing some more parallel
cost available Spartan 3 development system with Xilinx processes with this architecture on the same FPGA.
chip XC3S50 -5PQ208. The properties of other designs Future works include the use of the Xilinx System
along with ours are listed in Table 2. As seen from this Generator development tools for the implementation of
table, the design of the Sobel Edge Detector proposed by [9] other blocks used in computer vision like feature extraction
requires 204 CLB on the basis clock rate of 134.756 MHz. and object detection on Xilinx Programmable Gate Arrays
On the other hand, our resulting architecture spent about (FPGA).
177 CLB with a working frequency up to 54.505 MHz.
Obviously, our proposed architecture has lower complexity REFERENCES
and improved efficiency in area, thus providing a good [1] Xilinx System Generator User's Guide,www.xilinx.com
choice in terms of low-cost hardware. [2] K.Van Beeck, F.Heylen, J.Meel, T.Goedemé, “Comparative study of
Xilinx system generator is a very useful tool for Model-based hardware design tools”, In proceedings of European
Conference on the Use of Moder Electronics in ICT, ECUMICT 2010,
developing computer vision algorithms. It could be Ghent, Belgium, 25-26 March, 2010
described as a timely, advantageous option for developing in [3] T. Saidani, D. Dia, W. Elhamzi, M. Atri and R. Tourki, “Hardware
a much more comfortable way than that permitted by VHDL Co-simulation For Video Processing Using Xilinx System Generator”
or Verilog hardware description languages (HDLs). Proceedings of the World Congress on Engineering 2009 Vol I,WCE
2009, July 1 - 3, 2009, London, U.K.
[4] http://www.mathworks.com/
VI. CONCLUSION [5] H. Neoh, A. Hazanchuk, “Adaptive Edge Detection for Real-Time
Xilinx system generator has a unique hardware in the loop Video Processing using FPGAs”, Global Signal Processing (2004)
co-simulation feature that allows designers to greatly [6] SHIGERU.A, “Consistent Gradient Operators”, IEEE Transactions
on Pattern Analysis and Machine Intelligence, 22 (3), 2000.
accelerate simulation while simultaneously verifying the [7] Dong, Q., Song, C., Ben, C., Quan, L., “A fast subpixel edge
design in hardware. detection method using Sobel-Zernike moments operator”, Image and
The purpose of this paper was to demonstrate the use of Vision Computing, Vol.23, pp.11-17, 2005.
[8] S. Mittal, S. Gupta, and S. Dasgupta, “System Generator: The State-
System Generator to design a system Edge Detection for
Of-Art FPGA Design Tool For DSP Applications”, Third
image processing. This design is implemented in the device International Innovative Conference On Embedded Systems, Mobile
Spartan 3A DSP 3400 (XC3SD3400A-4FGG676C) and Communication And Computing (ICEMC2 2008), August 11-14,
Virtex 5 (xc5vlx50-1ff676). 2008, Global Education Center, Infosys.
[9] T. A. Abbasi and M.U. Abbasi, “A proposed FPGA based
The implemented Sobel Edge Detector architecture using
architecture for sobel edge detection operator”, J. of Active and
low cost available Spartan 3 development system with Passive Electronic Devices, Vol. 2, pp. 271–277.
Xilinx chip XC3S50 -5PQ208 has 54.505 MHz maximum

855