Synthesis Basics

Synopsys University Courseware

Copyright © 2016 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
1
Course Overview

 Synthesis Concepts
 3 lectures
 Standard Cell Libraries
 4 lectures
 Synthesis Constraints
 3 lectures
 Design Environment
 3 lectures
 Reports
 3 lectures

Synopsys University Courseware

Copyright © 20116 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
2
Synthesis Concepts

Synopsys University Courseware

Copyright © 2016 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
3
Concept of Automated Design

 It is possible to convert any digital function to a

logic circuit.
 This is used by synthesis tool to automatically
synthesize circuit from functional description.
a
b
z = (a+b)&(c+d)&e c
z
d
e

Synopsys University Courseware

Copyright © 20116 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
4
Concept of Automated Design (2)

 If primitive (standard) cells are previously designed,

large number of various digital circuits can be built using
these parts.

 The group of primitive cells which are used to build

larger circuits is called standard cell library.

Synopsys University Courseware

Copyright © 20116 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
5
Basic Steps of Synthesis

Circuit description z = (a+b)&(c+d)&e

Logic Synthesis
a
b
Logic Circuit c z
d
e
Physical Synthesis

Layout of finished design

Synopsys University Courseware

Copyright © 20116 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
6
Logic Synthesis

 Logic synthesis is the process of creation logic circuit

from circuit description.
Circuit Constraints Standard cell
description(*.v) (*.tcl) library (*.lib)
z : output; Timing AND
x, y, w : input; Area
z = (x ⊕ y) & w; Power XOR

Logic synthesis

x
y z
w
Synopsys University Courseware
Copyright © 20116 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
7
Logic Synthesis (2)

 The circuit that was simply created from function can operate not as
expected.
 For ensuring correct operation additional elements should be added
to the circuit.

“1” “1”

delay

 The circuit must be also optimized during the logic synthesis.

Synopsys University Courseware

Copyright © 20116 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
8
Optimization

 Same function can be represented with different circuits

 Different circuits can have different physical parameters
 Choice is performed based on the requirements
(Constraints)
Function: Y = a & b & c & d
Variant 1 Variant 2
Cell Power Area
a
b
c 2 100
d
y
e y 5 200

6 400
Total power: 9 Total power: 8
Total area: 300 Total area: 500

Synopsys University Courseware

Copyright © 20116 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
9
Main Optimization Trade-Offs

 Circuit design goals are:

 Timing - small delays
 Power - low power consumption (based on low power design
techniques, with UPF integration)
 Area - small area
 Circuit design is a trade-off of timing, area and power
 Optimal design is found as result of synthesis based on
the priorities set by designer
 For example when delays are small, power consumption is high, and
vice versa, circuit variant is chosen based on the importance of one of
parameters against another
 Note! By default tool give priority to timing during synthesis optimization
Synopsys University Courseware
Copyright © 20116 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
10
Constraints

 The design goal (timing, area, power) is

defined by the constraints
 Constraints are the set of rules that set limits
on circuit parameters according to parameter
priorities and requirements
 During synthesis process every time there is choice
between several circuit variants the one meeting
constraints is chosen

Synopsys University Courseware

Copyright © 20116 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
11
Environment Attributes
 Environmental parameters and net attributes affect circuit operation
 Synthesis step need to account for them for correct results
 This data should be provided to the synthesis tool
 In logic synthesis step net attributes should be modeling preliminary
with wire_load_models, as in this step no information about
placement
Environmental parameters Net attributes
voltage/temperature/process variations parasitic resistances/capacitances

IN … ?
D Q
… D Q OUT
?
?
?
CLK

Synopsys University Courseware

Copyright © 20116 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
12
Design Environment of Logic
Synthesis

Constraints Environment attributes

RTL
Logic circuit: Gate-
Code Logic Synthesis level Netlist
(Verilog) (Synthesis tool)
(Verilog / VHDL)
VHDL

Cell Library .lib/.db

(Logical Description) Physical Design
(Physical synthesis tool)

Synopsys University Courseware

Copyright © 20116 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
13
DC and Design Flow

Constrai
nts HDL

IP DesignWare Design Compiler

Library
Timing & power
Timing Data Power
optimization optimization optimization analysis

Technology
Library Area Test Timing
optimization synthesis closure Formal verification

Symbol Library

Optimized
SDF gate-level netlist
PDEF
Back-annotation
Place & route

Synopsys University Courseware

Copyright © 20116 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
14
Basic Synthesis Flow
Develop HDL files

Specify libraries

Read design
Design optimization constraints
Design rule constraints create_clock
set_max_transition Define design environment set_clock_latency
set_max_fanout set_propagated_clock
set_max_capacitance set_clock_uncertaintly
Set design constraints set_clock_transition
set_input_delay
set_output_delay
set_max_area
compile
Optimize the design

Analyze and resolve design check_design

report_area
problems report_constrai
nt
Save the design database report_timing
write

Synopsys University Courseware

Copyright © 20116 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
15
DC’s Input and Output Files

Design
source Reports and logs
Code (text formats)
Verilog(.v )
VHDL (.vhd) Design Design database
Synthesis (.db - Synopsys internal
scripts (.tcl) Compiler
database format)
Design Gate level Verilog
constraints description
(.con, .sdc)

Synopsys University Courseware

Copyright © 20116 Synopsys, Inc. All rights reserved.
Synthesis Basics
Lecture - 1
Developed By: Vazgen Melikyan
16