Integer Data Representation

Signed Integer
• 3 major representations:
Sign-magnitude
One’s complement
Two’s complement
• Assumptions:
4-bit machine word
16 different values can be represented
Roughly half are positive, half are negative
Sign and Magnitude Representation

-7 +0
-6 1111 0000 +1
1110 0001
-5 +2 +
1101 0010
-4 1100 0011 +3 0 100 = + 4

-3 1011 0100 +4 1 100 = - 4

1010 0101
-2 +5 -
1001 0110
-1 1000 0111 +6
-0 +7
High order bit is sign: 0 = positive (or zero), 1 = negative
Three low order bits is the magnitude: 0 (000) thru 7 (111)
Number range for n bits = +/-2n-1 -1
Two representations for 0
One’s Complement Representation

-0 +0
-1 1111 0000 +1
1110 0001
-2 +2 +
1101 0010
-3 1100 0011 +3 0 100 = + 4

-4 1011 0100 +4 1 011 = - 4

1010 0101
-5 +5 -
1001 0110
-6 1000 0111 +6
-7 +7
• Subtraction implemented by addition & 1's complement
• Still two representations of 0! This causes some problems
• Some complexities in addition
 Two’s Complement Representation

-1 +0
-2 1111 0000 +1
1110 0001
-3 +2 +
like 1's comp 1101 0010
except shifted -4 1100 0011 +3 0 100 = + 4
one position
clockwise -5 1011 1 100 = - 4
0100 +4
1010 0101
-6 +5 -
1001 0110
-7 1000 0111 +6
-8 +7

• Only one representation for 0

• One more negative number than positive number
Binary, Signed-Integer Representations
B Values represented

Sign and
b3 b2b1b0 magnitude 1's complement 2's complement

0 1 1 1 +7 +7 +7
0 1 1 0 +6 +6 +6
0 1 0 1 +5 +5 +5
0 1 0 0 +4 +4 +4
0 0 1 1 +3 +3 +3
0 0 1 0 +2 +2 +2
0 0 0 1 +1 +1 +1
0 0 0 0 +0 +0 +0
1 0 0 0 -0 -7 -8
1 0 0 1 -1 -6 -7
1 0 1 0 -2 -5 -6
1 0 1 1 -3 -4 -5
1 1 0 0 -4 -3 -4
1 1 0 1 -5 -2 -3
1 1 1 0 -6 -1 -2
1 1 1 1 -7 -0 -1

Binary, signed-integer representations.

Other Number Systems

1. Octal

2. Hexa-Decimal
 Conversion
Among
Various Number System
1.Binary

2.Octal

3.Decimal

4.Hexa-Decimal
Two’s Complement Number System

Question
Considering a 4 bit system, how to represent -5 in two’s complement number system?

Answer
There are multiple methods by which one can find out the answer.

Method 1: Take 1’s complement of +5 (represented in sign & magnitude) and add 1.

Method 2:- Scan from right to left, first 1 acts like a switch and then
complement rest of the bits.
Alternative Interpretation of
2’s Complement Numbers
Class Work
 Example

Question:
What is the decimal equivalent of the number 1101 (represented in two’s complement)?

Answer: [decimal of 101] - 2^3

Addition and Subtraction – 2’s Complement

4 0100 -4 1100
+3 0011 + (-3) 1101
If carry-in to the high 7 0111
order bit = -7 11001
carry-out then ignore
carry

if carry-in differs from 4 0100 -4 1100

carry-out then overflow
-3 1101 +3 0011

1 10001 -1 1111

Simpler addition scheme makes twos complement the most common

choice for integer number systems within digital systems
2’s-Complement Add and Subtract
Operations (+4)
(a) 0 0 10 (+2) (b) 0 1 00
+ 0 0 11 (+3 ) + 1 0 10 - 6
0 1 01 (+5) 1 1 10 - 2
(c) 1 0 11 - 5 (d) 0 1 11 (+7 )
+ 1 1 10 - 2 + 1 1 01 - 3
1 0 01 - 7 0 1 00 (+4)
(e) 1 1 01 - 3 1 1 01
- 100 1 - 7 + 0 1 11
0 1 00 (+4)
(f) 0 0 10 (+2) 0 0 10
- 010 0 ( + 4) + 1 1 00
1 1 10 - 2
(g) 0 1 10 (+6) 0 1 10
- 001 1 (+3) + 1 1 01
0 0 11 (+3)
(h) 1 0 01 - 7 1 0 01
- 101 1 - 5 + 0 1 01
1 1 10 - 2
(i) 1 0 01 - 7 1 0 01
- 000 1 (+1) + 1 1 11
1 0 00 - 8
(j) 0 0 10 (+2) 0 0 10
- 110 1 - 3 + 0 0 11
0101 ( + 5)

2's-complement Add and Subtract operations.

 Overflow - Add two positive numbers to get a negative
number or two negative numbers to get a positive number

-1 +0 -1 +0
-2 1111 0000 +1 -2 1111 0000 +1
1110 0001 1110 0001
-3 +2 -3
1101 1101 +2
0010 0010
-4 -4
1100 0011 +3 1100 0011 +3
-5 1011 -5
0100 1011
+4 0100 +4
1010 1010
-6 0101 -6 0101
1001
+5 +5
0110 1001 0110
-7 1000 0111 +6 -7 1000 +6
0111
-8 +7 -8 +7

5 + 3 = -8 -7 - 2 = +7
 Overflow Conditions
0111 1000
5 0101 -7 1001
3 0011
-2 1100
-8 1000
7 10111
Overflow Overflow
0000 1111
5 0101 -3 1101
2 0010 -5 1011
7 0111 -8 11000

No overflow No overflow

Overflow when carry-in to the high-order bit does not equal carry out
 Sign Extension
• Task:
– Given w-bit signed integer x
– Convert it to w+k-bit integer with same value
• Rule:
– Make k copies of sign bit:
– X  = xw–1 ,…, xw–1 , xw–1 , xw–2 ,…, x0
w
X • • •
k copies of MSB

• • •

X • • • • • •
k w
 Sign Extension Example

short int x = 15213;

int ix = (int) x;
short int y = -15213;
int iy = (int) y;

Decimal Hex Binary

x 15213 3B 6D 00111011 01101101
ix 15213 00 00 C4 92 00000000 00000000 00111011 01101101
y -15213 C4 93 11000100 10010011
iy -15213 FF FF C4 93 11111111 11111111 11000100 10010011
Binary Multiplication
 1 3 1101 (Multiplicand)
9 1001 (Multiplier)
1 1 7 1101
(a) 0000 Partial sums
0000
1101
1110101 (Product)
(b)
 13 → Multiplicand
 9 → Multiplier
 117 → Product
Basic Multiplication
 Consider the lsb of the multiplier
 If it is 1, write the value of the multiplicand
 If it is 0, write 0
 For the next bit of the multiplier
 If it is 1, write the value of the multiplicand shifted
by 1 position to the left
 If it is 0, write 0
 Keep going ….
Definitions

 If the multiplier has m bits, and the multiplicand

has n bits
 The product requires (m+n) bits
Multiplying 32 bit numbers
 Let us design an iterative multiplier that multiplies
two 32 bit signed values to produce a 64 bit result
 This will prevent the Overflow.
Class Work
Iterative Multiplier
Multiplicand Multiplier

U V

 Multiplicand (N), Multiplier (M), Product(P) = MN

 U and V are 32 bit registers
 beginning : V contains the multiplier, U = 0
 UV is one register for the purpose of shifting
Algorithm
Algorithm 1: Algorithm to multiply two 32 bit numbers and produce a 64 bit result

Data: Multiplier in V , U = 0, Multiplicand in N

Result: The lower 64 bits of UV contains the product
i ← 0
for i < 32 do
i ← i + 1
if LSB of V is 1 then
if i < 32 then
U ← U + N
end
else
U ← U − N
end
end
UV ← UV >> 1 (arithmetic right shift)
end
3x2=6
0011 (Multiplicand)
0010 (Multiplier)
0000
0011 Partial sums
0000
0000
0000110 (Product)
Example
Multiplicand (N) 0010 2

Multiplier (M) 0011 3

U V
beginning: 00000 0011

before shift: 00010 0011 1 add 2

1
after shift: 00001 0001

before shift: 00011 0001 1 add 2

2
after shift: 00001 1000

before shift: 00001 1000 0 --

3
after shift: 00000 1100

before shift: 00000 1100

0 --
4
after shift: 00000 0110

Product(P) 0110 6
 3x-2=-6
0011 (Multiplicand)
1110 (Multiplier)
0000
0011
0011
0011
1111010 (Product)

Result of the addition of first 3 rows:- Now subtract the 4th row from the partial Sum:-
0000 010010
0011X 1101XXX
0011XX --------------
------------------ 1111010 (-6)
010010 (Partial Sum)
3 * (-2)
Multiplicand (N) 0011 3

Multiplier (M) 1110 -2

U V
beginning: 00000 1110

before shift: 00000 1110 0 --

1
after shift: 00000 0111

before shift: 00011 0111 1 add 3

2
after shift: 00001 1011

before shift: 00100 1011

1 add 3
3
after shift: 00010 0101
1 sub 3
before shift: 11111 0101
4
after shift: 11111 1010

Product(P) 1010 -6
Operation of the Algorithm
 Take a look at the lsb of V
 If it is 0 → do nothing
 If it is 1 → Add N (multiplicand) to U
 Right shift
 Right shifting the partial product is the same as left
shifting the multiplicand, which
 Needs to be done in every step
 Last step is different
The Last Step ...
 In the last step
 lsb of V = msb of M (multiplier)
 If it is 0 → do nothing
 If it is 1
 Multiplier is negative
 Recall : A = A1 .. n-1 - 2n-1An
 Hence, we need to subtract the multiplicand if the msb of
the multiplier is 1
Booth Multiplier
 We can make our iterative multiplier faster
 If there are a continuous sequence of 0s in the multiplier
 do nothing
 If there is a continous sequnce of 1s

 do something smart
In case of Continuous 1’s:::::
If value of M is 0011 1100
Then,

Here, i = 2 and j = 5
So, M = 2^6 – 2^2
= 64 – 4
= 60

Otherwise, we have to calculate,

M = 2^5 + 2^4 + 2^3 + 2^2
= 32 + 16 + 8 + 4
= 60
 For a Sequence of 1s
 Sequence of 1s from position i to j
 Perform (j – i + 1) additions

 New method
 Subtract the multiplicand when we scan bit i ( ! count starts from 0)
 Keep shifting the partial product
 Add the multiplicand(N), when we scan bit (j+1)
 This process, effectively adds (2j+1 – 2i) * N to the partial product
 Exactly, what we wanted to do …
 So, (j – i + 1) additions will be replaced by 1 addition and 1 subtraction.
Operation of the Algorithm
 Consider bit pairs in the multiplier
 (current bit, previous bit)
 Take actions based on the bit pair
 Action table

(current value, previous value) Action

0,0 -
1,0 (1’s just started) subtract multiplicand from U
1,1 -
0,1 (runs of 1’s ended) add multiplicand to U
Booth's Algorithm
Algorithm 2: Booth’s Algorithm to multiply two 32 bit numbers to produce a 64 bit
result
Data: Multiplier in V , U = 0, Multiplicand in N
Result: The lower 64 bits of UV contain the result
i ← 0
prevBit ← 0
for i < 32 do
i ← i + 1
currBit ← LSB of V
if (currBit,prevBit) = (1,0) then
U ← U − N
end
else if (currBit,prevBit) = (0,1) then
U ← U + N
end
prevBit ← currBit
UV ← UV >> 1 (arithmetic right shift)
end
Multiplicand (N) 00011 3

Multiplier (M) 0010 2

U V
beginning: 00000 0010

before shift: 00000 0010 00 --

1
after shift: 00000 0001

before shift: 11101 0001 10 add -3

2
after shift: 11110 1000

before shift: 00001 1000 01 add 3

3
after shift: 00000 1100
00 --
before shift: 00000 1100
4
after shift: 00000 0110

Product(P) 0110 6
Multiplicand (N) 00011 3

Multiplier (M) 1110 -2

U V
beginning: 00000 1110

before shift: 00000 1110 00 --

1
after shift: 00000 0111

before shift: 11101 0111 10 add -3

2
after shift: 11110 1011

before shift: 11110 1011 11 --

3
after shift: 11111 0101
11 --
before shift: 11111 0101
4
after shift: 11111 1010

Product(P) 1010 -6
Integer Division
 Let us only consider positive numbers
 N = DQ + R . . . . . (1)
 N → Divident
 D → Divisor
 Q → Quotient
 R → Remainder

 Properties
 [Property 1:] R < D, R >= 0
 [Property 2:] Q is the largest positive integer
satisfying Equation 1
 Dividend (N)
Divisor (D) 111 Quotient (Q)
11 10

11

01
Remainder (R)
Reduction of the Divison Problem

We have reduced the original problem to a smaller problem

( Q’s are binary 0’s and 1’s )

How to Reduce the Problem
 We need to find Qn
 We can try both values – 0 and 1
 First try 1
 If : N – D2n-1 >= 0, Qn = 1 (maximize the
quotient)
 Otherwise it is 0
 Once we have reduced the problem
 We can proceed recursively
 Iterative Divider
Divisor(D) Dividend (N)

(U-D)

U V

Initial: V holds the dividend (N), U = 0

Final: U holds Remainder(R) and V holds Quotient(Q)

Restoring Division
Algorithm 3: Restoring algorithm to divide two 32 bit numbers
Data: Divisor in D, Dividend in V, U = 0
Result: U contains the remainder (lower 32 bits), and V contains the quotient
i ← 0
for i < 32 do
i ← i + 1
/* Left shift UV by 1 position */
UV ← UV << 1
U ← U - D
if U ≥ 0 then
q ← 1
end
else
U ← U + D
q ← 0
end
/* Set the quotient bit */
LSB of V ← q
end
Example
Dividend (N) 00111

Divisor (D) 0011

U V
beginning: 00000 0111

after shift: 00000 111X

1 end of 00000 1110
iteration:
after shift: 00001 110X
2 end of 00001 1100
iteration:
after shift: 00011 100X
3 end of 00000 1001
iteration:
after shift: 00001 001X
4
end of 00001 0010
iteration:

Quotient(Q) 0010

Remainder(R) 0001
Restoring Division
 Consider each bit of the dividend
 Try to subtract the divisor from the U
register
 If the subtraction is successful, set the relevant
quotient bit to 1
 Else, set the relevant quotient bit to 0
 Left shift