Floor Planning:

Floor plan determines the size of the design cell (or die), creates the boundary and core area, and
creates wire tracks for placement of standard cells. [1]. It is also a process of positioning blocks
or macros on the die.

Floor planning control parameters like aspect ratio, core utilization are defined as follows:
Aspect Ratio= Horizontal Routing Resources / Vertical Routing Resources
Core Utilization= Standard Cell Area / (Row Area + Channel Area)
Total 4 metal layers are available for routing in used version of Astro. M0 and M3 are horizontal
and M2 and M4 are vertical layers. Hence aspect ratio for SAMM is 1. Total number of cells
=1645; total number of nets=1837 and number of ports (excluding 16 power pads) = 60.
The figure depicting floor plan-die size (µm) of SAMM is shown beside.

Top Design Format (TDF) files provide Astro with special instructions for planning, placing, and
routing the design. TDF files generally include pin and port information. Astro particularly uses
the I/O definitions from the TDF file in the starting phase of the design flow. [1]. Corner cells are
simply dummy cells which have ground and power layers. The TDF file used for SAMM is
given below. The SAMM IC has total 80 I/O pads out of which 4 are dummy pads. Each side of
the chip has 20 pads including 2 sets of power pads. Number of power pads required for SAMM
is calculated in power planning section. Design is pad limited(pad area is more than cell area)
and inline bonding (same I/O pad height) is used.
define _cell (geGetEditCell)
;create power pads

There are two types of power planning and management. They are core cell power
management and I/O cell power management. In former one VDD and VSS power rings are
formed around the core and macro. In addition to this straps and trunks are created for macros as
per the power requirement. In the later one, power rings are formed for I/O cells and trunks are
constructed between core power ring and power pads. Top to bottom approach is used for the
power analysis of flatten design while bottom up approach is suitable for macros.
The power information can be obtained from the front end design. The synthesis tool reports
static power information. Dynamic power can be calculated using Value Change Dump
(VCD) or Switching Activity Interchange Format (SAIF) file in conjunction with RTL
description and test bench. Exhaustive test coverage is required for efficient calculation of peak
power. This methodology is depicted in Figure (1).

For the hierarchical design budgeting has to be carried out in front end. Power is calculated from
each block of the design. Astro works on flattened netlist. Hence here top to bottom approach
can be used. JupiterXT can work on hierarchical designs. Hence bottom up approach for power
analysis can be used with JupiterXT. IR drops are not found in floor planning stage. In placement
stage rails are get connected with power rings, straps, trunks. Now IR drops comes into picture
and improper design of power can lead to large IR drops and core may not get sufficient power.

Figure (1) Power Planning methodology

Below are the calculations for flattened design of the SAMM. Only static power reported by the
Synthesis tool (Design Compiler) is used instead of dynamic power.

 The number of the core power pad required for each side of the chip
= total core power / [number of side*core voltage*maximum allowable current for a I/O pad]
= 236.2068mW/ [4 * 1.08 V * 24mA] (Considering design SAMM)
= 2.278
~2
Therefore for each side of the chip 2 power pads (2 VDD and 2 VSS) are added.
 Total dynamic core current (mA)
= total dynamic core power / core voltage
= 236.2068mW / 1.08V
= 218.71 mA
 Core PG ring width
= (Total dynamic core current)/ (No. of sides * maximum current density of the metal layer used
(Jmax) for PG ring)
=218.71 mA/(4*49.5 mA/µm)
~1.1 µm
~2 µm
 Pad to core trunk width (µm)
= total dynamic core current / number of sides * J max where Jmax is the maximum current
density of metal layer used
= 218.71 mA / [4 * 49.5 mA/µm]
= 1.104596 µm
Hence pad to trunk width is kept as 2µm.

Using below mentioned equations we can calculate vertical and horizontal strap width and
required number of straps for each macro.
 Block current:
Iblock= Pblock / Vddcore

 Current supply from each side of the block:

 Power strap width based on EM:

 Power strap width based on IR:

 Refresh width:
Wrefresh_vertical =3 * routing pitch +minimum width of metal (M4)
Wrefresh_horizontal =3 * routing pitch +minimum width of metal (M3)

 Refresh number
Nrefresh_vertical = max (Wstrap_vertical ) / Wrefresh_vertical
Nrefresh_horizontal = max (Wstrap_horizontal ) / Wrefresh_horizontal

 Refresh spacing
Srefresh_vertical = Wblock / Nrefresh_vertical
Srefresh_horizontal = Hblock / Nrefresh_horizontal
Figure (2) Showing core power ring, Straps and Trunks