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Memory Systems for CSE Students

The document discusses memory organization and hierarchy. It describes how memory is arranged from fastest to slowest access speeds, including registers, cache memory, main memory, and auxiliary memory such as magnetic disks and tapes. It then focuses on main memory, including RAM and ROM chips, addressing schemes, and how memory is connected to the CPU through address and data buses. Memory chips are selected using chip select lines, and portions of the address bus are used to select locations within individual chips.

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Shaik Sharief
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109 views6 pages

Memory Systems for CSE Students

The document discusses memory organization and hierarchy. It describes how memory is arranged from fastest to slowest access speeds, including registers, cache memory, main memory, and auxiliary memory such as magnetic disks and tapes. It then focuses on main memory, including RAM and ROM chips, addressing schemes, and how memory is connected to the CPU through address and data buses. Memory chips are selected using chip select lines, and portions of the address bus are used to select locations within individual chips.

Uploaded by

Shaik Sharief
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Memory Organization 1 Lecture 40

Overview

 Memory Hierarchy

 Main Memory

 Auxiliary Memory

 Associative Memory

 Cache Memory

 Virtual Memory

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT


Memory Organization 2 Lecture 40

Memory Hierarchy
Memory Hierarchy is to obtain the highest possible access speed while minimizing
the total cost of the memory system

Magnetic
tapes I/O Main
processor memory
Magnetic
disks

CPU Cache
memory

Register

Cache

Main Memory

Magnetic Disk

Magnetic Tape

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT


Memory Organization 3 Lecture 40

Main Memory
RAM and ROM Chips
Typical RAM chip
Chip select 1 CS1
Chip select 2 CS2
Read RD 128 x 8 8-bit data bus
RAM
Write WR
7-bit address AD 7

CS1 CS2 RD WR Memory function State of data bus


0 0 x x Inhibit High-impedence
0 1 x x Inhibit High-impedence
1 0 0 0 Inhibit High-impedence
1 0 0 1 Write Input data to RAM
1 0 1 x Read Output data from RAM
1 1 x x Inhibit High-impedence

Typical ROM chip

Chip select 1 CS1


Chip select 2 CS2
512 x 8 8-bit data bus
ROM
9-bit address AD 9

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT


Memory Organization 4 Lecture 40

Memory Address Map


Address space assignment to each memory chip

Example: 512 bytes RAM and 512 bytes ROM

Hexa Address bus


Component address 10 9 8 7 6 5 4 3 2 1
RAM 1 0000 - 007F 0 0 0 x x x x x x x
RAM 2 0080 - 00FF 0 0 1 x x x x x x x
RAM 3 0100 - 017F 0 1 0 x x x x x x x
RAM 4 0180 - 01FF 0 1 1 x x x x x x x
ROM 0200 - 03FF 1 x x x x x x x x x

Memory Connection to CPU


-RAM and ROM chips are connected to a CPU through the data and address
buses
-- The low-order lines in the address bus select the byte within the chips and
other lines in the address bus select a particular chip through its chip select
inputs

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT


Memory Organization 5 Lecture 40

Connection of Memory to CPU


Address bus CPU
16-11 10 9 8 7-1 RD WR Data bus

Decoder
3 2 1 0
CS1
CS2

Data
RD 128 x 8
RAM 1
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 2
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 3
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 4
WR
AD7

CS1
CS2
Data

1- 7 512 x 8
8
9 } AD9 ROM

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT


Memory Organization 6 Lecture 40

Connection of Memory to CPU

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

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