ECE 1315 Digital Logic Design Laboratory Manual: Guide To Assembling Your Circuits
ECE 1315 Digital Logic Design Laboratory Manual: Guide To Assembling Your Circuits
Laboratory Manual
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V. - Guide to Assembling your Circuits.
In this section we describe the use of the breadboard and give basic hints about the
wiring process needed to power up and interconnect your circuits.
Assembling circuits on your breadboard is a fast and easy process once you get used
to it. To assemble your circuit first select the chips that you need, insert them in the
breadboard, wire up the power and ground connections as described in the next section
and next wire the logic elements according to the circuit connections that you obtained
from the design process.
Before you insert a chip into the breadboard, make sure it is properly oriented (see
Fig. 9 & 10), and that when you press it down the pins of the chip actually enter the holes
and do not bend underneath the chip package.
When wiring, be careful to hit the right hole needed in the connection, because this is
one of the most common mistakes found to cause an error in your projects.
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Fig. 6. - Breadboard
Also, in Figures 7 and 8 we show two typical ways to distribute power (1), and
ground (2) signals that are recommended in order to avoid noise in your circuit, and
assure good performance from the chips. The banana plugs (3), if available, can be used
to connect your breadboard to an external power supply (usually the Heathkit board).
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Fig. 9. - Inverter (NOT) gate pin distribution
Most commonly used TTL devices have their power and ground connections on pins
14 and 7 respectively, however verify this information before using some special function
or uncommon packages. Also, all packages have a notch or mark that indicates the proper
orientation of the device. From this mark each pin is numbered in a counter clockwise
direction. The specific function that each chip performs is typically described using
function tables, logic tables or logic diagrams as the ones shown in Figure 11.
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Fig. 11. - Typical Manual Descriptions for a TTL Gate.
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5.3. - Diagrams and Labeling.
Using the pin distribution for the TTL packages given by the manufacturer, and
once that you design the circuit that performs the desired logic function, the next step is
to wire up the circuit that implements this function. Because every chip has a different
number of gates, a good implementation step is to make a diagram for the circuit and
label all inputs, outputs and gates in the way shown in Figure 12. By doing this the wiring
and testing process will be done very easily in the lab.
Package Label
Pin Number
Gate Name
There are many methods than can be used to label a circuit. In this manual we show
only one that is easy to understand and implement. In this method, every input and output
pin shown in the diagram shows the respective pin number that corresponds to the gate in
its package. The gates are labeled using a letter and a number. The letter labels a specific
gate inside the package, and the number labels the package corresponding to its order.
This is shown in Figure 13.
For Figure 13, the gate labeled A1 means gate A in chip 1, B1 means gate B in chip
one, and A2 means gate A in chip 2 and so on and so forth. Using this information it is
very easy to wire the circuit on the breadboard since you only need to place the chips on
the breadboard following the order that the chip was given on the diagram. Next, you
only need to connect a wire between the pins that are given for every chip.
For example, a wire has to be connected between pin 6 of the third chip (B3) and pin
9 of the fourth chip (C4). Another wire has to be connected between pin 8 of the first chip
(C1) and pin 5 of chip number 5 (C5), and so on and so forth.
Labeling the circuit in this way also makes it easier to find errors on the wiring during
the testing process.
Another important characteristic that can be noticed from this diagram is that the flow
of interconnections and signals follows a left to right direction. This means that typically
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in an electric connection diagram, the inputs will be shown on the left and outputs will be
shown on the right. The reason for this is that in this way it is easy to follow the flow of
signals in the circuit, and the function implementation at every step that each gate
performs. On other hand, it makes the circuit interconnections to appear clearer.
In the Table 1, we show the TTL inventory for the chips available in the lab that can
be used in the implementation of your circuits. For some lab experiments you will be
informed about which chips you can exclusively use for that project in particular,
otherwise you can use any package that is given in the list. Also, a quick reference guide
for some of the most common devices is shown in Figure 14.
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NAME FUNCTION NAME FUNCTION
74LS139 DUAL 2-->4 DECODER 74LS00 2 INPUT NAND
74LS148 8-->3 DECODER 74LS02 2 INPUT NOR
74LS151 8-->1 MULTIPLEXER 74LS04 INVERTER
74LS153 4-->1 MULTIPLEXER 74LS08 2 INPUT AND
74LS155 2-->4 DECODER 74LS10 3 INPUT NAND
74LS157 2--> 1 MULTIPLEXER 74LS11 3 INPUT AND
74LS161 4 BIT COUNTER 74LS20 4 INPUT NAND
74LS163 4 BIT COUNTER 74LS25 4 INPUT NOR
74LS164 8 BIT SHIFT REG 74LS27 3 INPUT NOR
74LS169 4 BIT COUNTER 74LS30 8 INPUT NAND
74LS170 4 x 4 REGISTER 74LS32 2 INPUT OR
74LS174 HEX D F-F 74LS42 4-->10 DECODER
74LS175 QUAD D F-F 74LS74 DUAL D F-F
74LS191 4 BIT COUNTER 74LS75 QUAD LATCH
74LS193 4 BIT COUNTER 74LS83 4 BIT ADDER
74LS194 4 BIT SHIFT REG 74LS85 4 BIT COMPARATOR
74LS195 4 BIT SHIFT REG 74LS86 2 INPUT XOR
74LS244 OCTAL BUFFER 74LS93 4 BIT COUNTER
74LS259 8 BIT ADDER 74LS95 4 BIT SHIFT REG
74LS283 4 BIT ADDER 74LS109 DUAL J-K' F-F
74LS373 OCTAL LATCH 74LS138 3-->8 DECODER
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6.1. - TTL Quick Reference
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VII. – Circuit Testing and Input Generation and Output Display.
Once the circuits for your lab experiment have been designed and built on your
breadboard, the final step is to test them and verify that they produce the set of outputs
expected for the set of inputs provided. The set of inputs to test your circuit can be
generated in two different ways: manually and automatically.
In order to use one of the switches to generate a logic variable, just connect a
wire to the breadboard output of the respective switch, and connect the other side
of the wire to the respective input. To observe the state of this input you can
connect another wire from this variable to one of the displays.
W 1 16 Vcc
X 2 15 Column 1
Y 3 14 Column 2
Z 4 13 Column 3
Sequence 5 12 Column 4
Clock 6 11 Column 5
Column 8 7 10 Column 6
Ground 8 9 Column 7
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used for testing combinational circuits. The use of this pin will be explained later
in the sequential circuits section.
When the Chipmonk is working correctly you should see displayed on the
oscilloscope screen a truth table showing the input and output variables for your
circuit. The variables will be displayed from left to right on the screen, in the
same order that you wired them to the Chipmonk, as shown in Figure 16.
Normally, when testing your experiments, you will want to display both the
inputs to your circuit (W, X, Y, Z) and the outputs produced by your circuit, so
that you can determine whether the proper output values are produced for each
combination of input values. You can use any column to display either the value
of an input or the value of an output.
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In order for the Chipmonk circuitry and Oscilloscope to work properly, the
Heathkit frequency and frequency multiplier knobs (3 & 4 on Fig. 1) should be set
fully clockwise. The oscilloscope controls should all be set on the “X-Y” mode
(1, 2 , 3 and 4 in Fig. 17). Set channels 1 and 2 both at 0.5 volts per division (5,
6); AC coupled (7, 8), and pull out the channel 2-position control (9).
Use the channel 2 position and the horizontal position adjustments to center
the display on the screen. Once these controls are set, they should not need to be
changed.
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Next, in the section VIII we show a table with the main Boolean Algebra laws, theorems
and properties that can be applied to reduce a logic function.
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VIII. - Basic Laws and Theorems for Boolean Algebra.
IDENTITY LAWS
X + 0= X X · 1= X
X + 1= 1 X · 0= 0
IDEMPOTENT LAWS
X+X=X X·X=X
INVOLUTION LAW
(X')' = X
COMPLEMENT LAWS
X + X' = 1 X · X' = 0
COMMUTATIVE LAWS
X+Y=Y+X X·Y=Y·X
ASSOCIATIVE LAWS
(X + Y) + Z = X + (Y + Z) (X · Y) Z = X (Y · Z)
DISTRIBUTIVE LAWS
X(Y + Z) = X · Y + X · Z X + Y · Z = (X + Y) (X + Z)
SIMPLIFICATIVE THEOREMS
X · Y + X · Y' = X (X + Y) (X + Y') = X
(X + Y')Y = X · Y X · Y' + Y = X + Y
ABSORPTION THEOREMS
X+X·Y=X X (X + Y) = X
DEMORGAN'S LAWS
(X + Y) ' = X' · Y' (X · Y) ' = X' + Y'
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