DIGITAL LOGIC DESIGN

CEL-120
LAB MANUAL

DEPARTMENT OF COMPUTER SCIENCE

BAHRIA UNIVERSITY
ISLAMABAD CAMPUS
 LIST OF EXPERIMENTS

Lab No. Title of Experiment

Lab 01 Implementation of AND, OR, NAND, NOR and NOT gates.

Lab 02 To implement a circuit from given expression

Lab 03 Implementation of gate using the universal gates

Lab 04 Implementation of 3-Bit parity Generator and Checker

Lab 05 Implementation of half adder and a full adder

Lab 06 Implementation of 4x1 MUX using gates and using IC 74LS153

Lab 07 Implementation of 2 to 4 decoder using basic gates

Lab 08 Implementation of 4-bit adder and subtractor using IC 7483 and 7486

Lab 09 Implementation of SR latches & SR latches with control bit

Lab 10 Implementation of a D Latch & D FLIP FLOP

Lab 11 Implementation and verification of the functionality if T Flip Flop

Lab 12 Implementation and verification of the functionality if JK Flip Flop ,

Lab 13 Implementation and verification of Magnitude Comparator

Lab 14 Implementation and verification of 3-bit Asynchronous Counter

 LAB NO. 1

Implementation of AND, OR, NAND, NOR and

NOT gates.
OBJECTIVE:
Demonstrate the operations of basic logic gates.
Use the following gates and draw their truth table.
74LS00 Quad 2-Input NAND Gate
74LS02 Quad 2-Input NOR Gate
74LS04 Hex single-Input NOT Gate
74LS08 Quad 2-Input AND Gate
74LS32 Quad 2-Input OR Gate
74LS86 Quad 2-Input EX-OR Gate
74LS266 Quad 2-Input EX-NOR Gate

EQUIPMENT USED:
DEV-2771 Trainer, IC 7404, 7400, 7432, 7408, 7402

BACKGROUND THEORY:
A logic gate is a circuit which has one or more inputs and single output. A logic gate is
an elementary building block of a digital circuit. Most logic gates have two inputs and
one output. At any given moment, every terminal is in one of the two binary conditions
low (0) or high (1), represented by different voltage levels. The logic state of a terminal
can, and generally does, change often, as the circuit processes data. In most logic
gates, the low state is approximately zero volts (0 V), while the high state is
approximately five volts positive (+5 V).

For TTL 0 - 0.8V corresponds to ‘0’ logic level and 2 – 5V corresponds to ‘1’ logic level.

PROCEDURE:
Connect the circuit according to the pin configuration of the ICs as mentioned in the
datasheets and check the truth tables.

SYMBOLS:
Following are the symbols of the basic logic gates:
DESCRIPTION:
Verify the truth tables of all the ICs specified:

 74LS08 ( AND Gate ):

Y=A.B
Input Output
A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1

 74LS32 ( OR Gate ):

Y=A+B

Input Output
A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1

 74LS04 ( NOT Gate ):

 ̅
Y=𝑨

 74LS00 ( NAND Gate ):

̅̅̅̅̅
Y=𝑨. 𝑩

 74LS02( NOR Gate ):

̅̅̅̅̅̅̅̅
Y=𝐴 +𝐵

74LS86 (EX-OR Gate)

 ,

Ex-OR Gate Equivalent Circuit Ex-OR Function Realization using NAND gate

Ex-OR Function Realization using NOR gates

74LS266 (EX-NOR Gate)

Ex-NOR Gate Equivalent Circuit

Ex-NOR Function Realization using NAND gates

Ex-NOR Function Realization using NOR gate

 LAB 02

Implementation of a circuit from given

expression
OBJECTIVES:
To implement a circuit from given expression, make its truth table, find its minterms.
Now Implement the circuit from the minterms again and verify the results with the
initial given expression.
F=X+Ẋ.Y

EQUIPMENT USED:
DEV-2771 Trainer, 74LS32 (OR),74LS08(AND),74LS04(NOT).

PIN CONFIGURATIONS:
PROCEDURE:
From the Expression given make the circuit on the trainer using ICs mentioned and fill
in the truth table.

X Y 𝑋̅ ̅𝑌
𝑋. F

Now find the minterms of this expression and write it on the following blank

F= .

Implement the above expression on the trainer and fill the following table:

X Y F
0 0
0 1
1 0
1 1

Now verify the results of both the tables. Are they both the same or not? And why?
 LAB 03

Implementation of basic gates from universal

gates
OBJECTIVES:
Using two input NAND and NOR gates, construct the following

1. NOT,

2. AND,

3. OR,

After doing this, implement the given expression on the trainer board.

EQUIPMENT USED:
DEV-2771 trainer, IC 74LS00, 74LS02

THEORY:
NAND and NOR gates are called universal gates because we can make any basic gate
from them by using the following circuits.

IMPLEMENTATION OF GATES USING NAND:

AND Gate behavior:
 A B Q
0 0 0
0 1 0
1 0 1
1 1 1

OR GATE BEHAVIOR:

Input= x, y. Output=F.

X Y F
0 0 0
0 1 1
1 0 1
1 1 1

NOT GATE BEHAVIOR:

Input output
0 1
1 0
IMPLEMENTATION OF GATES USING NOR:
Verify all the truth tables on the trainer.

AND GATE BEHAVIOR.

A B Q
0 0 0
0 1 0
1 0 0
1 1 1

OR GATE BEHAVIOR.

A B F
0 0 0
 0 0 1
1 0 1
1 1 1

NOT GATE BEHAVIOR.

A F
0 1
1 0

EXERCISE IN LAB:
Implement following expression using NOR Gate only.

F=𝑿 + 𝒀. 𝒁
CIRCUIT DIAGRAM
TRUTH TABLE:

x Y z F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
 LAB 04

Implementation of 3-bit parity generator and

checker
OBJECTIVES:
Implementation of 3-bit parity generator and checker

TASKS:
 Using AND,OR,NOT gate ICs, implement 3-bit parity generator and checker and
fill in the truth table and make the corresponding circuit.
 After this implement 3-bit parity generator and checker using XOR gate
only(74LS86)

EQUIPMENT USED:
DEV-2771 trainer, IC 74LS86, 74LS32, 74LS08, 74LS04

THEORY:
A parity bit, or check bit, is a bit added to the end of a string of binary code that
indicates whether the number of bits in the string with the value one is even or odd.
Parity bits are used as the simplest form of error detecting code.

There are two variants of parity bits: even parity bit and odd parity bit. In case of even
parity, the parity bit is set to 1 if the count of ones in a given set of bits (not including
the parity bit) is odd, making the count of ones in the entire set of bits (including the
parity bit) even. If the count of ones in a given set of bits is already even, it is set to a 0.
When using odd parity, the parity bit is set to 1 if the count of ones in a given set of bits
(not including the parity bit) is even, making the count of ones in the entire set of bits
(including the parity bit) odd. When the count of set bits is odd, then the odd parity bit
is set to 0.
PIN CONFIGURATION OF XOR (74LS86):

X Y F
0 0 0
0 0 1
1 0 1
1 1 0
EXERCISE IN LAB:
Fill the following truth table for even parity generator

X Y Z F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Now from the table find the minterms and write the corresponding expression in the
following blank

P= .

From the expression make the corresponding circuit and implement it on the trainer
board:
Now make the following circuit on the trainer and verify the following truth table:

𝑝 = 𝑋⨁𝑌⨁𝑍

X0 X1 X2 P
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Now implement the following circuit of even parity generator and fill the truth table:

𝐶 = 𝑋⨁𝑌⨁𝑍⨁𝑃

X Y Z P C
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
 1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

LAB05

Implementation of a half adder and a full adder

OBJECTIVES:
To implement a half adder and a full adder

TASKS:
 Write a truth table for a half adder, design a simplified circuit for it .implement
it on trainer and verify the results.
 Write a truth table for a full adder, design a simplified circuit for it .implement it
on trainer and verify the results.

EQUIPMENT USED:
DEV-2771, IC – XOR, IC-OR, IC-AND.

BACKGROUND THEORY:
A half adder is a combinational circuit that adds two binary inputs .it gives two outputs,
S as the sum and C as the carry of the inputs.

A full adder is a combinational circuit that adds three binary inputs X, Y and Z .The
input Z is the carry input from another addition. It gives two outputs, S as the sum and
C as the carry of the inputs.
EXERCISE IN LAB:
Fill in the following truth table of half adder and full adder and draw the circuit from
them.

Table of full adder Table for half adder

A B C Sum Carry Input Input Sum Carry

0 0 0 A B
0 0 1 0 0
0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1
1 1
1 1 0
1 1 1

CIRCUIT DIAGRAM:
Circuit diagram for Half Adder

Circuit diagram for full adder

 LAB 06

Implementation of a 4 to 1 MUX using gates and

using IC 74LS153
TASKS:
 Write the truth table for a 2 to 1 MUX, design a circuit from it, implement it on
the trainer and verify the results.
 Write down the truth table for a 4 to 1 MUX, draw the circuit, implement it on
the trainer and verify the results.
 Use the IC 74LS153 (4 to 1 MUX) and verify the results.

EQUIPMENT USED:
DEV-2771 Trainer, IC 74LS04 (NOT), 74LS32 (OR), 74LS08 (AND), 74LS153 (4 TO 1 MUX)

BACKGROUND THEORY:
A MUX is a combinational circuit that can be used to select data and produce it at the
output. They can be 2 to 1, 4 to 1, 8 to 1, 16 to 1, etc. It has a lot of applications. There
are many scenarios in which we have to select a particular data and produce it at the
output.

EXERCISE IN THE LAB:

Following is the circuit for 2 to 1 MUX and truth table:
 S B A Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1

CIRCUIT DIAGRAMS:
Draw the diagram of 4 to 1 MUX as follows:

Fill in the following Truth Table:

S1 S0 X3 X2 X1 X0 Y
 0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1

IMPLEMENTING 74LS153:
Following is the pin configuration extracted from the datasheet.

DUAL-IN-LINE Package

FUNCTION TABLE:

SelectInputs DataInputs Strobe Output

 B A C0 C1 C2 C3 G Y
X X X X X X H L
L L L X X X L L
L L H X X X L H
L H X L X X L L
L H X H X X L H
H L X X L X L L
H L X X H X L H
H H X X X L L L
H H X X X H L H

LAB 07

Implementation of a 2 to 4 decoder
OBJECTIVES:
Implementation of a 2 to 4 decoder using basic gates

TASKS:
 Write truth table for a 2 to 4 decoder with enable bit in it.
 Draw the gate diagram of a 2 to 4 decoder.
 Implementation of a 2 to 4 decoder on trainer using three input AND gate with
enable bit as active low and verify with truth table.
 For three input AND gate use 74LS111C.

EQUIPMENT USE:
DEV-2771 Trainer, IC74LS04 (NOT),74LS11(Three input AND gate).

BACKGROUND THEORY:
A decoder is a combinational circuit that coverts binary information from “n” codes
to “2n” (two raised to the power n) unique outputs .They can be 2 to 4, 3 to8, 4 to
16 etc. It has a lot of applications. There are many scenarios in which we have to
use such devices.
EXERCISE IN LAB:
Fill in the truth table for a 2 to 4 decoder with an active low enable bit:

E S1 S0 D3 D2 D1 D0
0 0 0 0 0 0 1
0 0 1 0 0 1 0
0 1 0 0 1 0 0
0 1 1 1 0 0 0
1 X X X X X X

PIN CONFIGURATION OF 74LS11:

Following is the pin diagram of three input And gate IC:

Following is the truth table for three input AND gate IC:

Y=ABC

INPUTS OUTPUT
A B C Y
X X L L
X L X L
L X X L
H H H H
H=HIGH Logic level
L=LOW Logic level
 X=Either LOW or HIGH Logic level

CIRCUIT DIAGRAM:
Draw a 2 to 4 decoder with active low pin:

LAB 08

Implementation of a 4 bit adder and subtractor

OBJECTIVES:
Implementation of a 4 bit adder and subtractor using 74LS83 and 74LS86

TASKS:
 Fill in the truth table consisting of 5 additions and 5 subtractors
 Design the complete circuit on the trainer and verify the results.

EQUIPMENT USE:
DEV-2771 Trainer, IC74LS83 (4-bit adder),74LS86(XOR).

BACKGROUND THEORY:
The circuit for the adder/subtractor is used to do binary additions and subtractions. If
Cin=0, addition is performed and if Cin=1,subtraction is performed.

CIRCUIT DIAGRAM:
Following is the circuit diagram. Implement it on the trainer and verify the results:
This is a 4-bit adder/subtractor circuit. FA is full adder. The operation depends upon
Cin.If Cin=0, addition is performed and if Cin=1, subtraction is performed.

PIN CONFIGURATION OF 74LS83:

EXERCISE IN LAB:
Fill in the following truth table and verify your results and show it to the instructor:-

1)adder
A3 A2 A1 A0

B3 B2 B1 B0
 S3 S2 S1 S0

2)subtract
A3 A2 A1 A0

B3 B2 B1 B0

S3 S2 S1 S0

LAB 09

Implementation of SR latches with control bit and

SR Flip Flop
1. IMPLEMENTATION OF SR LATCHES

OBJECTIVES:
Implementation of SR latches

TASKS:
 Draw the circuit of SR latches with NAND and NOR gates both.
 Implement the circuits and verify the results.

EQUIPMENT USED:
DEV-2771 Trainer, IC 74LS02 (NOR Gate), 74LS00 (NAND Gate)

BACKGROUND THEORY:
The SR latch is a circuit constructed from two cross-coupled NOR or NAND
gates. It is derived from the single-loop storage element. The latch has two inputs
labeled as S for set and R for reset. When Q=1 and Q=0, it is said to be in the set state.
When Q=0 and Q=1, it is said to be in the reset state.
EXERCISE IN LAB:
Fill in the following truth tables of SR latches for both NAND and NOR
implementation and draw the circuits from them:

IMPLEMENTATION WITH NOR

S R Q QBAR
1 0 1 0
0 0 Latch(Previous) Latch(Previous)

0 1 0 1
0 0 Latch(Previous) Latch(Previous)

1 1 Undefined Undefined

IMPLEMENTATION WITH NAND

S R Q QBAR
0 1 1 0
1 1 Latch(Previous) Latch(Previous)

1 0 0 1
1 1 Latch(Previous) Latch(Previous)

0 0 Undefined Undefined

CIRCUIT DIAGRAMS:
Draw the circuit diagrams for SR Latch with both NAND and NOR
implementations:

SR Latch with NOR gates and with NAND gates:

 2. IMPLEMENTATION OF SR LATCHES WITH CONTROL BIT

OBJECTIVES:
Implementation of SR latches with control bit

TASKS:
 Draw the circuit of SR latches using NAND with control bit.
 Implement the circuits and verify the results.


EQUIPMENT USED:
DEV-2771 Trainer, 74LS00 (NAND Gate)

BACKGROUND THEORY:
The operation of a basic NOR and NAND latches can be modified by providing
an addition control bit that determines when the state of the latch can be changed.

EXERCISE IN LAB:
Fill in the following truth tables of SR latches with a control bit.

IMPLEMENTATION WITH NAND AND CONTROL BIT

C S R Q QBAR
0 x X Latch Latch
1 0 0 Latch Latch
1 0 1 0 1
1 1 0 1 0
1 1 1 unstable unstable
CIRCUIT DIAGRAM:
Draw the circuit diagram for SR latch with a control bit with only NAND gates

3. Implementation of SR Flip Flop

OBJECTIVE:
Implementation & Verification of the functionality of SR FLIP FLOP

TASKS:
 Write The Truth Table for SR FLIP FLOP
 Design and implement the SR FLIP FLOP on the trainer.
 Verify the results with the truth table.
EQUIPMENT USED:
DEV-2771 Trainer, basic gates

BACKGROUND THEORY:
The SR flip flop consists of two latches and an inverter. When the clock input C is 0, the
output of the inverter is 1. The slave latch is enabled and its output Q is equal to
master output Y. The master latch is disabled, because C is 0.

EXERCISE IN LAB:
Fill in the truth table for SR FLIP FLOP

S R Next Sate of Q
0 0 Latch Previous
0 1 Reset
1 0 set
1 1 unstable

CIRCUIT DIAGRAM:
SR master-slave flip-flop
 LAB 10

Implementation of a D Latch & D FLIP FLOP

1. IMPLEMENTATION OF A D LATCH

OBJECTIVE:
Implementation & Verification of the functionality of a D Latch

TASKS:
 Write The Truth Table for a D Latch.
 Design and implement the D Latch on the trainer.
 Verify the results with the truth table.

EQUIPMENT USED:
DEV-2771 Trainer, NAND gates (741s00), NOT Gate (741s04)
BACKGROUND THEORY:
In order to eliminate the undesired state in the SR Latch is to ensure that inputs S & R
are never equal to 1 at the same time. This is done in the D Latch. This latch has only
two inputs: D (Data) & C (Control), the D Latch receives its designation from its ability
to hold data in its internal storage.

EXERCISE IN LAB:
Truth Table for D latch:

C D Q Q bar
0 X Latch
1 0 1 0
1 1 1 1

CIRCUIT DIAGRAM:
Draw the circuit for D latch

2. IMPLEMENTATION OF D FLIP FLOP

OBJECTIVE:
Implementation & Verification of the functionality of D FLIP FLOP

TASKS:
 Write The Truth Table for D FLIP FLOP
 Design and implement the D FLIP FLOP on the trainer.
 Verify the results with the truth table.

EQUIPMENT USED:
DEV-2771 Trainer, basic gates
BACKGROUND THEORY:
The D flip flop is almost the same as the SR flip flop but with a difference that it has
only two input, D(data) and C (clock).

EXERCISE IN LAB:
Fill in the truth table for DFLIP FLOP

D Next Sate of Q
0
1

CIRCUIT DIAGRAM:
Draw the circuit for D FLIP FLOP

LAB 11
Implementation of Toggle FLIP FLOP
OBJECTIVE:
Implementation & Verification of the functionality of Toggle FLIP FLOP

TASKS:
 Write The Truth Table for Toggle FLIP FLOP
 Design and implement the Toggle FLIP FLOP on the trainer.
 Verify the results with the truth table.

EQUIPMENT USED:
DEV-2771 Trainer, basic gates

BACKGROUND THEORY:
The output of the toggle flip flop only deals with two cases. First case is to maintain the
last state and other is to toggle the previous output.
EXERCISE IN LAB:
Fill in the truth table for T FLIP FLOP

T Next Sate of Q
0
1

CIRCUIT DIAGRAM:
Draw the circuit for Toggle FLIP FLOP

LAB 12

Implementation of JK Latch and FLIP FLOP

OBJECTIVE:
1. Implementation & Verification of the functionality of JK Latch

TASKS:
 Write The Truth Table for JK FLIP FLOP
 Design and implement the JK FLIP FLOP on the trainer.
 Verify the results with the truth table.

EQUIPMENT USED:
DEV-2771 Trainer, basic gates

BACKGROUND THEORY:
A modified version of the SR flip flop which eliminates the undesired condition that
leads to undefined outputs and undetermined behavior is JK flip flop.
EXERCISE IN LAB:
Fill in the truth table for JK FLIP FLOP

J K Next Sate of Q
0 0
0 1
1 0
1 1

CIRCUIT DIAGRAM:
Draw the circuit for JK FLIP FLOP

2. IMPLEMENTATION & VERIFICATION OF THE FUNCTIONALITY OF JK FLIP

FLOP

OBJECTIVE:
Implementation & Verification of state machine using JK FLIP FLOP

TASKS:
 Write The Truth Table for JK FLIP FLOP
 Write the excitation table for 2 bit JK flip flop
 Write the Transition table.
 Write the K-Map for all flip flops
 Write the equation from the table
 Design the circuit

EQUIPMENT USED:
DEV-2771 Trainer, 741s76 (JK flip flop), basic gates.
BACKGROUND THEORY:
The basic concept in the implementation if the state machine is that we should know
about the truth table, excitation table of the JK flip flop and transition table. This lab
contains almost all the concepts that have been taught during the DLD course.

EXERCISE IN LAB:
Following is the state machine that has to be implemented.

TRUTH TABLE FOR JK FLIP FLOP:

Fill in the following table for the JK flip Flop

J K Next Sate of Q
0 0
0 1
1 0
1 1

EXCITATION TABLE:
Fill in the following excitation table according to the truth table for JK flip flops

Q(t) Q(t+1) J K
0 0
0 1
1 0
1 1
TRANSITION TABLE:
Fill in the following transition table

P.State Input=x N.State JB KB JA KA Output

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

K-MAPS:
Fill in the following K-Maps for the following outputs

JB:

00 01 11 10
X_bar 0
X 1
KB:

00 01 11 10
X_bar 0
X 1
JA:

00 01 11 10
X_bar 0
X 1
KA:

00 01 11 10
X_bar 0
X 1
OUTPUT:

00 01 11 10
X_bar 0
X 1
EQUATIONS:
Write the equations derived from the K-Maps. Fill in the following Blanks.

JB: .

KB: .

JA: .

KA: .

Output: .

CIRCUIT DIAGRAM:
Draw the resulting circuit diagram from the equation give above:

LAB 13

Implementation of MAGNITUDE COMPARATOR

OBJECTIVE:

TO STUDY THE BEHAVIOR MAGNITUDE COMPARATOR.

TASKS:
 Write the Truth Table for Magnitude Comparator
 Design and implement the Magnitude Comparator on the trainer.
 Verify the results with the truth table.

EQUIPMENT USED:
DEV-2771 Trainer, basic gates Power supply, Breadboard. IC 7485, LEDs.

Pin Configuration:
BACKGROUND THEORY:
Magnitude comparator compares two binary data signals A & B and generates the
results of comparison in form of three output signals A>B, A=B, A<B. IC 7485 is a
4-bit comparator. The cascade inputs A>B, A=B, A<B can be used to construct a
comparator comparing more than 4 bits. The compare outputs depend on both
compare I/ps as well as cascade I/ps.
PROCEDURE
1) Give biasing to the IC.
2) Give various two 4-bit inputs and note down output.
3) Do connections for cascading and note down output for various two 8-bit
inputs.
OBSERVATION
TABLE

For 4-bit Comparator

A3 A2 Al AO B3 B2 Bl BO A>B A=B A<B
 CONCLUSION:

LAB 14

Implementation of 3-bit Asynchronous Counter

OBJECTIVE:

TO STUDY THE BEHAVIOR OF 3-BIT ASYNCHRONOUS COUNTER.

TASKS:
 Write the Truth Table for 3-BIT ASYNCHRONOUS COUNTER
 Design and implement the 3-BIT ASYNCHRONOUS COUNTER on the trainer.
 Verify the results with the truth table.

EQUIPMENT USED:
DEV-2771 Trainer, basic gates Power supply, Breadboard. ICs 7476, 7490, LEDs.

Pin Configuration:
Circuit Diagram:
THEORY:
A circuit used for counting the pulses is known as counter. Basically, there are two types
of counters.
l)Asynchronous counter (ripple counter).
2)Synchronous counter.
Asynchronous counter:
In the case of an Asynchronous Counter, all the flip-flops are not clocked
simultaneously. This counter is simple in operation & requires a min. of hardware.
But its speed is low. Each FF is triggered by a previous FF o/p. Each FF takes its own
time to give o/p (due to propagation delay). So final settling time is high. They have
the problem of glitch.
Synchronous counter:
In synchronous counters all the Ffs are clocked simultaneously. It is complex in
construction, but speed is more. In this case since each FF is clocked simultaneously
thus settling time is the delay time of single FF. No problem of glitch.
Asynchronous counter IC (749O):
It is a BCD counter. It consists of four FFs internally connected to provide a mod-2
counter and a mod-5 counter. The mod-2 and mod-5 counters can be used
independently or in combination. FFA operates as a mod2 counter whereas the
combination of FFB, FFC and FFD form a mod-5 counter. There are two reset inputs
R1 & R2 both of which are to be connected to logic 1 level for clearing all the FFs.
The two set inputs S1 & S2 when connected to logic1 level are used for setting the
counter to 1001.

PROCEDURE:
1) Do connections as per the circuit diagram.
2)Give biasing to the ICs.
3)Observe o/p using LEDs.
OBSERVATIONS:
Counter State QO Ql Q2

CONCLUSION:
Feed Back by Students