KARTHIK.

S
ADSD PROBLEM SHEET 1
KARTHIK.S

1A. The diagram shows three gates in which one input (CONTROL) is being used to 1 D Y
1D
modify a signal at the other input (DATA). Complete the timing diagram by drawing C
C1
the waveforms of X, Y and Z. Describe in words the effect each of the gates has on
DATA when CONTROL is low and when it is high.
DATA DATA DATA
& ≥1 =1
X Y Z
CONTROL CONTROL CONTROL 5B. The circuits below are a D-latch and a D-flipflop with their outputs connected to their
inputs via an inverter. Draw the waveforms of X and Y assuming that they are both low
initially and that C is a uniform square wave. (One of these circuits is a disaster and
should never be used)
DATA
CONTROL

1 X
1 Y
1D 1D
2B. The symbol in a gate generally indicates how many of the inputs need to be high to C C
C1 C1
make the output high. Guess the truth tables of the following gates from their symbols.
Explain why any one of them could be considered as a 3-input XOR gate.
A 2n+1 A = A =1
B P B Q B R 6B. In the circuit below the propagation delay of the flipflops may vary between 4 and 7 ns
C C C while the propagation delay of the gates may vary between 2 and 6 ns.
Calculate the minimum and the maximum propagation delays from each of A and C to
each of P, Q and R and S.
3A. The circuits below are a D-latch and a D-flipflop. Complete the timing diagram by
drawing the waveforms of X and Y assuming that they are both low initially.
&
S
A P Q R
1D 1 1D
C
C1 C1
D X D Y
1D 1D C
C C
C1 C1 D

7C. In the circuit below the setup and hold times of the flipflops are 5 ns and 1 ns
respectively. The propagation delay of the flipflops may vary between 4 and 7 ns while
4B. The circuit below forms a ÷2 counter. If the inverter has a propagation delay of 5 ns the propagation delay of the gates may vary between 2 and 6 ns.
and the propagation delay, setup time and hold time of the flipflop are 8 ns, 4 ns and
2 ns respectively, calculate the highest clock frequency for reliable operation. Calculate the minimum and the maximum propagation delays between C and U. Hence
calculate the maximum frequency of the clock, C.

Rev: Oct-06 Digital Electronics II: Problem Sheet 1 Page 1

 KARTHIK.S
SET
≥1
N
A P
1
&
S
SET Q
S

R RESET
R
N
SET
& &
U
≥1
Q

&
B Q T V RESET RESET
1D 1D
C
C1 C1

10A. The springing contacts in switches always bounce when they close and sometimes do
so when they open as well. This contact bounce can last for several milliseconds. An
SR-latch can be used to debounce switch signals in the following circuit. Complete the
8C. In the six circuits below the setup and hold times of the flipflops are 5 ns and 1 ns timing diagram by drawing the waveform of Q.
respectively. The propagation delay of the flipflops may vary between 4 and 7 ns while
the propagation delay of the gates may vary between 2 and 6 ns. The signal C is a 0
UP Q
symmetrical square wave. S
1
Write down the setup and hold inequalities that relate to the second flipflop in each DOWN
R
UP
circuit. You should measure all times from the rising edge of CLOCK. Identify which 0 DOWN
of the circuits will not work reliably and determine the maximum clock frequency for
each of the others.
11C. The circuit shows a circuit to indicate who pressed their button first in a 2-contestant
(a) (b) game show. Design a similar circuit for a 3-contestant game show. The SR-latches use
D
1D 1D
D
1D 1 1D
the circuit from question 9.
C C
C1 C1 C1 C1
team A
1 BUTTONA LIGHTA
(c) (d) S
0
D
1D 1D
D
1D 1D
team B
≥1 R
C C
1 C1 C1 C1 1 C1 0

clear
(e) (f) BUTTONB LIGHTB
D 0 S
D 1
1D 1D 1D 1D
C
1 C1 C1
C
C1 1 C1
≥1 R

9B. The dual NOR-gate circuit shown below is called a Set-Reset latch and has the symbol
shown at right. Complete the timing diagram by showing the waveforms of Q and N
assuming that Q is initially low.
If SET and RESET are both high, say which one of these inputs dominates as far as Q
is concerned and as far as N is concerned.