LTC2308

Low Noise, 500ksps,

8-Channel, 12-Bit ADC
FEATURES DESCRIPTION
n 12-Bit Resolution The LTC®2308 is a low noise, 500ksps, 8-channel, 12-bit
n 500ksps Sampling Rate ADC with an SPI/MICROWIRE compatible serial interface.
n Low Noise: SINAD = 73.3dB This ADC includes an internal reference and a fully differ-
n Guaranteed No Missing Codes ential sample-and-hold circuit to reduce common mode
n Single 5V Supply noise. The internal conversion clock allows the external
n Auto-Shutdown Scales Supply Current with Sample serial output data clock (SCK) to operate at any frequency
Rate up to 40MHz.
n Low Power: 17.5mW at 500ksps
The LTC2308 operates from a single 5V supply and draws
0.9mW Nap Mode
just 3.5mA at a sample rate of 500ksps. The auto-shutdown
35μW Sleep Mode
n
feature reduces the supply current to 200μA at a sample
Internal Reference
n
rate of 1ksps.
Internal 8-Channel Multiplexer
n Internal Conversion Clock The LTC2308 is packaged in a small 24-pin 4mm × 4mm
n SPI/MICROWIRETM Compatible Serial Interface QFN. The internal 2.5V reference and 8-channel multiplexer
n Unipolar or Bipolar Input Ranges (Software Selectable) further reduce PCB board space requirements.
n Separate Output Supply OVDD (2.7V to 5.25V) The low power consumption and small size make the
n 24-Pin 4mm × 4mm QFN Package LTC2308 ideal for battery operated and portable appli-
APPLICATIONS cations, while the 4-wire SPI compatible serial interface
makes this ADC a good match for isolated or remote data
n High Speed Data Acquisition acquisition systems.
n Industrial Process Control L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
n Motor Control All other trademarks are the property of their respective owners.

n Accelerometer Measurements
n Battery Operated Instruments
n Isolated and/or Remote Data Acquisition

TYPICAL APPLICATION
5V

0.1μF 10μF 10μF 0.1μF

8192 Point FFT, fIN = 1kHz
0
–10 fSMPL = 500kHz
AVDD DVDD OVDD 2.7V TO 5.25 V SINAD = 73.6dB
CH0 –20
0.1μF THD = –89.5dB
LTC2308 –30
CH1
–40
MAGNITUDE (dB)

CH2 –50
SDI
CH3 ANALOG + 12-BIT –60
CH0-CH7 SERIAL SDO SERIAL DATA LINK TO
INPUT 500ksps –70
ASIC, PLD, MPU, DSP
ANALOG INPUTS CH4 MUX – ADC PORT
SCK OR SHIFT REGISTER –80
0V TO 4.096V UNIPOLAR
CH5 –90
±2.048V BIPOLAR CONVST
–100
CH6
VREF –110
CH7 INTERNAL 2.2μF –120
COM 2.5V REF –130
–140
0 50 100 150 200 250
FREQUENCY (kHz)
REFCOMP
2308 TA01b
GND 0.1μF 10μF
2308 TA01

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LTC2308
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
Supply Voltage (AVDD, DVDD, OVDD) ...........................6V

DVDD

OVDD
GND
CH2
CH1
CH0
Analog Input Voltage (Note 3)
CH0-CH7, COM, REF, 24 23 22 21 20 19

REFCOMP ...................(GND – 0.3V) to (AVDD + 0.3V) CH3 1 18 GND

CH4 2 17 SD0
Digital Input Voltage
CH5 3 16 SCK
(Note 3).......................... (GND – 0.3V) to (DVDD + 0.3V) 25
CH6 4 15 SDI
Digital Output Voltage .... (GND – 0.3V) to (OVDD + 0.3V) CH7 5 14 CONVST
Power Dissipation ...............................................500mW COM 6 13 AVDD
Operating Temperature Range 7 8 9 10 11 12
LTC2308C ................................................ 0°C to 70°C

VREF
REFCOMP
GND
GND
GND
AVDD
LTC2308I.............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
UF PACKAGE
24-LEAD (4mm s 4mm) PLASTIC QFN
TJMAX = 150°C, θJA = 37°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2308CUF#PBF LTC2308CUF#TRPBF 2308 24-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C
LTC2308IUF#PBF LTC2308IUF#TRPBF 2308 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

CONVERTER AND MULTIPLEXER CHARACTERISTICS The l denotes the specifications

which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 4, 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) l 12 Bits
Integral Linearity Error (Note 6) l ±0.3 ±1 LSB
Differential Linearity Error l ±0.25 ±1 LSB
Bipolar Zero Error (Note 7) l ±1 ±6 LSB
Bipolar Zero Error Drift 0.002 LSB/°C
Bipolar Zero Error Match l ±0.3 ±3 LSB
Unipolar Zero Error (Note 7) l ±0.5 ±3 LSB
Unipolar Zero Error Drift 0.002 LSB/°C
Unipolar Zero Error Match l ±0.3 ±2 LSB

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 LTC2308
CONVERTER AND MULTIPLEXER CHARACTERISTICS The l denotes the specifications
which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 4, 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Bipolar Full-Scale Error External Reference (Note 8) l ±1 ±9 LSB
Bipolar Full-Scale Error Drift External Reference 0.05 LSB/°C
Bipolar Full-Scale Error Match l ±0.5 ±3 LSB
Unipolar Full-Scale Error External Reference (Note 8) l ±1.5 ±8 LSB
Unipolar Full-Scale Error Drift External Reference 0.05 LSB/°C
Unipolar Full-Scale Error Match l ±0.4 ±3 LSB

ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN + Absolute Input Range (CH0 to CH7) (Note 9) l –0.05 REFCOMP V
VIN– Absolute Input Range (CH0 to CH7, Unipolar (Note 9) l –0.05 0.25 • REFCOMP V
COM) Bipolar (Note 9) l –0.05 0.75 • REFCOMP V
VIN+ – VIN– Input Differential Voltage Range VIN = VIN+ – VIN– (Unipolar) l 0 to REFCOMP V
VIN = VIN+ – VIN– (Bipolar) l ±REFCOMP/2 V
IIN Analog Input Leakage Current l ±1 μA
CIN Analog Input Capacitance Sample Mode 55 pF
Hold Mode 5 pF
CMRR Input Common Mode Rejection Ratio 70 dB

DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 10)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + Distortion) Ratio fIN = 1kHz l 71 73.3 dB
SNR Signal-to-Noise Ratio fIN = 1kHz l 71 73.4 dB
THD Total Harmonic Distortion fIN = 1kHz, First 5 Harmonics l –90 –78 dB
SFDR Spurious Free Dynamic Range fIN = 1kHz l 80 90 dB
Channel-to-Channel Isolation fIN = 1kHz –109 dB
Full Linear Bandwidth (Note 11) 700 kHz
–3dB Input Linear Bandwidth 25 MHz
Aperture Delay 13 ns
Transient Reponse Full-Scale Step 240 ns

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LTC2308
INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Output Voltage IOUT = 0 l 2.47 2.50 2.53 V
VREF Output Tempco IOUT = 0 ±25 ppm/°C
VREF Output Impedance –0.1mA ≤ IOUT ≤ 0.1mA 8 kΩ
VREFCOMP Output Voltage IOUT = 0 4.096 V
VREF Line Regulation AVDD = 4.75V to 5.25V 0.8 mV/V

DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage DVDD = 5.25V l 2.4 V
VIL Low Level Input Voltage DVDD = 4.75V l 0.8 V
IIN High Level Input Current VIN = VDD l ±10 μA
CIN Digital Input Capacitance 5 pF
VOH High Level Output Voltage OVDD = 4.75V, IOUT = –10μA 4.74 V
OVDD = 4.75V, IOUT = –200μA l 4 V
VOL Low Level Input Voltage OVDD = 4.75V, IOUT = 160μA 0.05 V
OVDD = 4.75V, IOUT = 1.6mA l 0.4 V
IOZ Hi-Z Output Leakage VOUT = 0V to OVDD, CONVST High l ±10 μA
COZ Hi-Z Output Capacitance CONVST High 15 pF
ISOURCE Output Source Current VOUT = 0V –10 mA
ISINK Output Sink Current VOUT = OVDD 10 mA

POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
AVDD Analog Supply Voltage 4.75 5 5.25 V
DVDD Digital Supply Voltage 4.75 5 5.25 V
OVDD Output Driver Supply Voltage 2.7 5.25 V
IDD Supply Current CL = 25pF l 3.5 4.2 mA
Nap Mode CONVST = 5V, Conversion Done l 180 400 μA
Sleep Mode CONVST = 5V, Conversion Done l 7 20 μA
PD Power Dissipation 17.5 mW
Nap Mode 0.9 mW
Sleep Mode 35 μW

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 LTC2308
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL(MAX) Maximum Sampling Frequency l 500 kHz
fSCK Shift Clock Frequency l 40 MHz
tWHCONV CONVST High Time (Note 9) l 20 ns
tHD Hold Time SDI After SCK↑ l 2.5 ns
tSUDI Setup Time SDI Valid Before SCK↑ l 0 ns
tWHCLK SCK High Time fSCK = fSCK(MAX) l 10 ns
tWLCLK SCK Low Time fSCK = fSCK(MAX) l 10 ns
tWLCONVST CONVST Low Time During Data Transfer (Note 9) l 410 ns
tHCONVST Hold Time CONVST Low After Last SCK↓ (Note 9) l 20 ns
tCONV Conversion Time l 1.3 1.6 μs
tACQ Acquisition Time 7th SCK↑ to CONVST↑ (Note 9) l 240 ns
tREFWAKE REFCOMP Wakeup Time (Note 12) CREFCOMP = 10μF, CREF = 2.2μF 200 ms
tdDO SDO Data Valid After SCK↓ CL = 25pF (Note 9) l 10.8 12.5 ns
thDO SDO Hold Time After SCK↓ CL = 25pF l 4 ns
ten SDO Valid After CONVST↓ CL = 25pF l 11 15 ns
tdis Bus Relinquish Time CL = 25pF l 11 15 ns
tr SDO Rise Time CL = 25pF 4 ns
tf SDO Fall Time CL = 25pF 4 ns
tCYC Total Cycle Time 2 μs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
may cause permanent damage to the device. Exposure to any Absolute when the output code flickers between 0000 0000 0000 and 1111 1111
Maximum Rating condition for extended periods may affect device 1111. Unipolar zero error is the offset voltage measured from +0.5LSB
reliability and lifetime. when the output code flickers between 0000 0000 0000 and
Note 2: All voltage values are with respect to ground with AVDD, DVDD and 0000 0000 0001.
OVDD wired together (unless otherwise noted). Note 8: Full-scale bipolar error is the worst-case of –FS or +FS untrimmed
Note 3: When these pin voltages are taken below ground or above VDD, deviation from ideal first and last code transitions and includes the effect
they will be clamped by internal diodes. These products can handle input of offset error. Unipolar full-scale error is the deviation of the last code
currents greater than 100mA below ground or above VDD without latchup. transition from ideal and includes the effect of offset error.
Note 4: AVDD = 5V, DVDD = 5V, OVDD = 5V, fSMPL = 500kHz, internal Note 9: Guaranteed by design, not subject to test.
reference unless otherwise specified. Note 10: All specifications in dB are referred to a full-scale ±2.048V input
Note 5: Linearity, offset and full-scale specifications apply for a single- with a 2.5V reference voltage.
ended analog input with respect to COM. Note 11: Full linear bandwidth is defined as the full-scale input frequency
Note 6: Integral nonlinearity is defined as the deviation of a code from a at which the SINAD degrades to 60dB or 10 bits of accuracy.
straight line passing through the actual endpoints of the transfer curve. Note 12: REFCOMP wakeup time is the time required for the REFCOMP pin
The deviation is measured from the center of the quantization band. to settle within 0.5LSB at 12-bit resolution of its final value after waking up
from SLEEP mode.

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LTC2308
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, AVDD = DVDD = OVDD = 5V,
fSMPL = 500ksps, Internal Reference, unless otherwise noted.

Integral Nonlinearity vs Differential Nonlinearity vs 1kHz Sine Wave

Output Code Output Code 8192 Point FFT Plot
1.00 1.00 0
–10 SNR = 73.7dB
0.75 0.75 SINAD = 73.6dB
–20 THD = –89.5dB
–30
0.50 0.50
–40

MAGNITUDE (dB)
0.25 0.25 –50
INL (LSB)

DNL (LSB)
–60
0 0 –70
–80
–0.25 –0.25 –90
–100
–0.50 –0.50
–110
–0.75 –0.75 –120
–130
–1.00 –1.00 –140
0 1024 2048 3072 4096 0 1024 2048 3072 4096 0 50 100 150 200 250
OUTPUT CODE OUTPUT CODE FREQUENCY (kHz)
2308 G01 2308 G02 2308 G03

Crosstalk vs Frequency for

an Adjacent Pair SNR vs Input Frequency SINAD vs Input Frequency
–60 80 80

–70
75 75
–80
CROSSTALK (dB)

70 70
–90 SINAD (dB)
SNR (dB)

–100 65 65

–110
60 60
–120
55 55
–130

–140 50 50
0.1 1 10 100 1000 1 10 100 1000 1 10 100 1000
FREQUENCY (kHz) FREQUENCY (kHz) FREQUENCY (kHz)
3208 G04
3208 G05 3208 G06

Supply Current vs
THD vs Input Frequency Sampling Frequency Supply Current vs Temperature
–60 3.5 5

–65 3.0
4
–70
SUPPLY CURRENT (mA)

SUPPLY CURRENT (mA)

2.5
–75 3
THD (dB)

2.0
–80
1.5
2
–85
1.0
–90
1
–95 0.5

–100 0 0
1 10 100 1000 1 10 100 1000 –50 –25 0 25 50 75 100 125
FREQUENCY (kHz) SAMPLING FREQUENCY (ksps) TEMPERATURE (oC)
3208 G07 3208 G08 3208 G09

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 LTC2308
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, AVDD = DVDD = OVDD = 5V,
fSMPL = 500ksps, Internal Reference, unless otherwise noted.

Analog Input Leakage Current vs

Sleep Current vs Temperature Temperature
10 1000
fSMPL = 0ksps

8 800

LEAKAGE CURRENT (nA)

SLEEP CURRENT (μA)

6 600

CH (ON)
4 400
CH (OFF)
2 200

0 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
3208 G10 3208 G11

Offset vs Temperature Full-Scale Error vs Temperature

1.5 4

2
FULL-SCALE ERROR (LSB)

BIPOLAR
1.0 BIPOLAR
OFFSET (LSB)

0
UNIPOLAR
UNIPOLAR
–2
0.5

–4

EXTERNAL REFERENCE EXTERNAL REFERENCE

0 –6
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
2308 G12 2308 G13

PIN FUNCTIONS
CH3-CH7 (Pins 1, 2, 3, 4, 5): Channel 3 to Channel 7 capacitor. The internal reference may be over driven by an
Analog Inputs. CH3-CH7 can be configured as single- external 2.5V reference at this pin.
ended or differential input channels. See the Analog Input
REFCOMP (Pin 8): Reference Buffer Output. Bypass to
Multiplexer section.
GND with a 10μF tantalum and 0.1μF ceramic capacitor
COM (Pin 6): Common Input. This is the reference point in parallel. Nominal output voltage is 4.096V. The internal
for all single-ended inputs. It must be free of noise and reference buffer driving this pin is disabled by grounding
connected to ground for unipolar conversions and midway VREF , allowing REFCOMP to be overdriven by an external
between GND and REFCOMP for bipolar conversions. source (see Figure 6c).
VREF (Pin 7): 2.5V Reference Output. Bypass to GND with GND (Pins 9, 10, 11, 18, 20): Ground. All GND pins must
a minimum 2.2μF tantalum capacitor or low ESR ceramic be connected to a solid ground plane.
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LTC2308
PIN FUNCTIONS
AVDD (Pins 12, 13): 5V Analog Supply. The range of AVDD is SDO (Pin 17): Serial Data Out. SDO outputs the data from
4.75V to 5.25V. Bypass AVDD to GND with a 0.1μF ceramic the previous conversion. SDO is shifted out serially on the
and a 10μF tantalum capacitor in parallel. falling edge of each SCK pulse.
CONVST (Pin 14): Conversion Start. A rising edge at OVDD (Pin 19): Output Driver Supply. Bypass OVDD to
CONVST begins a conversion. For best performance, ensure GND with a 0.1μF ceramic capacitor close to the pin. The
that CONVST returns low within 40ns after the conversion range of OVDD is 2.7V to 5.25V.
starts or after the conversion ends.
DVDD (Pin 21): 5V Digital Supply. The range of DVDD is
SDI (Pin 15): Serial Data Input. The SDI serial bit stream 4.75V to 5.25V. Bypass DVDD to GND with a 0.1 μF ceramic
configures the ADC and is latched on the rising edge of and a 10μF tantalum capacitor in parallel.
the first 6 SCK pulses.
CH0-CH2 (Pins 22, 23, 24): Channel 0 to Channel 2
SCK (Pin 16): Serial Data Clock. SCK synchronizes the Analog Inputs. CH0-CH2 can be configured as single-
serial data transfer. The serial data input at SDI is latched ended or differential input channels. See the Analog Input
on the rising edge of SCK. The serial data output at SDO Multiplexer section.
transitions on the falling edge of SCK.
GND (Pin 25): Exposed Pad Ground. Must be soldered
directly to ground plane.

BLOCK DIAGRAM
AVDD DVDD OVDD

CH0 LTC2308

CH1
CH2
SDI
CH3 ANALOG + 12-BIT
SERIAL SDO
INPUT 500ksps
CH4 MUX – ADC PORT
SCK
CH5
CONVST
CH6
VREF
CH7 8k
INTERNAL
COM 2.5V REF

GAIN = 1.6384x

REFCOMP
2308 BD

GND

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 LTC2308
TEST CIRCUIT
Load Circuit for tdis WAVEFORM 1 Load Circuit for tdis WAVEFORM 2, ten

VDD

3k
SDO TEST POINT
SDO TEST POINT CL
3k
CL 2308 TC02

2308 TC01

TIMING DIAGRAM
Voltage Waveforms for SDO Delay Times, tdDO and thDO tWLCLK (SCK Low Time)
tWHCLK (SCK High Time)
tHD (Hold Time SDI After SCK↑)
SCK tSUDI (Setup Time SDI Stable Before SCK↑)
VIL
tdDO
tWLCLK tWHCLK
thDO
VOH
SDO SCK
VOL
tHD
2308 TD01
SDI

tSUDI 2308 TD03

Voltage Waveforms for tdis

Voltage Waveforms for ten

CONVST VIH

CONVST
SDO 90%
WAVEFORM 1
(SEE NOTE 1) SDO 2308 TD04
tdis
SDO ten
WAVEFORM 2
10%
(SEE NOTE 2)
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH Voltage Waveforms for SDO Rise and Fall Times tr, tf
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
2308 TD02

VOH
SDO
VOL

tr tf 2308 TD05

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LTC2308
APPLICATIONS INFORMATION
Overview S/D O/S S1 S0 UNI SLP
The LTC2308 is a low noise, 500ksps, 8-channel, 12-bit
successive approximation register (SAR) A/D converter. S/D = SINGLE-ENDED/DIFFERENTIAL BIT
The LTC2308 includes a precision internal reference, a O/S = ODD/SIGN BIT
configurable 8-channel analog input multiplexer (MUX)
and an SPI-compatible serial port for easy data transfers. S1 = ADDRESS SELECT BIT 1
The ADC may be configured to accept single-ended or S0 = ADDRESS SELECT BIT 0
differential signals and can operate in either unipolar or
UNI = UNIPOLAR/BIPOLAR BIT
bipolar mode. A sleep mode option is also provided to
save power during inactive periods. SLP = SLEEP MODE BIT
Conversions are initiated by a rising edge on the CONVST Analog Input Multiplexer
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, a 6-bit input word (DIN) The analog input MUX is programmed by the S/D, O/S,
at the SDI input configures the MUX and programs vari- S1 and S0 bits of the DIN word. Table 1 lists the MUX
ous modes of operation. As the DIN bits are shifted in, configurations for all combinations of the configuration
data from the previous conversion is shifted out on SDO. bits. Figure 1a shows several possible MUX configurations
After the 6 bits of the DIN word have been shifted in, the and Figure 1b shows how the MUX can be reconfigured
ADC begins acquiring the analog input in preparation for from one conversion to the next.
the next conversion as the rest of the data is shifted out.
Table 1. Channel Configuration
The acquire phase requires a minimum time of 240ns
S/D O/S S1 S0 0 1 2 3 4 5 6 7 COM
for the sample-and-hold capacitors to acquire the analog
0 0 0 0 + –
input signal.
0 0 0 1 + –
During the conversion, the internal 12-bit capacitive 0 0 1 0 + –
charge-redistribution DAC output is sequenced through a
0 0 1 1 + –
successive approximation algorithm by the SAR starting
0 1 0 0 – +
from the most significant bit (MSB) to the least significant
0 1 0 1 – +
bit (LSB). The sampled input is successively compared
0 1 1 0 – +
with binary weighted charges supplied by the capacitive
DAC using a differential comparator. At the end of a conver- 0 1 1 1 – +
sion, the DAC output balances the analog input. The SAR 1 0 0 0 + –
contents (a 12-bit data word) that represent the sampled 1 0 0 1 + –
analog input are loaded into 12 output latches that allow 1 0 1 0 + –
the data to be shifted out. 1 0 1 1 + –
1 1 0 0 + –
Programming the LTC2308 1 1 0 1 + –
The various modes of operation of the LTC2308 are 1 1 1 0 + –
programmed by a 6-bit DIN word. The SDI data bits are 1 1 1 1 + –
loaded on the rising edge of SCK, with the S/D bit loaded
on the first rising edge and the SLP bit on the sixth rising
edge (see Figure 8 in the Timing and Control section). The
input data word is defined as follows:

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 LTC2308
APPLICATIONS INFORMATION
4 Differential 8 Single-Ended Unipolar Mode Bipolar Mode
+ (–) CH0 + CH0
– (+) { CH1 + CH1
+ CH2
+ (–) CH2 +
– (+) {
CH3
CH3 + CH4
+ (–) CH4 + CH5
– (+) { CH5 + CH6
COM
+ CH7 COM
+ (–) CH6 REFCOMP/2 +
– (+) { CH7 COM (–)
– 2308 F02

Figure 2. Driving COM in UNIPOLAR and BIPOLAR Modes

Combinations of Differential
and Single-Ended
mode. In conversion mode, the analog inputs draw only
+ CH0
a small leakage current. If the source impedance of the
–{ CH1
driving circuit is low, the ADC inputs can be driven directly.
– CH2
+{ CH3 Otherwise, more acquisition time should be allowed for a
+ CH4 source with higher impedance.
+ CH5
+ CH6
+ CH7 Input Filtering
COM (–)
2308 F01a The noise and distortion of the input amplifier and other
circuitry must be considered since they will add to the
Figure 1a. Example MUX Configurations
ADC noise and distortion. Therefore, noisy input circuitry
1st Conversion 2nd Conversion should be filtered prior to the analog inputs to minimize
noise. A simple 1-pole RC filter is sufficient for many
applications.
+ CH2 – CH2
–{ CH3 + { CH3 The analog inputs of the LTC2308 can be modeled as
+ CH4 + CH4 a 55pF capacitor (CIN) in series with a 100Ω resistor
–{ CH5 + { CH5
COM
(RON) as shown in Figure 3a. CIN gets switched to the
COM (–)
(UNUSED) selected input once during each conversion. Large filter
2308 F01b RC time constants will slow the settling of the inputs. It
Figure 1b. Changing the MUX Assignment “On the Fly” is important that the overall RC time constants be short
enough to allow the analog inputs to completely settle to
Driving the Analog Inputs 12-bit resolution within the acquisition time (tACQ) if DC
accuracy is important.
The analog inputs of the LTC2308 are easy to drive. Each
of the analog inputs can be used as a single-ended input When using a filter with a large CFILTER value (e.g. 1μF),
relative to the COM pin (CH0-COM, CH1-COM, etc.) or in the inputs do not completely settle and the capacitive input
differential input pairs (CH0 and CH1, CH2 and CH3, CH4 switching currents are averaged into a net DC current
and CH5, CH6 and CH7). Figure 2 shows how to drive COM (IDC). In this case, the analog input can be modeled by an
for single-ended inputs in unipolar and bipolar modes. equivalent resistance (REQ = 1/(fSMPL • CIN)) in series with
Regardless of the MUX configuration, the “+” and “–” an ideal voltage source (VREFCOMP/2) as shown in Figure 3b.
inputs are sampled at the same instant. Any unwanted The magnitude of the DC current is then approximately
signal that is common to both inputs will be reduced by IDC = (VIN – VREFCOMP/2)/REQ, which is roughly propor-
the common mode rejection of the sample-and-hold circuit. tional to VIN. To prevent large DC drops across the resistor
The inputs draw only one small current spike while charg- RFILTER, a filter with a small resistor and large capacitor
ing the sample-and-hold capacitors during the acquire should be chosen. When running at the minimum cycle
2308fb

11
LTC2308
APPLICATIONS INFORMATION
INPUT LTC2308 ANALOG 50Ω
RON CH0
RSOURCE CH0-CH7 INPUT
100Ω LTC2308
VIN 2000pF
CIN
C1 55pF COM

2308 F03a
REFCOMP
10μF 0.1μF
2308 F04a
Figure 3a. Analog Input Equivalent Circuit

Figure 4a. Optional RC Input Filtering for Single-Ended Input

INPUT
IDC CH0-CH7
RFILTER
LTC2308
VIN 1000pF
REQ 50Ω
CFILTER 1/(fSMPL • CIN) CH0
DIFFERENTIAL LTC2308
+ VREFCOMP/2 ANALOG 1000pF
– INPUTS 50Ω
CH1
2308 F03b
1000pF

Figure 3b. Analog Input Equivalent Circuit REFCOMP

for Large Filter Capacitances 10μF 0.1μF
2308 F04b

time of 2μs, the input current equals 106μA at VIN = 5V, Figure 4b. Optional RC Input Filtering for Differential Inputs
which amounts to a full-scale error of 0.5LSBs when using
a filter resistor (RFILTER) of 4.7Ω. Applications requiring Signal-to-Noise and Distortion Ratio (SINAD)
lower sample rates can tolerate a larger filter resistor for The signal-to-noise and distortion ratio (SINAD) is the
the same amount of full-scale error. ratio between the RMS amplitude of the fundamental input
Figures 4a and 4b show respective examples of input frequency to the RMS amplitude of all other frequency
filtering for single-ended and differential inputs. For the components at the A/D output. The output is band-limited
single-ended case in Figure 4a, a 50Ω source resistor to frequencies from above DC and below half the sampling
and a 2000pF capacitor to ground on the input will limit frequency. Figure 5 shows a typical SINAD of 73.3dB with
the input bandwidth to 1.6MHz. High quality capacitors a 500kHz sampling rate and a 1kHz input. A SNR of 73.4dB
and resistors should be used in the RC filter since these can be achieved with the LTC2308.
components can add distortion. NPO and silver mica type
0
dielectric capacitors have excellent linearity. Carbon surface –10
mount resistors can generate distortion from self heating –20
–30
and from damage that may occur during soldering. Metal –40
film surface mount resistors are much less susceptible
MAGNITUDE (dB)

–50
–60
to both problems. –70
–80
Dynamic Performance –90
–100
–110
FFT (Fast Fourier Transform) test techniques are used to –120
test the ADC’s frequency response, distortion and noise –130
at the rated throughput. By applying a low distortion –140
0 50 100 150 200 250
sine wave and analyzing the digital output using an FFT FREQUENCY (kHz)

algorithm, the ADC’s spectral content can be examined 2308 TA01b

for frequencies outside the fundamental. Figure 5. 1kHz Sine Wave 8192 Point FFT Plot

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12
 LTC2308
APPLICATIONS INFORMATION
Total Harmonic Distortion (THD) R1
VREF 8k BANDGAP
Total Harmonic Distortion (THD) is the ratio of the RMS 2.5V
REFERENCE
2.2μF
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency 4.096V REFCOMP
REFERENCE
band between DC and half the sampling frequency(fSMPL/2). AMP

THD is expressed as: 10μF

R2

V22 + V32 + V42... + VN2

0.1μF
GND R3
THD = 20 log LTC2308
V1
2308 F06a

where V1 is the RMS amplitude of the fundamental fre- Figure 6a. LTC2308 Reference Circuit
quency and V2 through VN are the amplitudes of the second
through Nth harmonics. 5V

0.1MF
Internal Reference VIN

LT1790A-2.5
The LTC2308 has an on-chip, temperature compensated VOUT VREF
bandgap reference that is factory trimmed to 2.5V (Refer 2.2μF
LTC2308
to Figure 6a). It is internally connected to a reference REFCOMP
amplifier and is available at VREF (Pin 7). VREF should +
10μF 0.1μF
be bypassed to GND with a 2.2μF tantalum capacitor GND
to minimize noise. An 8k resistor is in series with the
2308 F06b
output so that it can be easily overdriven by an external
reference if more accuracy and/or lower drift are required Figure 6b. Using the LT1790A-2.5 as an External Reference
as shown in Figure 6b. The reference amplifier gains the
5V
VREF voltage by 1.638 to 4.096V at REFCOMP (Pin 8). To
compensate the reference amplifier, bypass REFCOMP VIN VREF

with a 10μF ceramic or tantalum capacitor in parallel with LT1790A-4.096

LTC2308

a 0.1μF ceramic capacitor for best noise performance. The VOUT REFCOMP
+
internal reference buffer can also be overdriven from 1V 10μF 0.1μF
to AVDD with an external reference at REFCOMP as shown GND
in Figure 6c. To do so VREF must be grounded to disable 2308 F06c

the reference buffer. This will result in an input range of

Figure 6c. Overdriving REFCOMP Using the LT1790A-4.096
0V to VREFCOMP in unipolar mode and ±0.5 • VREFCOMP in
bipolar mode.
Digital Interface
Internal Conversion Clock
The LTC2308 communicates via a standard 4-wire SPI
The internal conversion clock is factory trimmed to compatible digital interface. The rising edge of CONVST
achieve a typical conversion time (tCONV) of 1.3μs and a initiates a conversion. After the conversion is finished, pull
maximum conversion time of 1.6μs over the full operat- CONVST low to enable the serial output (SDO). The ADC
ing temperature range. With a typical acquisition time of shifts out the digital data in 2’s complement format when
240ns, a throughput sampling rate of 500ksps is tested operating in bipolar mode or in straight binary format when
and guaranteed. in unipolar mode, based on the setting of the UNI bit.

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13
LTC2308
APPLICATIONS INFORMATION
For best performance, ensure that CONVST returns low Nap Mode
within 40ns after the conversion starts (i.e., before the first
The ADC enters nap mode when CONVST is held high
bit decision) or after the conversion ends. If CONVST is
after the conversion is complete (tCONV) if the SLP bit is
low when the conversion ends, the MSB bit will appear at set to a logic 0. The supply current decreases to 180μA
SDO at the end of the conversion and the ADC will remain in nap mode between conversions, thereby reducing the
powered up. average power dissipation as the sample rate decreases.
For example, the LTC2308 draws an average of 200μA
Timing and Control
with a 1ksps sampling rate. The LTC2308 keeps only the
The start of a conversion is triggered by a rising edge at reference(VREF) and reference buffer(REFCOMP) circuitry
CONVST. Once initiated, a new conversion cannot be re- active when in nap mode.
started until the current conversion is complete. Figures 8
and 9 show the timing diagrams for two different examples Sleep Mode
of CONVST pulses. Example 1 (Figure 8) shows CONVST The ADC enters sleep mode when CONVST is held high
staying HIGH after the conversion ends. If CONVST is high after the conversion is complete (tCONV) if the SLP bit is
after the tCONV period, the LTC2308 enters NAP or SLEEP set to a logic 1. The ADC draws only 7μA in sleep mode,
mode, depending on the setting of SLP bit from the DIN
provided that none of the digital inputs are switching. When
word that was shifted in after the previous conversion.
CONVST returns low, the LTC2308 is released from the
(see Nap Mode and Sleep Mode for more detail).
SLEEP mode and requires 200ms to wake up and charge
When CONVST returns low, the ADC wakes up and the the respective 2.2μF and 10μF bypass capacitors on the
most significant bit (MSB) of the output data sequence VREF and REFCOMP pins.
at SDO becomes valid after the serial data bus is enabled.
All other data bits from SDO transition on the falling edge Board Layout and Bypassing
of each SCK pulse. Configuration data (DIN) is loaded into To obtain the best performance, a printed circuit board with
the LTC2308 at SDI, starting with the first SCK rising edge a solid ground plane is required. Layout for the printed
after CONVST returns low. The S/D bit is loaded on the circuit board should ensure digital and analog signal lines
first SCK rising edge. are separated as much as possible. Care should be taken
Example 2 (Figure 9) shows CONVST returning low be- not to run any digital signal alongside an analog signal. All
fore the conversion ends. In this mode, the ADC and all analog inputs should be shielded by GND. VREF, REFCOMP
internal circuitry remain powered up. When the conver- and AVDD should be bypassed to the ground plane as
sion is complete, the MSB of the output data sequence at close to the pin as possible. Maintaining a low impedance
SDO becomes valid after the data bus is enabled. At this path for the common return of these bypass capacitors
point(tCONV 1.3μs after the rising edge of CONVST), puls- is essential to the low noise operation of the ADC. These
ing SCK will shift data out at SDO and load configuration traces should be as wide as possible. See Figure 7 for a
data (DIN) into the LTC2308 at SDI. The first SCK rising suggested layout.
edge loads the S/D bit into the LTC2308. SDO transitions
on the falling edge of each SCK pulse.
Figures 10 and 11 are the transfer characteristics for the
bipolar and unipolar modes. Data is output at SDO in 2’s
complement format for bipolar readings and in straight
binary for unipolar readings.

2308fb

14
 LTC2308
APPLICATIONS INFORMATION

Figure 7b. Layer 1 Component Side

Figure 7a. Top Silkscreen

Figure 7c. Layer 2 Ground Plane Figure 7d. Layer 3 Power Plane

2308fb

15
LTC2308
APPLICATIONS INFORMATION

Figure 7e. Layer Back Solder Side

JP1
CH0 JP4
J1 1 3 E26
OVDD
CH0 2 SMA 2 EXT OVDD
R1 3 5V 1
OPT OPEN 5V C4 5V
0.1μF
C2 C3 C1
10μF 0.1μF 0.1μF
E1
TP1 21 19 13 12
OPT E2
R2 100Ω CH0 22 CH0 DVDD 0VDD AVDD AVDD
J2
E3 23 CH1
HEADER 12x2 CONV 14
R3 100Ω CH1 24 CH2 CONV_AT_ADC
1 2 SDO 17 R4 301Ω
E4 1 CH3 SDO_AT_ADC
3 4 R5 100Ω SCK 16
CH2 2 CH4 SCK_AT_ADC
5 6 LTC2308 SDI 15
E5 3 CH5 SDI_AT_ADC
7 8 R6 100Ω CH3 REFCOMP 8
4 CH6
9 10 E6 VREF 7 R9 49.9Ω E8 C38
R7 100Ω 5 CH7 10μF
11 12 CH4 VREF
6 COM C5
13 14 E7 2.2μF
R8 100Ω CH5 GND GND GND GND GND GND E9
15 16
E10 25 9 10 11 20 18 REFCOMP
17 18
R10 100Ω CH6
19 20
21 22 E11
R11 100Ω CH7
23 24
R12 100Ω JP3
E12 COM E13
TP2 C7 C9 C11 C13 C14 1 EXTERNAL
OPEN C15
OPT 47pF 47pF 47pF 47pF 47pF 2 BIAS
10μF JP2
C6 C8 C10 C12 3 GND DC BIAS
47pF 47pF 47pF 47pF R13 1
4.99k EXTERNAL
2
C16 3 REFCOMP
1μF R14
4.99k
2308 F07F
E14
DC_BIAS/2

Figure 7f. Partial Demo Board Schematic

2308fb

16
 LTC2308
APPLICATIONS INFORMATION
tWLCONVST
tACQ
CONVST
NAP OR
tCONV
SLEEP
tCYC

1 2 3 4 5 6 7 8 9 10 11 12

SCK

SDI S/D O/S S1 S0 UNI SLP

MSB LSB

Hi-Z Hi-Z
SDO B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

2308 F08

Figure 8. LTC2308 Timing with a Long CONVST Pulse

tACQ
tWHCONV tHCONVST

CONVST

tCYC
tCONV
1 2 3 4 5 6 7 8 9 10 11 12

SCK

SDI S/D O/S S1 S0 UNI SLP

MSB LSB

Hi-Z Hi-Z
SDO B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
2308 F09

Figure 9. LTC2308 Timing with a Short CONVST Pulse

2308fb

17
LTC2308
APPLICATIONS INFORMATION
011...111

OUTPUT CODE (TWO’S COMPLEMENT)

011...110 BIPOLAR
ZERO

000...001
000...000
111...111
111...110

100...001 FS = 4.096V
1LSB = FS/2N
100...000
1LSB = 1mV

–FS/2 –1 0V 1 FS/2 – 1LSB

LSB LSB
INPUT VOLTAGE (V)
2308 F10

Figure 10. LTC2308 Bipolar Transfer

Characteristics (2’s Complement)

111...111
111...110
OUTPUT CODE

100...001
100...000
011...111 UNIPOLAR
ZERO
011...110

000...001 FS = 4.096V
1LSB = FS/2N
000...000 1LSB = 1mV

0V FS – 1LSB
INPUT VOLTAGE (V)
2308 F11

Figure 11. LTC2308 Unipolar Transfer

Characteristics (Straight Binary)

2308fb

18
 LTC2308
PACKAGE DESCRIPTION
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)

0.70 p0.05

4.50 p 0.05 2.45 p 0.05

3.10 p 0.05 (4 SIDES)

PACKAGE OUTLINE

0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH
R = 0.20 TYP OR
4.00 p 0.10 0.75 p 0.05 R = 0.115 0.35 s 45o CHAMFER
(4 SIDES) TYP
23 24

PIN 1 0.40 p 0.10

TOP MARK
(NOTE 6) 1
2

2.45 p 0.10
(4-SIDES)

(UF24) QFN 0105

0.200 REF 0.25 p 0.05

0.00 – 0.05 0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

2308fb

19
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2308
TYPICAL APPLICATION
Clock Squaring/Level Shifting Circuit Allows Testing with RF Sine Generator,
Convert Re-Timing Flip-Flop Preserves Low Jitter Clock Timing
5V
2.7V TO 5V

10μF 0.1μF 10μF 0.1μF 0.1μF

AVDD DVDD OVDD LTC2308

CH0
CH1
CH2 SDI
CH3 ANALOG + 12-BIT
SERIAL
SDO
INPUT 500ksps
CH4 MUX – ADC PORT SCK
CH5 CONVST VCC

CH6 CONTROL
VREF LOGIC
PRE
CH7 INTERNAL 2.2μF (FPGA, CPLD,
Q D DSP, ETC.)
COM 2.5V REF NL17SZ74
Q
CLR
CONVERT ENABLE
REFCOMP
GND 0.1μF 10μF
VCC

RF SIGNAL GENERATOR OR
OTHER LOW JITTER SOURCE 0.1μF 1k MASTER
CLOCK

50Ω 1k NC7SVU04P5X

MASTER CLOCK • • • • • • • • • • • •

CONVERT ENABLE • • • • • • JITTER • • • • • •

CONVST • • • • • • • • • • • •
2308 TA02

DATA TRANSFER

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2308fb

LT 0908 REV B • PRINTED IN USA

20 Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007