EDC Questions With Answers
EDC Questions With Answers
Part-A
1. What is diffusion current? (Nov/Dec 2013)
In a semiconductor it is possible to have a non-uniform distribution of carriers. A
concentration gradient exists if the number of either holes and electrons is greater in
one region as compared to the rest of the region. The holes and electrons then tend to
move from a region of higher concentration to lower concentration region.
This process is known as diffusion and the electric current produced due this process is
known as diffusion current.
2. What is a PN junction diode? (Nov/Dec 2013)
A PN junction diode is a two terminal device consisting of a PN junction formed either
of Germanium or Silicon crystal. A PN junction is formed by diffusing P type material
to one half side and N type material to other half side.
3. Explain the terms knee voltage and breakdown voltage? (Nov 2010)
Knee voltage: The forward voltage at which the current through the PN junction starts
increasing rapidly is known as knee voltage. It is also called as cut-in voltage or
threshold voltage or Breakdown voltage: It is the reverse voltage of a PN junction
diode at which the junction breaks down with sudden rise in the reverse current.
4. Define and explain peak inverse voltage ( PIV) (Nov 2010)
Peak inverse voltage is the maximum reverse voltage that can be applied to the PN
junction without damage to the junction. If the reverse voltage across the junction exceeds
to its peak inverse voltage, the junction may be destroyed due to excessive heat.
5. Define the term diffusion capacitance or storage capacitance.
(Apr/May 2015)
The diffusion capacitance effect is found when the diode is forward biased and it is
defined as the rate of change of injected charge with voltage and given by
=
VT
Where dQ is the increase in charge and dV is the change or increase in voltage. The
depletion region increases with the increase in reverse bias potential the resulting
transition capacitance decreases. The formula for transition capacitance is given as CT =
Aε/W, where A is the cross sectional area of the region, and W is the width.
7. Define Static resistance and Dynamic resistance? (May 2013)
The resistance offered by the diode to DC operating conditions is called “Static
resistance” and the resistance offered by the diode to AC operating conditions is called
“Dynamic resistance”.
8. List the applications of PN junction diode (april/may 2012):
1. Used as rectifier in DC power supplies.
2. Used as signal diodes in communication circuits.
3. Used in clipper and clamper circuits.
9. What is a rectifier and list its types? (Apr/May2015, Nov/Dec 2014,
Nov/Dec 2013)
Rectifier is a circuit which converts a.c. to d.c. signal.
Half-wave rectifier: It is the simplest type of rectifier, which is made with just one
diode.
Full-wave rectifier: This rectifier is essentially made of two half-wave rectifiers, and
can be made with two diodes and an earthed centre tap on the transformer. The centre
tap allows the circuit to be completed because current cannot flow through the other
diode.
Bridge rectifier: A bridge rectifier makes use of four diodes in a bridge arrangement
to achieve full-wave rectification.
10. What is an LED? Draw its symbol. (May 2013)
LED is a Light emitting diode which emits light when it is forward biased.
Part – B
i) Peak Current
The instantaneous value of the voltage applied to the rectifier can be written as Vs =
Vsm Sinωt
Assuming that the diode has a forward resistance of RFWD ohms and a reverse
resistance equal to infinity, the current flowing through the load resistance RLOAD is
given as
Im = Vsm/ (RF + RLoad)
Where VBE=0.7 V
Therefore, VO= constant.
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The emitter current is same as load current. The current IR is assumed to be constant
for a given supply voltage. Therefore, if IL increases, it needs more base currents, to
increase base current Iz decreases. The difference in this regulator with zener regulator
is that in later case the zener current decreases (increase) by same amount by which the
load current increases (decreases). Thus the current range is less, while in the shunt
regulators, if IL increases by ΔIL then IB should increase by ΔIL / β or IZ should decrease
by ΔIL / β. Therefore the current range control is more for the same rating zener.In a
power supply the power regulation is basically, because of its high internal impedance.
In the circuit discussed, the unregulated supply has resistance RS of the order of 100
ohm. The use of emitter follower is to reduce the output resistance and it becomes
approximately.
R h 0
R1 fe
z ie
Where RZ represents the dynamic zener resistance. The voltage stabilization ratio SV is
approximately
SV V0 Rz
Vi Rz Ri
SV can be improved by increasing R. This increases VCE and power dissipated in the
transistor. Other disadvantages of the circuit are.
1. No provision for varying the output voltage since it is almost equal to the zener
voltage.
2. Change in VBE and Vz due to temperature variations appear at the output since
the transistor is connected in series with load, it is called series regulator and
transistor is allow series pass transistor.
PN-junction Laser: A semiconductor laser is a specially fabricated pn junction device
(both the p and n regions are highly doped) which emits coherent light when it is
forward biased. It is made from Gallium Arsenide (GaAs) which operated at low
temperature and emits light in near IR region. Now the semiconductor lasers are also
made to emit light almost in the spectrum from UV to IR using different
semiconductor materials. They are of very small size (0.1 mm long), efficient, portable
andoperate at low power. These are widely used in Optical fibre communications, in
CD players, CD-ROM Drives, optical reading, laserprinting,etc.P and N regions are
made from same semiconductor material (GaAs). A p type region is formed on the n
type by doping zinc atoms. The diode chip is about 500 micrometer long and 100
micrometer wide and thick. The top and bottom face has metal contacts to pass the
current. the front and rare faces are polished to constitute the resonator .
When high doped p and n regions are joined at the atomic level to form pn-junction, the
equilibrium is attained only when the equalization of Fermi level takes place in this case
8
the Fermi level is pushed inside the conduction band in n type and the level pushed
inside the valence band in the p type.
When the junction is forward biased, at low voltage the electron and hole recombine and
cause spontaneous emission. But when the forward voltage reaches a threshold value the
carrier concentration rises to very high value. As a result the region "d" contains large
number of electrons in the conduction band and at the same time large number of holes in
the valence band. Thus the upper energy level has large number of electrons and the lower
energy level has large number of vacancy, thus population inversion is achieved. The
recombination of electron and hole leads to spontaneous emission and it stimulate the
others to emit radiation. Ga As produces laser light of 9000 Å in IR region.
9
5.Explain the working of bridge rectifier. Give the expressions for RMS current,
PIV, Ripple factor and efficiency. (Nov/Dec 2014, May 2017)
Full Wave Bridge Rectifier uses four individual rectifying diodes connected in a
closed loop “bridge” configuration to produce the desired output. The main advantage
of this bridge circuit is that it does not require a special centre tapped transformer,
thereby reducing its size and cost. The single secondary winding is connected to one
side of the diode bridge network and the load to the other side as shown below.
During the negative half cycle of the supply, diodes D3 and D4 conduct in series, but
diodes D1 and D2 switch “OFF” as they are now reverse biased. The current flowing
through the load is the same direction as before.
The Negative Half-cycle
10
As the current flowing through the load is unidirectional, so the voltage developed
across the load is also unidirectional the same as for the previous two diode full-wave
rectifier, therefore the average DC voltage across the load is 0.637Vmax.However in
reality, during each half cycle the current flows through two diodes instead of just one
so the amplitude of the output voltage is two voltage drops ( 2 x 0.7 = 1.4V ) less than
the input VMAX amplitude. The ripple frequency is now twice the supply frequency
(e.g. 100Hz for a 50Hz supply or 120Hz for a 60Hz supply.)Although we can use four
individual power diodes to make a full wave bridge rectifier, pre-made bridge rectifier
components are available “off-the-shelf” in a range of different voltage and current
sizes that can be soldered directly into a PCB circuit board or be connected by spade
connectors.The image to the right shows a typical single phase bridge rectifier with
one corner cut off. This cut-off corner indicates that the terminal nearest to the corner
is the positive or +ve output terminal or lead with the opposite (diagonal) lead being
the negative or -ve output lead. The other two connecting leads are for the input
alternating voltage from a transformer secondary winding.
Ripple factor:
Ripple factor for bridge rectifier is 0.482
UNIT II- TRANSISTORS
Part-A
1. What is meant by biasing a transistor? (Nov/Dec 2014) Transistor biasing is the
process of maintaining proper flow of zero signal collector current and collector-
emitter voltage during the passage of signal. Biasing keeps emitter-base junction
forward biased and collector-base junction reverse biased during the passage of
signal.
11
dissipation at the collector - base junction. This I in turn further increase the
temperature of the collector-base junction causing the collector current to further
increase. This process may become cumulative and it is possible for the transistor to
burn out. This process is known as Thermal runaway.
4. What is intrinsic stand off ratio of a UJT?
The ratio of voltage between emitter and base 1 to VBB is called as intrinsic
stand of ratio.The value lies between 0.51 to 0.82.
Beta ( ) is the current gain of a common emitter transistor. It can be defined as the
Parameters CB CE CC
Current gain (Ai) Low High High
Voltage gain (Vi) High High Low
Input resistance (Ri) Low Medium High
Output resistance (Ro) High Medium Low
Part - B
1. Explain the input and output characteristics of a CE transistor configuration. List
out the comparisons between CE, CB and CC configurations.(Nov/Dec 2013). Input
Characteristic: The curve between IB and VBE for different values of VCE are shown in
figure. Since the base emitter junction of a transistor is a diode, therefore the
characteristic is similar to diode one. With higher values of VCE collector gathers slightly
more electrons and therefore base current reduces. Normally this effect is neglected.
(Early effect). When collector is shorted with emitter then the input characteristic is the
characteristic of a forward biased diode when VBE is zero and IB is also zero.
Output Characteristic: The output characteristic is the curve between V CE and IC for
various values of IB. For fixed value of IB and is shown in figure. For fixed value of IB,
IC is not varying much dependent on VCE but slopes are greater than CE characteristic.
The output characteristics can again be divided into three parts.
dc
dc
1dc
IC (1dc )I COdc I B
I I
C C 0
dcI I
BCO
If adc is truly constant then IC would be independent of VCE. But because of early effect,
αdc increases by 0.1% (0.001) e.g. from 0.995 to 0.996 as V CE increases from a few
volts to 10V. Then βdc increases from 0.995 / (1-0.995) = 200 to 0.996 / (1-0.996)
= 250 or about 25%. This shows that small change in a reflects large change in b.
Therefore the curves are subjected to large variations for the same type of transistors.
(2) Cut Off:
Cut off in a transistor is given by IB = 0, IC= ICO. A transistor is not at cut off if the base
current is simply reduced to zero (open circuited) under this condition,
IC = IE= ICO / ( 1-αdc) = ICEO
The actual collector current with base open is designated as I CEO. Since even in the
neighborhood of cut off, a dc may be as large as 0.9 for Ge, then IC=10
ICO(approximately), at zero base current. Accordingly in order to cut off transistor it is
not enough to reduce IB to zero, but it is necessary to reverse bias the emitter junction
slightly. It is found that reverse voltage of 0.1 V is sufficient for cut off a transistor. In
Si, the α dc is very nearly equal to zero, therefore, I C = ICO. Hence even with IB= 0, IC=
IE= ICO so that transistor is very close to cut off. In summary, cut off means I E = 0, IC =
ICO, IB = -IC = -ICO , and VBE is a reverse voltage whose magnitude is of the order of
0.1 V for Ge and 0 V for Si.
(3).Saturation Region:
In this region both the diodes are forward biased by at least cut in voltage. Since the
voltage VBE and VBC across a forward is approximately 0.7 V therefore, VCE = VCB+
VBE = - VBC + VBE is also few tenths of volts. Hence saturation region is very close to
zero voltage axis, where all the current rapidly reduces to zero. In this region the
transistor collector current is approximately given by VCC / R C and independent of
base current. Normal transistor action is last and it acts like a small ohmic resistance.
Comparison of CE, CB and CC configurations:
Parameters CB CE CC
Current gain (Ai) Low High High
Voltage gain (Vi) High High Low
Input resistance (Ri) Low Medium High
Output resistance (Ro) High Medium Low
15
Operation of EMOSFET:
As its name indicates, this MOSFET operates only in the enhancement mode and has
no depletion mode. It operates with large positive gate voltage only. It does not
=
conduct when the gate-source voltage VGS 0. This is the reason that it is called
normally-off MOSFET. In these MOSFET’s drain current ID flows only when VGS
exceeds VGST [gate-to-source threshold voltage].
When drain is applied with positive voltage with respect to source and no potential is
applied to the gate two N-regions and one P-substrate from two P-N junctions connected
back to back with a resistance of the P-substrate. So a very small drain current that is,
reverses leakage current flows. If the P-type substrate is now connected to the source
-
terminal, there is zero voltage across the source substrate junction, and the drain-substrate
junction remains reverse biased. When the gate is made positive with respect to the source
and the substrate, negative (i.e. minority) charge carriers within the substrate are attracted
to the positive gate and accumulate close to the-surface of the substrate. As the gate
voltage is increased, more and more electrons accumulate under the gate. Since these
electrons cannot flow across the insulated layer of silicon dioxide to the gate, so they
accumulate at the surface of the substrate just below the gate. These accumulated minority
charge carriers N -type channel stretching from drain to source. When this occurs, a
channel is induced by forming what is termed an inversion layer (N-type). Now a drain
current starts flowing. The strength of the drain current depends upon the channel
resistance which, in turn, depends upon the number of charge carriers attracted to the
positive gate. Thus drain current is controlled by the gate potential. Since the conductivity
of the channel is enhanced by the positive bias on the gate so this device is also called the
enhancement MOSFET or E- MOSFET.The minimum value of gate-to-source voltage V GS
that is required to form the inversion layer
16
(N-type) is termed the gate-to-source threshold voltage VGST. For VGS below VGST, the
drain current ID = 0. But for VGS exceeding VGST an N-type inversion layer connects the
source to drain and the drain current ID is large. Depending upon the device being
used, VGST may vary from less than 1 V to more than 5 V.JFETs and DE-MOSFETs are
classified as the depletion-mode devices because their conductivity depends on the
action of depletion layers. E-MOSFET is classified as an enhancement-mode device
because its conductivity depends on the action of the inversion layer. Depletion-mode
devices are normally ON when the gate-source voltage V GS = 0, whereas the
enhancement-mode devices are normally OFF when VGS = 0.
Characteristics of EMOSFET:
Figure shows a typical transconductance curve. The current IDSS at VGS <=0 is very
small, being of the order of a few nano-amperes. When the V GS is made positive, the drain
current ID increases slowly at first, and then much more rapidly with an increase in V GS.
The manufacturer sometimes indicates the gate-source threshold voltage V GST at which the
drain current ID attains some defined small value, say 10 u A. A current I D (0N,
corresponding approximately to the maximum value given on the drain characteristics and
the values of VGS required to give this current VGs QN are also usually given on the
manufacturers data sheet. The equation for the transfer characteristic does not obey
equation. However it does follow a similar “square law type” of relationship. The
equation for the transfer characteristic of E-MOSFETs is given as:
2
ID=K(VGS-VGST)
17
3. Explain the construction and operation of NPN transistor with neat sketch.
Also comment on the characteristics of NPN transistor.
(Nov/Dec 2014)
The NPN Transistor
In the previous tutorial we saw that the standard Bipolar Transistor or BJT, comes in two
basic forms. An NPN (Negative-Positive-Negative) type and a PNP (Positive-Negative-
Positive) type, with the most commonly used transistor type being the NPN Transistor. We
also learnt that the junctions of the bipolar transistor can be biased in one of three different
ways – Common Base, Common Emitter and Common Collector.
In this tutorial about bipolar transistors we will look more closely at the “Common
Emitter” configuration using the Bipolar NPN Transistor with an example of the
construction of a NPN transistor along with the transistors current flow characteristics
is given below.
A Bipolar NPN Transistor Configuration
(Note: Arrow defines the emitter and conventional current flow, “out” for a Bipolar
NPN Transistor.)
The construction and terminal voltages for a Bipolar NPN Transistor are shown above.
The voltage between the Base and Emitter ( VBE ), is positive at the Base and negative
at the Emitter because for an NPN transistor, the Base terminal is always positive with
respect to the Emitter. Also the Collector supply voltage is positive with respect to the
Emitter ( VCE ). So for a bipolar NPN transistor to conduct the Collector is always
more positive with respect to both the Base and the Emitter.
22
maximum current flowing through the device. The Base supply voltage V B is connected to
the Base resistor RB, which again is used to limit the maximum Base current.
So in a NPN Transistor it is the movement of negative current carriers (electrons)
through the Base region that constitutes transistor action, since these mobile electrons
provide the link between the Collector and Emitter circuits. This link between the
input and output circuits is the main feature of transistor action because the transistors
amplifying properties come from the consequent control which the Base exerts upon
the Collector to Emitter current.
Then we can see that the transistor is a current operated device (Beta model) and that a
large current ( Ic ) flows freely through the device between the collector and the emitter
terminals when the transistor is switched “fully-ON”. However, this only happens when a
small biasing current ( Ib ) is flowing into the base terminal of the transistor at the same
time thus allowing the Base to act as a sort of current control input.
The transistor current in a bipolar NPN transistor is the ratio of these two currents
( Ic/Ib ), called the DC Current Gain of the device and is given the symbol of hfe or
nowadays Beta, ( β ). The value of β can be large up to 200 for standard transistors,
and it is this large ratio between Ic and Ib that makes the bipolar NPN transistor a
useful amplifying device when used in its active region as Ibprovides the input and Ic
provides the output. Note that Beta has no units as it is a ratio.
Also, the current gain of the transistor from the Collector terminal to the Emitter terminal,
Ic/Ie, is called Alpha, ( α ), and is a function of the transistor itself (electrons diffusing
across the junction). As the emitter current Ie is the sum of a very small base current plus
a very large collector current, the value of alpha α, is very close to unity, and for a typical
low-power signal transistor this value ranges from about 0.950 to 0.999
+
+
==
23
3. Draw the Eber moll model of a transistor. (Nov/Dec 2014)
5. Define upper and lower cut off frequencies of an amplifier. (Apr/May 2014)
The frequency at which the voltage gain of the amplifier is exactly 70.7% of the
10. State the reason for choosing 3 db point to determine the bandwidth. (Apr/May
2014)
The reason for choosing 3 db point to determine the bandwidth is that,
above this level, larger the frequency variation (i.e. output delivers the constant output
below this level even for lower frequency variation), the gain variation is large i.e. the
output is not constant. Thus 3 db point is selected as reference to find the bandwidth.
Part-B
1.Explain about CE amplifier and derive the expression for h parameters of the
same. Also derive the expression for gain, input impedance and output
impedance of CE amplifier. (Nov/Dec 2013), (Nov/Dec 2014), (Apr/May 2015) ,
(Nov/Dec 2016)
Analysis of CE amplifier:
24
In a transistor amplifier, the dc source sets up quiescent current and voltages. The ac
source then produces fluctuations in these current and voltages. The simplest way to
analyze this circuit is to split the analysis in two parts: dc analysis and ac analysis. One
can use superposition theorem for analysis.
CE Amplifier circuit diagram
For ac equivalent circuits reduce dc voltage sources to zero and open current sources
and short all capacitors. This circuit is used to calculate ac currents and voltage.
The total current in any branch is the sum of dc and ac currents through that branch.
The total voltage across any branch is the sum of the dc voltage and ac voltage across
that branch.
Phase Inversion:
Because of the fluctuation is base current; collector current and collector voltage also
swings above and below the quiescent voltage. The ac output voltage is inverted with
o
respect to the ac input voltage, meaning it is 180 out of phase with input. During the
positive half cycle, increase in base current causing the collector current to increase.
This produces a large voltage drop across the collector resistor; therefore, the voltage
25
output decreases and negative half cycle of output voltage is obtained. Conversely, on
the negative half cycle of input voltage less collector current flows and the voltage
drop across the collector resistor decreases, and hence collector voltage increases we
get the positive half cycle of output voltage.
H-model of CE amplifier
Current gain:
For the transistor amplifier stage, Ai is defined as the ratio of output to input currents.
Input Impedance:
The impedance looking into the amplifier input terminals (1,1') is the input impedance Zi
Voltage gain:
The ratio of output voltage to input voltage gives the gain of the transistors.
26
Output Admittance:
It is defined as
27
2.Explain about CB amplifier and derive the expression for h parameters of the
same. Also derive the expression for gain, input impedance and output impedance
of CB amplifier. (Nov/Dec 2013)
The figure shows the transistor connected in common emitter configuration and the
figure also shows the hybrid equivalent circuit of such a transistor.
In common emitter transistor configuration, the input signal is applied between the
base and emitter terminals of the transistor and output appears between the collector
and base terminals. The input voltage (Vbe) and the output current (ic) are given by the
following equations:
Vbe = hib.ib + hrb.Vc
ie = hfb.ib + hob.Vc
Hybrid expression
Expression can be obtained from the general hybrid formulas derived in this article
Hybrid Equivalent of Transistor by adding a second subscript letter ‘b’ (which stands
for commonbase) with the h-parameters and are as discussed below.
Current Gain
It is given by the relation,
Ai = -(hfb/(1 + hob.rL))
Where rL is the A.C load resistance. Its value is equal to the parallel combination of
resistance Rcand RL. Since hfb of a transistor is a positive number, therefore A i of a
common emitter amplifier is negative.
Input Resistance
The resistance looking into the amplifier input terminals (i.e. base of a transistor) is
given by the relation,
Ri = hib + hrb.Ai.rL = hib – ((hrb.hfb)/(hob + (1/rL)))
The input resistance of the amplifier stage (called stage input resistance R is) depends
upon the biasing arrangement. For a fixed bias circuit, the stage input resistance is, R is
= Ri
Voltage Gain
It is given by the relation,
Av = Ai.r1/Ri
Since the current gain (Ai) of a common base amplifier is positive, therefore the voltage
gain (Av) is also positive. It means that there is no phase difference between the input
and output signals of the common base amplifier. The voltage gain, in terms of h-
parameters, is given by the relation.
Av = hfb.rL/(hib + ∆h.rL)
Where
∆h = hib.hob – hrb.hfb
28
Output Resistance
The resistance looking into the amplifier output terminals is given by the relation,
Ro = (Rs + hib)/(Rs.hob + ∆h)
Where
Rs = Resistance of the source, and
∆h = hib.hob – hrb.hfb
The output resistance of the stage,
Ros = Ro // rL
Overall Voltage Gain
It is given by the relation,
Avs = (Av.Ris)/(Rs + Ris)
Overall Current Gain
It is given by relation,
Ais = Ai.Rs/(Rs + Ris)
3. Explain about CS amplifier(MOSFET) and derive the expression for gain,
input impedance and output impedance and also draw its small signal equivalent
circuit. (May 2013), (Nov 2014), (Apr 2015)
common-source is one of three basic single-stage (FET) amplifier topologies,
typically used as a . The easiest way to tell if a FET is common source, or common is
to examine where the signal enters and leaves. The remaining terminal is what is
known as "common". In this example, the signal enters the gate, and exits the drain.
The only terminal remaining is the source. This is a common-source FET circuit.
gm is the trans-conductance of Tin. (We assume here that Tin operates in saturation
and that its current depends only on its Vgs; the drain-source small-signal resistance is
infinite. Tinbehaves as a current source.) The small-signal output voltage is: Vout = - i
x R. (2)
(The “large signal” output voltage is Vout = VDD – RI.)
Note, that we here neglected the drain-source resistance of Tin. This is not a problem if
rds >>R. Note also, that we neglected all the parasitic capacitances. Combining of (1)
and (2), we obtain:
A = - gmR. (4)
Discussion:
Voltage gain A is large if gm is large and R is large. However, if R is large, transistor
currentI should be small, otherwise DC voltage at transistor’s drain would be too low, so
that Tin isnot in saturation. Unfortunately, a small transistor-current leads to a small
gm. The use of acurrent-source instead normal resistor can solve the problem. This
will be explained later.
Output impedance
We have just calculated the gain without load of the amplifier; however, this is not
everything weneed to characterize the circuit. Knowing the gain of an amplifier is
similar to knowing theopen circuit (no load) voltage of a real voltage-source. The
information about the outputImpedance is missing. First, we will concentrate on output
resistance – Rout. We can thinkout a test circuit for the calculation of the Rout (shown
in T2). We connect a test voltage source Vtest to theoutput of the amplifier. We
“measure” the current flowing through Vtest, let us call it Itest.
Rout = Vtest/Itest(5)
30
It is important that we set the input signal to zero when we calculate rout. Therefore vin
= vgs= 0.In this case, the current source, assigned to Tin, does not generate current.
(Generally, Tin insaturation is modeled with a parallel connection of its current source
(icurrsc = gm x vgs) andits drain source resistance rds. Since icurrsc = 0, only the drain
source resistance remains) Test generator Vtest “sees” in this way resistance R
connected to VDD and rds of Tinconnected to GND. Because of that, for small signals
VDD = GND = 0, the two resistances areeffectively in parallel. They can by described
by an equivalent parallel resistance:
This is the output resistance of the amplifier. Therefore we have the following result:
Clearly, for large R ~ 100kOhm and low-resistance load Rload~8Ohm, only a small
part of the original amplified voltage will be present at Rload. Such an amplifier
cannot be used to drive a low-resistance load in efficient way.
Output impedance
Test voltage source at the output sees not only resistances. We have a few capacitances in
the circuit as well. These capacitances are “hidden” inside the transistor Tin, they are
result of the fact that any change of the drain-bulk or drain-source voltage is followed (or
better caused) by charge flow necessary, for instance, to empty or fill certain silicon
depleted regions. These capacitances are called parasitic capacitances. The most important
parasitic capacitances of a transistor in saturation are Cgs, Cgb, Cgd, Cdb and Csb, see
T4. We assume that source and bulk of Tin are both connected to ground. (It is interesting
- but not so important - that Cgd is slightly different from Cdg. We assume their equality.)
The test voltage source sees all the drain related capacitances – Cgd and
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Cdb connected in parallel. (Note that gate node is connected to ground in this test
circuit.)
We have now two possibilities :Either, we combine the output impedance (capacitances
Cgd and Cdb) with the output resistance into the mixed output impedance, or we treat the
output impedance as a part of load – we call it then the “intrinsic capacitive load”. We will
do the later. (Everything here is more or less approximate. Since we didn’t take the
capacitances into account when we derived the gain without load, we will not add them to
output impedance as well. However, we will take the intrinsic capacitances into account
when we calculate the input impedances.) Generally, the intrinsic capacitive load can be
neglected if 1/omega x C >> Rload, for the angular frequency of interest.
Input impedance
The input small-signal impedance can be calculated using a test generator connected to
amplifier’s input and by measuring the current that flows through this generator (T5). The
inputimpedance is then defined as the ratio between the test voltage and the current.
Let us compare this result with the result that we had if Cgd were connected between
Vtest(input node) and ground. If we changed Vtest (from 0 to Vtest), we would
measure charge:
If we compare last two equations, we see that, from the point of Vtest, capacitance
Cgd is effectively increased by factor (1+gmR) if we connect it between gate and
drain. This is called Miller effect. It is another disadvantage of the common source
amplifier. The input capacitance is large due to the Miller effect.
4. Explain about the high frequency response of FET and derive the
expression for lower cut off frequency and upper cut off frequency.
An amplifier is a circuit that increases/decrease the input signal value and in this
experiment the signal to be amplified is the voltage. In this experiment you are going
to investigate frequency response characteristic of a voltage amplifier circuit using the
N-channel JFET device.
Most amplifiers have relatively constant gain over a certain range of frequencies. This
range of frequencies is called the bandwidth of the amplifier. The bandwidth for a given
amplifier depends on the circuit component values, the type of active components and the
dc operating point of the active component. When an amplifier is operated within its
bandwidth, the current gain Ai , voltage gain Av , and power gain Ap values are
referred to as midband gain values. A simplified frequency-response curve that
represents the relationship between amplifier gain and operating frequency is shown in
Figure 1
35
.
Frequency response curves and specification sheets often list gain values that
are measured in decibels (dB). Positive and negative decibels of equal magnitude
represent reciprocal gains and losses. A +3dB gain caused power to double while a –
3dB gain caused power to be cut in half.
The voltage component of the equation is referred to as dB voltage gain. When the
amplifier input and out resistances are equal
Thus, when the voltage gain of an amplifier changes by –3dB, the power gain of the
amplifier also changes by –3dB.
5. Draw the ideal tank circuit and write the expression for its resonant
frequency (Nov/dec 2011)
Fr=1/(2πRC)
6. What are the advantages of tuned amplifiers? (Apr/May 2010)
They amplify defined frequencies.
Signal to noise ratio at output is good
They are suited for radio transmitters and receivers
36
8. What are the advantages of push pull amplifier? (Nov/Dec 2014)
The harmonic distortions are removed.
The efficiency is increased.
9. What is cross over distortion? How it can be eliminated? (Apr/May 2011)
There is a 0.7V delay in between every half cycle. Due to this the sine wave will not
be a continues wave. This is called cross over distortion. It can be eliminated by class
AB amplifier.
10. What is neutralization? (Apr/May 2010)
The effect of collector to base capacitance of the transistor is neutralized by
introducing a signal that cancels the signal coupled through collector base capacitance.
This process is called neutralization.
11. Define conversion efficiency of power amplifier (Nov/Dec 2016)
It is a measure of the ability of an active device to convert the dc power of the supply
into an ac power delivered to the load
The emitter-coupled differential pair is a very important circuit that is used many bipolar
analog integrate circuits.The circuit is shown in the figure and the two transistors are
assumed identical. The current source IEE is typically implemented as a current source
circuit (eg. Current mirror, wilson current source).The input voltages V i1 and Vi2 can be
considered to be composed of a differential signal Vid and a common mode signal Vicm
defined below: v v v
id i1 i 2
v
icm 1/ 2(vi1 vi 2 )
Differential output voltage is defined as
vod vo1 vo 2 ,
since v V R i ,v V Ri
o1 CC C C1 o 2 CC2
CC
For a pure differential input (when Vicm=0), it can be shown the a non-zero differential
output voltage Vod is resulted, as a differential input signal steers IEEtowards one side or
the other.
In summary, the circuits rejects common-mode input and responds to the differential
input. In amplifiers, a small differential input signal is amplified to a differential output
signal.
From the half circuit, we can then compute the gain, input impedance and output
impedance.
v
R icm r (1)REF (1)R
id i EB
b1 ib 2 2
Note that we have defined the common-mode input impedance to be the voltage
divided by the total current the source must deliver to both terminals. The gain from a
single-ended load to common-mode input is:
v v
A O1 Ocm
RC
vcm
vicm vicm
r (1)(REF 2REB )
For output impedance, we have:
ROs RC
ROb 2RC
38
A measure of how well the amplifier rejects the common-mode signal relative to the
differential signal is the common-mode rejection ratio (CMRR). By definition, the CMRR
is ratio of the gain for the differential signal to the gain for common-mode signal.
2. Explain with a neat sketch the working of single tuned voltage amplifier
using FET.
41
adjusted until the d.c. grid current no longer changes, or, at most, shows a small
gradual rise and fall, with a maximum at resonance. The circuit is then neutralized.
Cascading means connecting the output of one amplifier to the input of another to
form a multistage amplifier. The overall gain of cascaded amplifiers depends on that of
each stage and the total number of stages. The purpose of cascading amplifiers is to
reach the desired signal power with a minimum amount of distortion, by providing
equal overall gain characteristics to all frequencies in the signal.
Gain
42
Gain tells the amount of power by which an amplifier increases a signal, and is usually
measured in decibels referenced to a milliwatt. Using dBm allows a small range of
numbers to represent a large increase in power. A gain of 3 dB roughly doubles the
power. A level of 0 dBm, which represents 0.001 watt or 1.0 milliwatt sent to a 50 dB
amplifier, would result in an output signal of +50 dBm or 100 watts. However, a wide-
band signal sent into such a large amplifier would come out with a poor frequency
response.
Frequency Response
An amplifier with high gain can only increase a certain range of frequencies. Higher
frequencies require different design characteristics. A 50 dB amplifier may amplify the
lower frequencies at the full capacity of the amplifier, but would only amplify the
midrange at 48.5 dB and the high range at 47 dB. That may only seem like a small
difference, but the higher frequencies would be only half the wattage of lower. This 50
dB amplifier would have a frequency response of 3 dB. Amplifiers can be designed for
lower gain, and to amplify certain portions of the signal differently.
2 2 +
Part-B
1. Draw and describe the four types of topology for feedback of an amplifier.
Derive the expression for gain with feedback. Mention the advantages of
negative feedback amplifier.(Nov/Dec 2014, Nov/Dec 2013, Nov/Dec 2016,May
2017)
There are four different types of feedback topologies based on type of output signal
and feedback signal (voltage or current signal). Voltage feedback is taken in series with
the load and current feedback is taken in shunt with the load. They are
The Four Basic Feedback Topologies
i) Voltage - Series
ii) Voltage - Shunt
iii) Current - Series
iv) Current - Shunt
Voltage Series Feedback:[Voltage Sample – Voltage Sum]
Assume that we have a voltage amplifier – voltage input with amplified voltage output.
Since the output quantity is a voltage, it follows that any feedback network should
44
sample the output voltage. It also follows that the feedback signal xf should be a
voltage that can be added to the source voltage in series.
This type of feedback topology – voltage sampling, series summing – is referred
to as the Voltage - Series configuration. The series part refers to the input and voltage
refers to the output. The feedback amplifier employing the Voltage -Series topology
can be represented by the diagram below:
45
current sampling, voltage summing. This type of topology is also referred to as the
Series-Series configuration.
AGf= Io / Vs
β= Vf / Io
Voltage Shunt:[Voltage Sample – Current Sum]
Assume a Transresistance amplifier – current signal input, voltage signal output. It
follows that the appropriate topology for such an amplifier is a voltage sample,
current sum configuration. This is also referred to as the voltage – shunt
configuration.
ARf = Vo / Is
β = If / Vo
Feedback Voltage Current Current shunt Voltage
topology series series shunt
Input
Increases Increases Decreases Decreases
resistance
Rif Rif Rif =Ri/(1+A*β) Rif =
=Ri*(1+A*β) =Ri*(1+A*β) Ri/(1+A*β)
Output
Decreases Increases Increases Decreases
resistance
Rof = Rof Rof=Ro*(1+A*β) Rof =
Ro/(1+A*β) =Ro*(1+A*β) Ro/(1+A*β)
46
Colpitts Oscillator
Tank Circuit
It uses a capacitor voltage divider as its feedback source. The two capacitors, C1 and
C2 are placed across a common inductor, L as shown so that C1, C2 and L forms the
tuned tank circuit the same as for the Hartley oscillator circuit.
The advantage of this type of tank circuit configuration is that with less self and
mutual inductance in the tank circuit, frequency stability is improved along with a
more simple design.
As with the Hartley oscillator, the Colpitts oscillator uses a single stage bipolar
transistor amplifier as the gain element which produces a sinusoidal output. Consider
the circuit below.
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The transistor amplifiers emitter is connected to the junction of capacitors, C1 and C2
which are connected in series and act as a simple voltage divider. When the power
supply is firstly applied, capacitors C1 and C2 charge up and then discharge through
the coil L. The oscillations across the capacitors are applied to the base-emitter
junction and appear in the amplified at the collector output.
The amount of feedback depends on the values of C1 and C2 with the smaller the
values of C the greater will be the feedback.
The required external phase shift is obtained in a similar manner to that in the Hartley
oscillator circuit with the required positive feedback obtained for sustained un-damped
oscillations. The amount of feedback is determined by the ratio of C1 and C2. These
two capacitances are generally “ganged” together to provide a constant amount of
feedback so that as one is adjusted the other automatically follows.
The frequency of oscillations for a Colpitts oscillator is determined by the resonant
frequency of the LC tank circuit and is given as:
3. With a neat diagram explain about Hartley oscillator & derive the
expression for frequency of oscillation and condition of oscillation. (Nov/Dec
2014)
48
In the circuit diagram resistors R1 and R2 give a potential divider bias for the
transistor Q1. Re is the emitter resistor, whose job is to provide thermal stability for
the transistor. Ce is the emitter by pass capacitors, which by-passes the amplified AC
signals. If the emitter by-pass capacitor not there, the amplified ac voltages will drop
across Re and it will get added on to the base-emitter voltage of Q1 and will disrupt
the biasing conditions. Cin is the input DC decoupling capacitor while C out is the output
DC decoupling capacitor. The task of a DC decoupling capacitor is to prevent DC
voltages from reaching the succeeding stage. Inductor L1, L2 and capacitor C1 forms
the tank circuit.
When the power supply is switched ON the transistor starts conducting and the
collector current increases. As a result the capacitor C1 starts charging and when the
capacitor C1 is fully charged it starts discharging through coil L1. This charging and
discharging creates a series of damped oscillations in the tank circuit and it is the key.
The oscillations produced in the tank circuit is coupled (fed back) to the base of Q1 and it
appears in the amplified form across the collector and emitter of the transistor. The output
voltage of the transistor (voltage across collector and emitter) will be in phase with the
voltage across inductor L1. Since the junction of two inductors is grounded, the voltage
across L2 will be 180° out of phase to that of the voltage across L1. The voltage across L2
is actually fed back to the base of Q1. From this we can see that, the feedback voltage is
180° out of phase with the transistor and also the transistor itself will create another 180°
phase difference. So the total phase difference between input and output is 360° and it is
very important condition for creating sustained oscillations.
Condition for oscillation:
Barkhausen Criterion: A linear system will produce sustained oscillations only at
frequencies for which the gain around the feedback loop is 1 and the phase shift
around the feedback loop is ZERO or an integral multiple of 2π.
Frequency of the Hartley oscillator:
Resonance Frequency:
49
The frequency “F” of a Hartley oscillator can be expressed using the equation;
50
for use in electronic oscillators, the crystal is suitably cut and then mounted between
two metal plates, as shown in fig (a). Although the crystal has electro-mechanical
resonance but the crystal action can be represented by an electrical resonance circuit,
as shown in fig. (b). The crystal actually behaves as a series R-L-C circuit in parallel
with CM where CM is the capacitance of the mounting electrodes. Because the crystal
losses, represented by R, are small the equivalent crystal Q is high-typically 20,000.
6
Values of Q upto 10 can be obtained by making use of crystals. Because of presence
of CM, the crystal has two resonant frequencies. One of these is the series resonant
frequency fs at which 2πfL = 1/2πfC and in this case the crystal impedance is very low.
The other is parallel resonance frequency fp which is due to parallel resonance of
capacitance CM and the reactance of the series circuit. In this case crystal impedance is
very high. The impedance versus frequency curve of the crystal is shown in figure. In
order to use the crystal properly it must be connected in a circuit so that its low
impedance in the series-resonant operating mode or high impedance in the anti-
resonant or parallel resonant operating mode is selected.
Two resonant frequencies are given by the expressions Series resonant frequency, fs =
1/2 π√LC Parallel resonant frequency, FP = 1/2π√[1 + C/CM] / LC It appears that fp is
higher than fs but the two frequencies are very close to each other. It is due to the fact
that the ratio C/CM is very small.To stabilize the frequency of an oscillator, a crystal
may be operated at either its series or parallel resonant frequency.
Theoretically in a simple RC circuit , the output voltage will lead the input voltage by a
phase angle Φ =90°. Anyway in practical case the phase angle will be something below
90° just because it is impossible to get a purely ideal capacitor. Phase shift of a practical
RC network depends on the value of the capacitor, resistor and the operating frequency.
Let F be the operating frequency, R be the resistance and C be the capacitance. Then the
capacitive reactance Xc to the frequency F can be given by the equation Xc = 1 /
(2πFC)
The effective impedance of the circuit can be given by the equation Z = √( R² + Xc²)
-1
The phase angle of the RC network can be derived as Φ = tan (Xc/R)
Just by making an RC network with phase shift equal to 60° and cascading three of
them together the desired phase shift of 180° can be attained. This 180° phase shift by
the RC network plus the 180° phase shift made by the transistor gives a total phase
shift of 360° between the input and output which is the necessary condition for
maintaining sustained oscillations. The circuit diagram of a three stage RC network
producing a phase shift of 180° is shown in the figure below.
52
Connecting such a three stage RC phase shift network between the input and output of
a common emitter transistor amplifier will result in a transistor based RC phase shift
oscillator. The circuit diagram is shown below.
Where:
ƒr is the Output Frequency in Hertz
R is the Resistance in Ohms
C is the Capacitance in Farads
N is the number of RC stages. (N = 3)
53
Since the resistor-capacitor combination in the RC Oscillator circuit also acts as an
attenuator producing an attenuation of -1/29th ( Vo/Vi = β ) per stage, the gain of the
amplifier must be sufficient to overcome the circuit losses. Therefore, in our three
stage RC network above the amplifier gain must be greater than 29.
The loading effect of the amplifier on the feedback network has an effect on the
frequency of oscillations and can cause the oscillator frequency to be up to 25% higher
than calculated. Then the feedback network should be driven from a high impedance
output source and fed into a low impedance load such as a common emitter transistor
amplifier but better still is to use an as it satisfies these conditions perfectly.
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