ICE Emulator for the 80186 and 80196

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TRACE32 Documents ...................................................................................................................... 

ICE In-Circuit Emulator ................................................................................................................. 

ICE Target Guides ...................................................................................................................... 

ICE Emulator for the 80186 and 80196 .................................................................................. 1

Warning ................................................................................................................................. 6

Quick Start ............................................................................................................................ 7

Troubleshooting ................................................................................................................... 11
Hang-Up 11
Dual-Port Errors 12

FAQ ........................................................................................................................................ 13

Configuration ........................................................................................................................ 14
DIP-Switch Setting of 8086/8088/V20/V30 14
DIP-Switch Setting of 80186(EA)/80188(EA)/80C186(XL)/80C188(XL) 15
DIP-Switch Setting of 80186EB/80188EB/80186EC/80188EC, V40/V50 16
DIP-Switch Setting of 186EM/ES/ER/ED/188EM/ES/ER 17
DIP-Switch Setting of 186CC/CH/CU 18

Basics .................................................................................................................................... 19
Emulation Modes 19
Dual-Port Access 21
SYStem.Clock Clock generation 21

General SYStem Settings and Restrictions ....................................................................... 22

General Restrictions 22
SYStem.Option BreakWin Break window 23
SYStem.Option ONCE On-circuit emulation 23
SYStem.Option RamWait Wait states 23
SYStem.Option REFresh Trace refresh cycles 24
SYStem.Option REL Relocation register 24
SYStem.Option SPLIT Access control on splitted memory 24
SYStem.Option TestClock Clock fail detection 24
SYStem.Option V33 3.3 V power fail detection 25
Continue with CPU specific Special Settings and Restrictions 25

Special Settings 8086/8088/V20/V30 ................................................................................... 26

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 1
 SYStem.Option FPU Floating-point unit 26
SYStem.Option MAX MIN/MAX mode 27

Special Settings 80186/80188 .............................................................................................. 28

SYStem.Option FPU Floating-point unit 28
SYStem.Option MAX MIN/MAX mode 28

Special Settings C186(XL)/C188(XL)/EA and Restrictions ............................................... 29

Restrictions 80C186(XL)/80C188(XL)/80C186EA/80C188EA 29
SYStem.Option Enhanced Enhanced mode 29
SYStem.Option FPU Floating-point unit 29

Special Settings 80186EB/80188EB/80186EC/80188EC .................................................... 30

SYStem.Option FPU Floating-point unit 30

Special Settings 186EM, 188EM and Restrictions ............................................................. 31

Restrictions 186EM, 188EM 31
SYStem.CPU CPU type 31
SYStem.Line ADDR Shared address pins 32
SYStem.Line SRDY SRDY pin 32

Special Settings 186ES, 188ES, 186ED and Restrictions ................................................. 33

Restrictions 186ES, 188ES, 186ED 33
SYStem.CPU CPU type 33
SYStem.Line ADDR Shared address pins 34
SYStem.Line SRDY SRDY pin 34
Mapping 34
MAP.BUS8 Bus width mapping 35

Special Settings 186ER/188ER and Restrictions .............................................................. 36

Restrictions 186ER/188ER 36
SYStem.CPU CPU type 36
SYStem.Line ADDR Shared address pins 36
SYStem.Line SRDY SRDY pin 37
SYStem.Option CLKSEL Clock select 37
SYStem.Option IMDIS Internal memory disable 37
SYStem.Option SREN Show read enable 37

Special Settings 186CC/CU/CH and Restrictions .............................................................. 38

Restrictions 186CC/CU/CH 38
SYStem.Line SRDY SRDY pin 38
SYStem.Line ARDY ARDY pin 39
SYStem.Option CLKSEL Clock select 39

Special Settings V40/V50 and Restrictions ........................................................................ 40

Restrictions V40/V50 40

Exception Control ................................................................................................................ 41

Reset 42

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 2
 Reset Input (not 8086/8088/V20/V30) 42
Reset Input (8086/8088/V20/V30) 43
NMI 43
HOLD 44
DMA Modes 44
SYStem.Line HOLD Enable HOLD line (emulation stopped) 44
Interrupt and Timer Control 45
Interrupt Stimulation 47
INT0 48
Trap Trigger 50

Refresh Operation ................................................................................................................ 51

FPU ........................................................................................................................................ 51
I/O Connector for Coprocessor (8086/8087) 52

Memory Classes ................................................................................................................... 53

Segmentation ........................................................................................................................ 55

Banked Target Systems ....................................................................................................... 56

Memory and I/O Access Routines 58

Monitor Extensions .............................................................................................................. 59

State Analyzer ....................................................................................................................... 60

Keywords for the Trigger Unit 60
General Keywords for the Trigger Unit 60
8086/8088/V20/V30MAX Keywords for the Trigger Unit 61
8086/8088/V20/V30MIN Keywords for the Trigger Unit 62
80(C)186(XL)/80(C)188(XL)/EA/EB/EC/EM/ES/ER Keywords for the Trigger Unit 62
V40/V50 Keywords for the Trigger Unit 64
Keywords for the Display 65
General Keywords 65
8086/8088/V20/V30MAX Keywords 65
8086/8088/V20/V30MIN Keywords 65
80(C)186(XL)/80(C)188(XL)/EA/EB/EC/EM/ES/ER/ED/CC Keywords 65
V40/V50MIN Keywords 66
Dequeueing 66

Port Analyzer ........................................................................................................................ 67

Keywords for the Port Analyzer (8086/8088/V20/V30) 67
Keywords for the Port Analyzer (80(C)186(XL)/80(C)188(XL)/EA) 68
Keywords for the Port Analyzer (80186EB/80188EB) 69
Keywords for the Port Analyzer (80186EC/80188EC) 70
Keywords for the Port Analyzer (18xEM/18xES/18xER/186ED) 71
Keywords for the Port Analyzer (V40/V50) 73
Input Connector for free Channels (8086/8088/80186/80188) 74
Input Connector for free Channels (80186EB/80188EB) 74
©1989-2019 Lauterbach GmbH
ICE Emulator for the 80186 and 80196 3
 Input Connector for free Channels (18xEM/18xES/18xER/186ED/CC) 75

Compilers .............................................................................................................................. 76

3rd-Party Tool Integrations ................................................................................................. 77

Realtime Operation Systems ............................................................................................... 79

Emulation Frequency ........................................................................................................... 80

Emulation Modules .............................................................................................................. 81

Module Overview 81
Order Information 82

Operating Voltage ................................................................................................................ 83

Physical Dimensions ........................................................................................................... 84

Adapter .................................................................................................................................. 93

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 4
ICE Emulator for the 80186 and 80196

Version 06-Nov-2019

P:0040:07A0 \\MCC\MCC\_sieve+29 ........... MIX AI

E::w.d.l
addr/line code label mnemonic comment
{
576 prime = i + i + 3;
P:0040:07A0 8BC6 mov ax,si
P:0040:07A2 D1E0 shl ax,1
P:0040:07A4 050300 add ax,3
P:0040:07A7 8946FE mov [bp-2],ax
577 k = i + prime;
P:0040:07AA 8BFE mov di,si
P:0040:07AC EB05 jmp 7B3
while ( k <= SIZE )
{
580 flags[ k ] = FALSE;
P:0040:07AE C685D80400 mov byte ptr [di+4D8],0

Cy _ AX 5 BX 12 SP >0040 E::w.v.l %m %r %t
P _ CX 5 DX 0BC -06 000B sieve()
Ac _ DS 2F3 SI 2 -04 0002 (auto int) prime = 5
Zr _ ES 2F3 DI 15 -02 0005 (auto int) count = 2
S _ SS 2F3 SP 4562 FP >457E (register int) i = 2
T _ BP 456A +02 076F (register int) k = 21

For general informations about the In-Circuit Debugger refer to the “ICE User’s Guide” (ice_user.pdf). All
general commands are described in “PowerView Command Reference” (ide_ref.pdf) and “General
Commands and Functions”.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 5
Warning

NOTE: Do not connect or remove probe from target while target power is ON.

Power up: Switch on emulator first, then target

Power down: Switch off target first, then emulator

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 6
Quick Start

Before debugging can be started, the emulator must be configured by hardware and software:

1. Check DIP-switch setting (chapter Configuration)

2. Create setup file (next)

Ready to run setup files for most standard compilers can be found on the software CD in the directory
…/Demo/I86/Compiler. All setup files are designed to run the emulator stand alone without target
hardware.

The following description should make the initial setup (to run the emulator together with the target
hardware) easier. It describes a typical setup with frequently used settings. It is recommended to use the
programming language PRACTICE to create a batch file, which includes all necessary setup commands.
PRACTICE files (*.cmm) can be created with the PRACTICE editor pedit (Command: PEDIT <file name>)
or with any other text editor.

A basic setup file includes the following parts:

1. Set system options

2. Select dualport mode (optional)

3. Set mapper (optional)

4. Select frequency (optional)

5. Activate the emulator

6. Load application file (optional)

7. Initialize registers and chipselect units (optional)

8. Set breakpoints (optional)

9. Start application

10. Stop application (optional)

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 7
 Now a typical example, how to setup the system:

1. Set system options

The system window controls the CPU specific setup. Please check this window very carefully and set
the appropriate options. Use the ? button in the main tool bar and click to the option check box
(Command: HELP.PICK) to get online help in a pop up window.

system.down ; switch the system down

system.reset ; all system settings to default
system.option once on ; on: if clip over adapter is used
; important: ext. pull-up FLT# > 6.8K
system.option v33 on ; on: if 3.3 V module is used

2. Select dualport mode (optional)

Dualport allows access to emulation RAM, while emulation is running. This is necessary to display
variables, set breakpoints or display the flag listings while the emulation is running. System.access
selects how dualport access is done.

system.access request ; request: HOLD/HLDA line is used for

; dualport
; refresh: 186 Enhanced Mode only
; nodelay: frequency limited
; denied: dualport is disabled

3. Set mapper (optional)

The mapper controls the memory access of the CPU. This means the use of internal or external
memory, the number of wait states, the bus width etc. Address ranges must be defined by using
memory classes.

map.reset ; reset mapper (all external)

map.mode fast ; use fast mode, if possible
map.ram ap:0x000000--0x00ffff ; emulation RAM: use low 64KB
map.ram ap:0x0f0000--0x0fffff ; emulation RAM: use top 64KB
; memory: use low 64KB internal
map.intern ap:0x000000--0x0ffff ; use top 64KB external
; use top 64KB dualport

Select frequency (optional)

The CPU can be clocked by internal (emulator) or external (target). If the internal clock is used, the
clock is provides by the VCO of the emulator. The setting of the internal clock is done by the VCO
command.

The current CPU frequency can be displayed in the counter window (Command: Count).

vco.clock 25. ; frequency: set to 25 MHz

; (necessary if internal clock used)

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 8
 4. Activate the emulator

When the emulator is activated a monitor program is loaded into hidden emulator memory. After the
load and the falling edge of RESET the monitor program is started. This program allows access to
user memory (data.dump, data.list) and register and gives control to start and stop the emulation.

system.mode emulext ; system up: emulation external

; (target, ext. clock)
; or: system.mode aloneint
; (stand alone, int. clock)

5. Load application file (optional)

Application can be loaded by various file formats. OMF86 file is often used to load code and symbol
information. For information about the load command for your compiler see Compiler.

data.load.omf file.abs /nocode ; load application file (symbols

; only) emulator mmu is set
; automatically

6. Initialize registers and chipselect units (optional)

For correct data.list and data.dump after RESET it necessary to initialize chipselect units.
Stackpointer should be initialized by hand if debugging is started at RESET until it is initialized by the
program. Stack is used for the emulator break system.

register.set sp 0x1000 ; initialize stack pointer to allow

; debugging from begin of program
data.set io:0x0ffa0 %w 0x0fc3c ; initialize UCS

7. Set breakpoints (optional)

There are several ways to set breakpoints (Command: Break.Set). Breakpoints can be displayed
using the Break.List command. Information regarding HLL lines (for HLL breakpoints) is loaded
automatically when a HLL file is loaded.

breakpoint.set main /program ; set program break on function

; main
breakpoint.set counter /write ; set write break on variable
; counter

8. Start application

Application can be started with giving a break address. For example “go main” starts the application
and stops at symbol main.

go ; run application

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 9
 9. Stop application (optional)

Application can be breaked manually by using the Break command. If application executed a halt
instruction the command Break.HALT should be used to terminate the application.

break ; break application by hand

It is recommended to check the following chapters for all questions regarding the correct setup:

• Configuration

• General SYStem Settings and Restrictions

• Special Settings 8086/8088/V20/V30

• Special Settings 80186/80188

• Special Settings C186(XL)/C188(XL)/EA and Restrictions

• Special Settings 80186EB/80188EB/80186EC/80188EC

• Special Settings 186EM, 188EM and Restrictions

• Special Settings 186ES, 188ES, 186ED and Restrictions

• Special Settings 186ER/188ER and Restrictions

• Special Settings 186CC and Restrictions

• Special Settings V40/V50 and Restrictions

• Troubleshooting

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 10
Troubleshooting

Hang-Up

If you are not able to stop the emulation, there could be some typically reasons:

Halt The program runs to HALT state. No cycles are generated by the
CPU and the trigger system can not work. Use Break.Halt to
generate a NMI interrupt and stop then the emulation.

No READY Signal If TIMOUT is not specified, the CPU cycle will not be completed,
when the READY signal is missing. You can verify this state by
checking the CYCLE signal with the counter function. If low, the
CPU is stopped in the middle of the cycle. On dual-port access an
error occurs and the emulator system changes to reset state.

Clock Error The clock lines between the target and the oscillator replacement
are very short. Therefore normally no problems should occur when
using an external crystal. Be sure that the capacitors on the target
have a value of 20 pF minimum and are connected with short routes
to the CPU socket. If the clock input signal is only used by the CPU,
the clock may be generated by the emulator system using the
EmulInt mode.

NMI Break system will not work if NMI input is active at the same time a
breakpoint or a trigger point is reached. Be sure that on emulation
NMI is not used by the target system. Otherwise switch off the NMI
line by eXeption.Enable NMI Off.

RESET and HOLD Reset and Hold signals from the target system stop emulation
immediately. If these signals are constantly active, memory dump
will be possible, but no emulation.

Analyzer Malfunction If you switch off the analyzer and the CPU has stopped operation
within a cycle, an invalid display will occur. Make a SYStem.Up
command to see the correct trace information.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 11
Dual-Port Errors

Dual-port errors may occur by the following conditions:

1. The length of the CPU cycle is extended by wait cycles, so that the request timeout signal is
generated.

2. External DMA requests (single cycles) are too long.

To solve problems with dualport error first increase the SYStem.TimeReq value. Be sure of that the
SYStem.TimeOut value is larger than the access time limit. If it is not possible to solve the problem by
changing the values, you must switch to DENIED mode. In this mode no access to memory is possible while
running realtime emulation. The internal dual-port access can increase the reaction time for external DMA
requests. The performance reduction by the dual-port access is typically 1% with some data windows (dual-
ported) on the screen and may be at max. 5% when using dynamic emulation memory.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 12
FAQ

Why is the location after break wrong ?

Most emulators use some bytes of user stack for the break system. Therefore it
is necessary to have valid stack, if single step or breakpoints are used.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 13
Configuration

The configuration of different target CPU's is done by changing the probe or the CPU. The port analyzer is
an optional unit, which is plugged on the ICE186 board. The software is configured automatically.

The CPU type on the probes must be jumpered. Otherwise the message Configuration Error may appear.

DIP-Switch Setting of 8086/8088/V20/V30

.

Module 8086

++++++++++++++++++++++++

++++++++++++++++++++++++
++++++++++++++++++++++++
CPU type 1 2 3 4

8086 OFF ON - -
1234 8088 ON ON - -
V30 OFF OFF - -
V20 ON OFF - -

To select another CPU type, it is necessary to exchange the CPU on the module!

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 14
DIP-Switch Setting of 80186(EA)/80188(EA)/80C186(XL)/80C188(XL)
Module 80186

++++++++++++++++++++++++

++++++++++++++++++++++++
++++++++++++++++++++++++
CPU type 1 2 3 4

80C186(XL) OFF OFF ON OFF

1234 80C188(XL) ON OFF ON OFF
80186 OFF ON ON OFF
80188 ON ON ON OFF
80C186EA OFF OFF OFF ON
80C188EA ON OFF OFF ON

Adapter 80186

CPU type 1 2 3

80C186(XL) OFF OFF ON

123 80C188(XL) OFF OFF ON
80186 OFF OFF ON
80188 OFF OFF ON
80C186EA ON ON OFF
80C188EA ON ON OFF

To select another CPU type, it is necessary to exchange the CPU on the module!

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 15
DIP-Switch Setting of 80186EB/80188EB/80186EC/80188EC, V40/V50
Module 80186EB/EC,V40/V50

++++++++++++++++++++++++

++++++++++++++++++++++++
++++++++++++++++++++++++
CPU type 1

80C186EB/EC,V50 OFF
1 80C188EB/EC,V40 ON

To select another CPU type, it is necessary to exchange the CPU on the module!

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 16
DIP-Switch Setting of 186EM/ES/ER/ED/188EM/ES/ER
Module 186EM/ES/ER

2
CPU type 1 2

186EM(LV) OFF OFF

186ES(LV) OFF OFF
186ER OFF OFF
188EM(LV) ON ON
1 188ES(LV) ON ON
188ER ON ON

CPU type selection (old pcb)

Top PCB, bottom view (old pcb)

Adapter 186EM/ES/ER/ED

Switch 1 2 3 4 7 8

DEN- function ON OFF x x x x

PIO5 function OFF ON x x x x
1
DT/R- function x x ON OFF x x
PIO4 function x x OFF ON x x
8
186EM,ES,ER,ED x x x x OFF OFF
188EM,ES,ER x x x x ON ON

DEN- and DT/R- function is selected

by default

Bottom PCB, top view (old pcb) Switch 5, 6 is not used

Bottom PCB, bottom view (new pcb)

To select another CPU type, it is necessary to exchange the CPU on the module and to set SYStem.CPU
correctly.

NOTE: When using 186ER/188ER, one 0R jumper must be closed on bottom side of
top pcb to guarantee 3.3V operation also in standalone mode.
SYStem.Option V33 must be set to on.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 17
 Module 186EM/ES/ER/ED

J 472 332 Jumper is left of Resistor 4K7 (472)

CPU type J (Jumper)

186EM(LV) open
186ES(LV) open
186ER 0R (closed)
186ED(LV)

open
188EM(LV) open
188ES(LV) open
Top PCB, bottom view (new pcb)
188ER 0R (closed)

Jumper selection new pcb

DIP-Switch Setting of 186CC/CH/CU

Adapter 186CC
Switch SW1 1 2 3 4 5 6 7 8

DEN-/DS-function 1 0 x x x x x x
PIO30 function 0 1 x x x x x x
DT/R- function x x 1 0 x x x x
PIO29 function x x 0 1 x x x x
WR- function x x x x 1 0 x x
PIO15 function x x x x 0 1 x x
1 8 BHE- function x x x x x x 1 0
PIO34 function x x x x x x 0 1
SW1
1 8 Switch SW2 1 2 3 4 5 6 7 8
SW2
ALE function 1 0 x x x x x x
PIO33 function 0 1 x x x x x x

Bottom PCB, bottom view

Setting: 1 - ON, 0 - OFF, x - don’t care

DEN-, DT/R-, WR-, BHE-, ALE function are

set by default.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 18
Basics

Emulation Modes

E::w.sys
system Mode Clock TimeReq Option
Down RESet  VCO 1.000ms MAX
 Up Analyzer Low TimeOut REFresh
Monitor Mid 50.000us RamWait
RESet ResetDown High BreakWin
ResetUp Line ONCE
cpu-type NoProbe Access HOLD Enhanced
I80C186 AloneInt Nodelay TestClock
AloneExt REFresh
EmulInt  Request
BankMode EmulExt Denied
 OFF
INTern BankFile
EXTern

The emulation head can stay in 6 modes. The modes are selected by the SYStem.Up or the SYStem.Mode
command.

Format: SYStem.Mode <mode>

<mode>: ResetDown
ResetUp
AloneInt
AloneExt
EmulInt
EmulExt

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 19
 Reset Down Target is down, all drivers are in tristate mode.

Reset Up Target has power, drivers are logically in inactive state, but not tristate.

Alone Internal Probe is running with internal clock, driver inactive. This mode is used for
'standalone' operation.

Alone Exter- Probe is running with external clock, driver inactive.

nal

Emulation Probe is running with internal clock, strobes to target are generated.
Internal

Emulation Probe is running with external clock, strobes to target are activated.
External

In active mode, the power of the target is sensed and by switching down the target the emulator changes to
RESET mode. The probe is not supplied by the target. When running without target, the target voltage is
simulated by an internal pull-up resistor.

The probe uses an active buffered emulation technology. Emulation is possible in a target system with
hardware errors in the address or data bus. The basic module supports Intel, Siemens, AMD and NEC
CPUs.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 20
Dual-Port Access

Format: SYStem.Access <option>

<option>: Nodelay
REFresh
Request
Denied

Nodelay This method is used at lower speed up to 12 MHz. The gap between the CPU
cycles is used for memory access.

REFresh Only usable on 188/186 CPU in Enhanced Mode when generating refresh
cycles. Uses the refresh cycles for making the dual-port access.

Request To realize the dual-port access (emulation memory) at high frequencies the
HOLD-line (186) of the CPU is used. Dual-port accesses are only allowed while
no external request to the bus occurs and the CPU cycle is completed. If the
emulation CPU is in RESET state of the CPU the system controller will always
access the emulation memory. Not usable in 8086/8088/V20/V30 Max Mode.

Denied Dualport access is not possible while the emulation is running.

Dualport allows access to emulation RAM, while emulation is running. This is necessary to display variables,
set breakpoints or display flag listings while the emulation is running. Dualport access is only possible for
emulator internal RAM.

SYStem.Clock Clock generation

Format: SYStem.Clock <option>

<option>: VCO
High
Mid
Low

VCO Variable frequency 1 … 35 MHz.

Low, Mid, 2.5, 5.0 or 10.0 MHz.

High

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 21
General SYStem Settings and Restrictions

General Restrictions

Memory Setup All 186 type in-circuit emulators need memory in the stack area (SS:SP)
to break correctly. If you get an invalid IP and CS value after stopping the
program, the stack area may be outside the memory area. The break
system needs additionally 12 bytes on the top of the stack. To set
breakpoints on I/O cycles, there must be free memory for this area.
Therefore reserve 64 K of memory for the I/O/ area if possible.

Register Setup The TF (Trap Flag) register trace flag must not be set to 1.

Internal I/O The internal I/O should not be set to be memory mapped from location
Relocation 0..7fff.

Interrupt The NMI signal is used for stopping emulation. The “INT 3” instruction
Restrictions and the TrapFlag are used for single stepping and program breaks.
Therefore the interrupt vectors 1, 2 and 3 may not be used by the target
program when breakpoints are set or single stepping is done. However
the vector entries should be defined, as the first locations of the code,
addressed by these vectors, are fetched but not executed. If the vectors
are not defined, this fetch can cause unpredictable results by reading
memory or trigger by accessing wrong data areas.

Pending Interrupts When internal interrupts are pending and the emulation is started at a
program breakpoint, the interrupt routine will be executed once and the
program will stop at the same breakpoint again. A solution to this problem
can be to execute one step to skip over the breakpoint location. An other
solution is to disable or reset the timer while the emulation is stopped.
This can be done by an emulation monitor extension (SYStem.MonFile).

Pending Interrupts When executing an assembler step and internal interrupts are pending,
during Single Step the emulator will step into the interrupt program. This can be changed
either by preventing the interrupt, e.g. stop the timer while the emulation
is stopped (see “Pending Interrupts”) or by disabling the interrupt bit in
the CPU (command SETUP.IMASKASM). For HLL steps the problem can
be solved in the same ways (command SETUP.IMASKHLL) or by
temporarily removing the HLL breakpoint of the current line during the
step (SETUP.StepInt).

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 22
 Pending Interrupts When the emulation is started on an active breakpoint, and an interrupt is
when starting pending, the target will execute the interrupt routine and return to the
emulation same address. To prevent this behavior activate the SETUP.StepBreak
and SETUP.IMASKASM commands will force a single step before
starting the real-time emulation.

Accessing location A read access to location 0:4 in single step mode, or while a hardware
0:4 breakpoint is pending will cause an undefined behavior of the program.

SYStem.Option BreakWin Break window

Format: SYStem.Option BreakWin [ON | OFF]

All program breakpoints are hardware based. The operation is done by replacing the opcode with an INT3
instruction. For not breaking on every INT3 code in the target program break sequencing is only possible
during some cycles after the breakpoint cycle. In some cases it may be an advantage to switch off this
feature (for example when using INT3 as software breakpoints in relocating programs).

NOTE: If the Break Window is OFF, accesses to vector table stop the emulation.

SYStem.Option ONCE On-circuit emulation

Format: SYStem.Option ONCE [ON | OFF]

This option selects the ONCE mode. The CPU soldered on the target system is switched off on target reset.
Emulator must be in SYS.M ResetDown when target reset line is going inactive. To use this option a special
clip-over adapter is needed.

SYStem.Option RamWait Wait states

Format: SYStem.Option RamWait [ON | OFF]

One wait state for all memory cycles. Additional wait states will be generated if MAP.Wait is defined.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 23
SYStem.Option REFresh Trace refresh cycles

Format: SYStem.Option REFresh [ON | OFF]

Normally refresh cycles are not used for trigger and trace functions. On default it is switched off.

SYStem.Option REL Relocation register

Format: SYStem.Option REL <value>

If running in Enhanced Mode, the refresh function must be stopped when emulation breaks. Set REL option
must be set to the same value the user program write to the REL register.

The adjusted I/O base address can be read back with the functions IOBASE() and IOBASE.ADDRESS().
They return the offset or the complete address (offset and access mode) for the I/O area.

SYStem.Option SPLIT Access control on splitted memory

Format: SYStem.Option SPLIT [ON | OFF]

When MAP.SPLIT command is used to split program and data memory, SYStem.Option SPLIT ON forces
the emulator to use dualport on data.dump p: windows (also data.list). This means dumps to program
memory is only possible via dualport to emulator internal memory.

SYStem.Option TestClock Clock fail detection

Format: SYStem.Option TestClock [ON | OFF]

Missing clock signals force emulator system to generate a Target Clock Fail error and to set emulation
system to RESET. To use the Power-Down modes of the CPU the clock test logic must be blocked.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 24
SYStem.Option V33 3.3 V power fail detection

Format: SYStem.Option V33 [ON | OFF]

The emulator has logic to detect a power fail. This logic has to be adjusted for 3.3Volt CPUs (AM18xER,
186CC/CU/CH for example).

Continue with CPU specific Special Settings and Restrictions

The following Special Settings and Restrictions are subdivided by CPU type.

• Special Settings 8086/8088/V20/V30

• Special Settings 80186/80188

• Special Settings C186(XL)/C188(XL)/EA and Restrictions

• Special Settings 80186EB/80188EB/80186EC/80188EC

• Special Settings 186EM, 188EM and Restrictions

• Special Settings 186ES, 188ES, 186ED and Restrictions

• Special Settings 186ER/188ER and Restrictions

• Special Settings 186CC and Restrictions

• Special Settings V40/V50 and Restrictions

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 25
Special Settings 8086/8088/V20/V30

SYStem.Option FPU Floating-point unit

Format: SYStem.Option FPU [ON | OFF]

To allow a correct emulator fpu support, 8087 must always be plugged on the pod. If 8087 coprocessor is
used (on 8086 pod) in stand alone mode, this option must be switched to ON. If 8087 coprocessor is used
(on 8086 pod) in external mode (together with a target), this option should be switched to OFF and some
additional lines connected. SYStem.Option MAX must be switched to ON.

8087 is connected internally (on the pod) with 8086. This means if standalone mode is used and
SYStem.Option FPU is ON, all necessary connections between 8086 and 8087 are routed on the emulator
pod. To give user more flexibility the following 8087 signals are located on a 10-pole connector on the
emulator pod:

9 7 5 3 1
10 8 6 4 2

1 CLK 2 GND
3 RQ/GT0- 4 GND
5 RQ/GT1- 6 GND
7 INT 8 GND
9 BUSY 10 GND

In standalone mode CLK is connected to emulator CPU clock. In external clock mode 8087 clock must
always be supplied on pin 1 of the connector! RQ/GT1- line of 8087 is always connected to the connector.

SYStem.Option FPU controls the following lines:

SYS.O FPU ON OFF

8087 signal 8086 target socket signal

RQ/GT0- connected with RQ/GT1- open
INT connected with INTR open
BUSY connected with TEST- open

This means if pod is connected to a target, sys.o fpu must be switched off and the above listed signals
connected via the 10-pole connector to the target.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 26
 Summary:

10-pole connector

1 CLK CLK input if external clock mode

3 RQ/GT0- RQ/GT0- I/O if SYStem.Option FPU is OFF
5 RQ/GT1- RQ/GT1- I/O of FPU (always connected)
7 INT INT output if SYStem.Option FPU is OFF
9 BUSY BUSY output if SYStem.Option FPU is OFF

SYStem.Option MAX MIN/MAX mode

Format: SYStem.Option MAX [ON | OFF]

8086/8088/V20/V30 CPUs may run in two modes. The modes differ in the pin function of some pins. Pin
MN/MX- (S/LG-) select minimum or maximum mode. This MIN/MAX selection should be done before
leaving the emulator reset state.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 27
Special Settings 80186/80188

SYStem.Option FPU Floating-point unit

Format: SYStem.Option FPU [ON | OFF]

If 80187 coprocessor is used (on the target) this option must be switched to ON.

SYStem.Option MAX MIN/MAX mode

Format: SYStem.Option MAX [ON | OFF]

80186/80188 controls via the RD- line two different modes (MIN: standard, MAX: queue status). This
MIN/MAX selection should be done before leaving the emulator reset state.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 28
Special Settings C186(XL)/C188(XL)/EA and Restrictions

Restrictions 80C186(XL)/80C188(XL)/80C186EA/80C188EA

SYStem.Option Enhanced Enhanced mode

Format: SYStem.Option Enhanced [ON | OFF]

RCU The refresh control unit of the 80C186 is disabled, when the emulation is
stopped. Refresh of external dynamic memory can be made by the
REFresh.StandBy command. The RCU control register should not be modified
when the emulation is stopped. The value displayed in memory windows will be
wrong.

If running in target systems the CPU is automatically started in Enhanced mode if the target system uses
this mode. In standalone mode this feature must be stimulated by the emulator system.

SYStem.Option FPU Floating-point unit

Format: SYStem.Option FPU [ON | OFF]

If 80187 coprocessor is used (on the target) this option must be switched to ON.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 29
Special Settings 80186EB/80188EB/80186EC/80188EC

SYStem.Option FPU Floating-point unit

Format: SYStem.Option FPU [ON | OFF]

If 80187 coprocessor is used (on the target) this option must be switched to ON.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 30
Special Settings 186EM, 188EM and Restrictions

Restrictions 186EM, 188EM

Peripheral Register PIO29/S6 at the 18xEM must be programmed as S6 signal. Therefore

Setup PIO29/S6 monitor program initializes PIO DIRECTION REGISTER 1 (offset: 78h)
to 0dfffh (instead of 0ffffh). It is important to initialize PIO DIRECTION
REGISTER 1 with the first executed instructions after RESET.

Peripheral Register CLKOUTA line must not be disabled by PDCON (offset: 0f0h), because
Setup CLKOUTA emulator needs this signal.

Peripheral Register LMCS (offset: 0a2h) controls waitstates and use of SRDY/ARDY pin for
Setup Chip Select LCS- output. For frequencies above 28 MHz. monitor program needs at
Unit least one wait state for correct working. LMCS must be programmed to
use either more than zero wait or external ARDY/SRDY.

SYStem.CPU CPU type

Format: SYStem.CPU [186EM]

Select used CPU type. Use 186EM for 188EM(LV)/186EM(LV). CPU type must be set before any other
system setting.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 31
SYStem.Line ADDR Shared address pins

Format: SYStem.Line ADDR <mask>

18xEM have shared A17-A19/PIO7-PIO9 pins. If pins should be used as address lines, the configuration
must be set by the SYStem.LINE ADDR command. Each set bit indicates that the address line should be
used.

SYStem.Line SRDY SRDY pin

Format: SYStem.Line SRDY [ON | OFF]

18xEM have a shared SRDY/PIO6 pin. It is necessary to switch SYStem.Line SRDY to on, if function SRDY
is used. If PIO6 is used, SYStem.Line SRDY must be switched off.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 32
Special Settings 186ES, 188ES, 186ED and Restrictions

Restrictions 186ES, 188ES, 186ED

Peripheral Register PIO29/S6 at the 18xES/186ED must be programmed as S6 signal.

Setup PIO29/S6 Therefore monitor program initializes PIO DIRECTION REGISTER 1
(offset: 78h) to 0dfffh (instead of 0ffffh). It is important to initialize PIO
DIRECTION REGISTER 1 with the first executed instructions after
RESET.

Peripheral Register The watchdog timer at the 18xES/186ED is disabled from monitor
Setup Watchdog program via WDTCON (offset: 0e6h).

Peripheral Register CLKOUTA line must not be disabled by PDCON (offset: 0f0h), because
Setup CLKOUTA emulator needs this signal.

Peripheral Register LMCS (offset: 0a2h) controls waitstates and use of SRDY/ARDY pin for
Setup Chip Select LCS- output. For frequencies above 28 MHz. monitor program needs at
Unit least one wait state for correct working. LMCS must be programmed to
use either more than zero wait or external ARDY/SRDY.

Peripheral Register The bus width of LMCS (offset: 0a2h) must be set to 16bit. This is done in
Setup Chip Select AUXCON register (offset: 0f2h). The reason for this restriction is the
Unit and AUXCON internal running monitor program of the emulator, which must run under
bus width Control 16bit bus width.

SYStem.CPU CPU type

Format: SYStem.CPU [186ES | 186ED]

Select used CPU type. Use 186ES for 188ES(LV)/186ES(LV) or 186ED for 186ED(LV). CPU type must be
set before any other system setting.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 33
SYStem.Line ADDR Shared address pins

Format: SYStem.Line ADDR <mask>

18xES/186ED have shared A17-A19/PIO7-PIO9 pins. If pins should be used as address lines, the
configuration must be set by the SYStem.LINE ADDR command. Each set bit indicates that the address
line should be used.

SYStem.Line SRDY SRDY pin

Format: SYStem.Line SRDY [ON | OFF]

18xES/186ED have a shared SRDY/PIO6 pin. It is necessary to switch SYStem.Line SRDY to on, if function
SRDY is used. If PIO6 is used, SYStem.Line SRDY must be switched off.

Mapping

For basic function of mapper please refer to Emulator User’s Guide.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 34
MAP.BUS8 Bus width mapping

Format: MAP.BUS8 <range>

Format: MAP.NOBUS8 [<range>]

18x/186ED have a chip select dependent bus width control. This control is implemented in AUXCON
register (Offset: F2h). If any of the chip select units is used in 8bit mode, MAP.BUS8 must be set for the
corresponding range. 16bit bus width is the default selection

map.bus8 d:0x040000++0xffff ; MSIZ=1

map.nobus8 ; remaps all to 16 bit

The MAP.RESet command sets the bus width definition to 16 bit.

NOTE: The bus width of LMCS (offset: 0a2h) must be set to 16bit. This is done in
AUXCON register (offset: 0f2h). The reason for this restriction is the internal
running monitor program of the emulator, which must run under 16bit bus width.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 35
Special Settings 186ER/188ER and Restrictions

Restrictions 186ER/188ER

Peripheral Register PIO29/S6 at the 18xER must be programmed as S6 signal. Therefore

Setup PIO29/S6 monitor program initializes PIO DIRECTION REGISTER 1 (offset: 78h)
to 0dfffh (instead of 0ffffh). It is important to initialize PIO DIRECTION
REGISTER 1 with the first executed instructions after RESET.

Peripheral Register CLKOUTA line must not be disabled by PDCON (offset: 0f0h), because
Setup CLKOUTA emulator needs this signal.

Peripheral Register LMCS (offset: 0a2h) controls waitstates and use of SRDY/ARDY pin for
Setup Chip Select LCS- output. For frequencies above 28 MHz. monitor program needs at
Unit least one wait state for correct working. LMCS must be programmed to
use either more than zero wait or external ARDY/SRDY.

Internal RAM The 18xER internal RAM must not be used at base address 0 (lowest
(Onchip) 32 KByte). All other addresses are allowed. See also
SYStem.Option IMDIS and SYStem.Option SREN.

SYStem.CPU CPU type

Format: SYStem.CPU [186ER]

Select used CPU type. Use 186ER for 188ER or 186ER. CPU type must be set before any other system
setting.

SYStem.Line ADDR Shared address pins

Format: SYStem.Line ADDR <mask>

18xER has shared A17-A19/PIO7-PIO9 pins. If pins should be used as address lines, the configuration must
be set by the SYStem.LINE ADDR command. Each set bit indicates that the address line should be used.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 36
SYStem.Line SRDY SRDY pin

Format: SYStem.Line SRDY [ON | OFF]

18xER has a shared SRDY/PIO6 pin. It is necessary to switch SYStem.Line SRDY to on, if function SRDY is
used. If PIO6 is used, SYStem.Line SRDY must be switched off.

SYStem.Option CLKSEL Clock select

Format: SYStem.Option CLKSEL [<*4 | *1 | /2>]

Use this option to select clocking mode. CPU input clock is multiplied by four (default), multiplied by one or
divided by two. If divide by two mode is selected, the PLL is disabled.

SYStem.Option IMDIS Internal memory disable

Format: SYStem.Option IMDIS [ON | OFF]

Use this option to disable the 18xER onchip RAM (32 kByte). When this option is switched to ON, onchip
memory is always hidden, also if IMCS register bit 9 (internal RAM enable) is set. If option is switched to
OFF, onchip memory is available if IMCS register bit 9 is set. Onchip memory can be used, but not at base
address 0 (lowest 32 kByte). For analyzer trace to onchip memory see under SYStem.Option SREN.

SYStem.Option SREN Show read enable

Format: SYStem.Option SREN [ON | OFF]

Use this option to show read data on the 18xER onchip RAM accesses. Note that if a byte read is being
shown, the unused byte will also be driven on the AD15-AD0 bus.

When this option is switched to ON, read data on onchip memory accesses are always visible, also if IMCS
register bit 10 (show read) is reset. If option is switched to OFF, read data on onchip memory accesses are
available, if IMCS register bit 10 is set. Onchip memory can be used, but not at base address 0 (lowest 32
kByte).

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 37
Special Settings 186CC/CU/CH and Restrictions

Restrictions 186CC/CU/CH

Peripheral Register BHE-/PIO34 must be programmed as BHE- signal. ADEN- is held low
Setup BHE- on power-on reset by the emulator. Therefore the AD bus drives both
/PIO34/ADEN- addresses and data, regardless of how software configures the DA bit
setting.

Peripheral Register The watchdog timer is disabled from monitor program via WDTCON
Setup Watchdog (offset: 3e0h).

Peripheral Register CLKOUTA line must not be disabled by SYSCON (offset: 3f0h),
Setup CLKOUTA because emulator needs this signal.

Peripheral Register LMCS (offset: 3a2h) controls waitstates and use of SRDY/ARDY pin
Setup Chip Select for LCS- output. For frequencies above 28 MHz. monitor program
Unit needs at least one wait state for correct working. LMCS must be
programmed to use either more than zero wait or external ARDY/SRDY.
If DRAM is used for LCS (LDEN=1) ARDY/SRDY pin is ignored.
Therefore one internal wait should be programmed in the LMCS
register.

Peripheral Register The bus width of LMCS (offset: 3a2h) must be set to 16bit. The reason
Setup Chip Select for this restriction is the internal running monitor program of the
Unit and AUXCON emulator, which must run under 16bit bus width.
Bus width Control

SYStem.Line SRDY SRDY pin

Format: SYStem.Line SRDY [ON | OFF]

186CC/CU/CH has a shared SRDY/PIO35 pin. It is necessary to switch SYStem.Line SRDY to ON, if
function SRDY is used. If PIO35 is used, SYStem.Line SRDY must be switched OFF. In this mode a
10kOhm pull-down resistor is active. A 100kOhm pull-down resistor is always active.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 38
SYStem.Line ARDY ARDY pin

Format: SYStem.Line ARDY [ON | OFF]

186CC/CU/CH has a shared ARDY/PIO8 pin. It is necessary to switch SYStem.Line ARDY to ON, if function
ARDY is used. If PIO8 is used, SYStem.Line ARDY must be switched OFF. In this mode a 10kOhm pull-
down resistor is active. A 100kOhm pull-down resistor is always active.

SYStem.Option CLKSEL Clock select

Format: SYStem.Option CLKSEL [<*2 | *4 | *1/BYPASS>]

Use this option to select clocking mode. CPU Input clock is multiplied by two (default), by four or by one or
used without PLL (bypass). The data sheet should be checked for the allowed frequency ranges.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 39
Special Settings V40/V50 and Restrictions

Restrictions V40/V50

Waitstates For memory accesses, not more than 7 waitstates should be used. Using more
waitstates inhibits emulator to break correctly.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 40
Exception Control

E::w.x
exception Activate Enable Trigger Puls Puls
OFF  OFF OFF  OFF  OFF Single
 ON RESIN  ON ON RESIN Width
RESet HOLD  RESIN RESIN INT0 1.000us
 HOLD RESET HOLD PERiod
 NMI HOLD NMI 0.000
 INT0 HLDA EINT0+
 INT1 PULS EINT0- Vector
 INT2 VINT0+ 00 (000.)
 INT3 VINT0-
 TMRIN0
 TMRIN1
 DRQ0
 DRQ1

The exception control system depends on the processor used. The window shown here is for the
80(C)186/XL/EA. The exception control system can only control external interrupt sources (see also
General Restrictions)

Format: eXception.Enable ON

Format: eXception.Enable OFF

Format: eXception.Activate OFF

Format: eXception.Enable OFF

Enable ON Enable all exception lines.

Enable OFF Disable all exception lines.

Activate OFF Inactivate all exception lines.

Pulse OFF Disable all pulse exceptions.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 41
Reset

Reset Input (not 8086/8088/V20/V30)

+1 > Trace / X.Trigger

VCC

22k

RES- >
X.Enable- >=1 X.Activate- & > RES- (CPU)
Run- X.Puls-
Sys.Reset

Format: eXception.Enable RESIN [ON | OFF]

Format: eXception.Activate RESIN [ON | OFF]

Enable RESIN Enables the RESIN line.

Activate Activates the RESIN line.

RESIN

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 42
Reset Input (8086/8088/V20/V30)

+1 > Trace / X.Trigger

GND

22k

RESET >
X.Enable & X.Activate >=1 > RESET (CPU)
Run X.Puls
SYS.RESO

Format: eXception.Enable RESET [ON | OFF]

Format: eXception.Activate RESET [ON | OFF]

Enable RESET Enables the RESET line.

Activate Activates the RESET line.

RESET

NMI

+1 > Trace
GND

22k

NMI >
X.Enable & X.Activate >=1 > NMI (CPU)
Run X.Puls
Break

Format: eXception.Enable NMI [ON | OFF]

Enable NMI Enables the NMI line.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 43
HOLD

+1 > Trace / X.Trigger

GND

22k

HOLD >
X.Enable & X.Activate >=1 > HOLD (CPU)
Run X.Puls
Dualport

Format: eXception.Enable HOLD [ON | OFF]

Format: eXception.Activate HOLD [ON | OFF]

Enable HOLD Enables the HOLD line.

Activate Activates the HOLD line.

HOLD

DMA Modes

External DMA circuits request the bus by the HOLD signal. If realtime emulation is stopped external and
internal DMA circuits will not get access to the bus. They are requesting the bus, but no HLDA signal is
generated. If external DMA should be enabled at every time, the HOLD line will always have to be enabled.
Internal DMA functions are simultaneously stopped when emulation stop (Break by NMI).

While emulation is stopped, the DMA function will be interrupted for about 10 cycles if the CPU executes
internal monitor functions. This may force malfunction, if the DMA needs very fast memory access response
times.

SYStem.Line HOLD Enable HOLD line (emulation stopped)

Format: System.Line HOLD [ON | OFF]

This option allows DMA access without running realtime emulation. If external DMA should be enabled at
every time, the HOLD line must always be enabled (SYStem.Line HOLD ON). External DMA circuits are not
stopped on breakpoints.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 44
Interrupt and Timer Control

As interrupt signals or timer signals are bidirectional, the control is done by analog switches.

+1 > Trace

Target <> S1 <> CPU

22k 22k

GND GND S1 = 50  (HC4066)

Format: Exception.Enable <option> [ON | OFF]

<option>: INTR (8086/8088/V20/V30)

INT0 .. INT3 ((C)186(XL)/(C)188(XL)/80C186EA/80C188EA)
INT0 .. INT4 (80186EB/80188EB)
INT0 .. INT7 (80186EC/80188EC)
INTP1 .. INTP7 (V40/V50)
TMRIN0 ((C)186(XL)/(C)188(XL)/EA/EB/EC/EM/ES/ER/ED/CC)
TMRIN1 ((C)186(XL)/(C)188(XL)/EA/EB/EC/EM/ES/ER/ED/CC)
DRQ0 .. DRQ1 ((C)186(XL)/(C)188(XL)/EA/EM/ES/ER/ED/CC)
DRQ0 .. DRQ3 (V40/V50/80186EC/80188EC)

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 45
 DRQ0 Enables the DRQ0 line.

DRQ1 Enables the DRQ1 line.

DRQ2 Enables the DRQ2 line.

DRQ3 Enables the DRQ3 line.

INT0 Enables the INT0 line.

INT1 Enables the INT1 line.

INT2 Enables the INT2 line.

INT3 Enables the INT3 line.

INT4 Enables the INT4 line.

INT5 Enables the INT5 line.

INT6 Enables the INT6 line.

INT7 Enables the INT7 line.

INTP1 Enables the INTP1 line.

INTP2 Enables the INTP2 line.

INTP3 Enables the INTP3 line.

INTP4 Enables the INTP4 line.

INTP5 Enables the INTP5 line.

INTP6 Enables the INTP6 line.

INTP7 Enables the INTP7 line.

INTR Enables the INTR line.

TMRIN0 Enables the TMRIN0 line.

TMRIN1 Enables the TMRIN0 line.

ON Enables all exception line.

OFF Disables all exception lines.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 46
Interrupt Stimulation

Interrupt stimulation is only possible in Stand-Alone mode or if no external interrupt controller is used. The
simulation circuit supports level and edge triggered interrupts with and without external vector support.

+1 > Trace
GND

22k

INTx >
X.Enable INTx & >=1 > INTx (CPU)
X.Puls

Format: Exception.Puls <option> <time> <period>

<option>: INT0
EINT0+
EINT0-
VINT0+
VINT0-

The possible interrupt line depend on the CPU used. The following description is for the 80186/XL/EA
processors. The functionality is the same for other processors.

EINT0- Stimulate EINT0- line.

HOLD Stimulate HOLD line.

INT0 Stimulate INT0 line.

INTR Stimulate INTR line.

NMI Stimulate NMI line.

RESET Stimulate RESET line.

RESIN Stimulate RESIN line.

VINT0- Stimulate VINT0- line.

OFF No stimulation on any exception line.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 47
INT0

This is the simulation for vectored interrupts in cascaded mode. The simulation circuit sets INT0 to high until
2 interrupt acknowledge cycles are executed. The vector is supplied on the second IACK cycle. The pulse
width should be at minimum 2 CPU cycles.

E::w.x
Exception setup Trigger Puls Puls
 OFF OFF Single
ON RESIN Width
RESIN  INT0 10.000us
RESET HOLD PERiod
HOLD NMI 0.000
HLDA EINT0+
PULS EINT0- Vector
VINT0+ 33 (051.)
VINT0-

E::w.a.l ,t.0 def Analyzer list

run address cycle d.w sy
AP:000000401 fetch 00
AP:000000402 fetch 04
AP:000000403 fetch 00 Stimulation puls
AP:000000404 fetch 00
jmp 0000:0400
AP:000000405 fetch 00
AD:000000400 iack 00 1st IACK cycle
AD:000000400 iack 33 2nd IACK cycle, vector
AD:0000000CC rd-mem 00
AD:0000000CD rd-mem 05 vector table read
AD:0000000CE rd-mem 00
AD:0000000CF rd-mem 00
AD:000000FF2 wr-mem 02
AD:000000FF3 wr-mem F2 stack write
AD:000000FF0 wr-mem 00
AD:000000FF1 wr-mem 00
AD:000000FEE wr-mem 00
AD:000000FEF wr-mem 04
AP:000000500 fetch EA interrupt program
AP:000000501 fetch 00

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 48
 EINT0+ The pulse generator is directly connected to the interrupt pin. A low to high
pulse is generated. No interrupt vector is supplied by the simulation logic (Fully
nested mode).

EINT0- The pulse generator is directly connected to the interrupt pin. A high to low
pulse is generated. No interrupt vector is supplied by the simulation logic (Fully
nested mode).

VINT0+ The pulse generator is directly connected to the interrupt pin. A low to high
pulse is generated. All IACK cycles are supplied with the interrupt vector
defined by the eXception.Vector field.

VINT0- The pulse generator is directly connected to the interrupt pin. A high to low
pulse is generated. All IACK cycles are supplied with the interrupt vector
defined by the eXception.Vector field.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 49
Trap Trigger

Format: eXception.Trigger <vector>

<vector>: 0. … 255.

Every trap can be used as a separate trigger point. Trap trigger is detected by accessing the vector table!

HLDA Trigger on HLDA line.

HOLD Trigger on HOLD line.

Pulse Trigger on Pulse line.

RESET Trigger on RESET line.

RESIN Trigger on RESIN line.

ON Trigger on all exception lines.

OFF No trigger on any exception lines.

x.t 2 on ; activate NMI trigger

x.t 2 off ; deactivate NMI trigger

x.t 0x0--0x0ff off ; switch off all vector triggers

x.t 0x80--0x0ff ; set vectors 128 to 255 trigger active

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 50
Refresh Operation

The probe supports refresh operation in realtime emulation, but the refresh function is stopped when
emulation stops and starts again on realtime emulation. The CDRAM register value must be 40H (80H
C188) at minimum! When emulation is stopped, the REFresh system of the emulator has to generate valid
refresh cycles for the target system. Refresh doesn't work together with the Request access mode. Use
Denied or Nodelay access mode in this case.

FPU

Format: FPU.ON

Format: FPU.OFF

Format: FPU.RESet

Format: FPU.view

Format: FPU.Set <register> <value>

ON/OFF FPU display option is switched on or off

RESet FPU is initialized via 'finit' instruction

view Display window. The display is only updated, if the FPU is in idle state

FPU.Set Changes FPU registers

FPU commands

E::w.fpu
IM I IE _ C0 _ CW 037F ST(0) 1.2 3FFF.999999999999
DM D DE _ C1 _ SW 3000 ST(1) 3.4 4000.D99999999999
ZM Z ZE _ C2 _ TW 0FFF ST(2) NAN FFFF.C00000000000
OM O OE _ C3 _ TOP 6 ST(3) NAN FFFF.C00000000000
UM U UE _ B _ ST(4) NAN FFFF.C00000000000
PM P PE _ OPC 0106 ST(5) NAN FFFF.C00000000000
PC S SF _ IP 00000B00 ST(6) NAN FFFF.C00000000000
RC C ES _ OP 00010280 ST(7) NAN FFFF.C00000000000

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 51
I/O Connector for Coprocessor (8086/8087)

9 7 5 3 1
10 8 6 4 2

1 CLK 2 GND
3 RQ/GT0- 4 GND
5 RQ/GT1- 6 GND
7 INT 8 GND
9 BUSY 10 GND

Signals connected through 8087 on the 8086 emulator pod. For a description look under SYStem.Option
FPU.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 52
Memory Classes

Access Class Description

D Data

P Program

IO IO

ED Dualport Data

EP Dualport Program

EIO Dualport I/O

A Absolute

AD Absolute Data

AP Absolute Program

AC Absolute CPU

EA Absolute Dualport

EAD Absolute Dualport Data

EAP Absolute Dualport Program

EAC Absolute Dualport CPU

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 53
 C:, P: and D: This access types use all the same memory by default. Using
System.Option SPLIT it is possible to use separate emulation memory
for program and data accesses. If no segment address is used, the D:
prefix will refer to DS and the P: prefix to CS register

d.s P:0--0ffff 0 ; fill program memory with zero

d.s 0--0ffff 0 ; fill data memory with zero
d.s 100 0 ; set location ds:100 to 0

d.a 100 nop ; assemble to location cs:100

d.a 0--0fff nop ; fill program memory with nop
; instruction

d.i AD:1000 ; read memory mapped i/o from

; physically address 1000h

d.a 40:0 nop ; writes NOP to address 40:0 (400H)

IO:, AIO:, EIO:, The I/O addressing is always absolute. The IO-Range is 64K. Upper
EAIO: address bits are cut.

d.s IO:0x100 0x33 0x44 ; write 33H to port 100H and 44H to 101H

d.o 0x100 'A' ; sets port

d.i 0x100 ; read one byte from port 100H

d IO:0x100--0x103 ; displays 4 ports from 100H to 103H

d EIO:0x100--0x103 ; display state of output ports via

; dualport memory

A:, EA: Absolute addressing. The address parameter specifies the physically
address.

d.s A:0x12000 0x33 ; write to address 12000H in program/data

; memory

d EA:0x12000 ; displays absolute address 12000H from

; dualport memory

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 54
Segmentation

The MMU setup is normally done by loading a program. The section-table of the object-file (segments,
groups) is used to define the valid physical areas for the translation of physical addresses to logical
addresses. For more detailed information see command MMU.

Segment Description

CS: Current value of CS

DS: Current value of DS
SS: Current value of SS
ES: Current value of ES

<number>: Any hex segment number

<seg_name>: Any segment name for the sYmbol.SECtion table

Segment and offset are separated by a colon. If no segment is defined, the emulator will use the CS:
segment for program related commands and the DS: segment for data related commands. The D: access
class will force the usage of the DS: segment and the P: access class will force usage of the CS: segment.

d.s DS:0x100 ; if DS register is 10H, the physical

; address is DS*10H+addr = 200H

d.a 0x200 ; assemble to CS:200

d.s 0x100 0x0 ; set location DS:100

d SS:0x0f000 ; displays stack segment

d.l 0x0ffff:0x0 ; list code is segment 0ffff

d far_romdata:0x0 ; dump segment 'far_romdata'

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 55
Banked Target Systems

Banking as described in this chapter refers to address extension of 80x86 processors, not the internal
segmentation of the 80x86 family. In banked systems the upper address lines are supplied by the external
bank probe. Four additional lines offer 16 different memory banks. Accessing the different pages is done by
adding an extra bank component to all logical addresses and extending all physical memory addresses to
24 bit. The physical address bits A20 to A23 select the memory bank. Every command which makes a
memory access first calls a special bank driver subroutine to select the temporary memory bank. On
realtime emulation the bank number is traced on the upper four bits of the address bus. On a breakpoint the
upper four bit of the address bus are stored to the bank number of the PP register (Program Pointer).

Format: SYStem.BankFile <file>

This command loads the bank driver. The bank driver is a special subroutine to select the actual bank.
Loading a special bank driver gives a maximum of flexibility to the user. A bank address delivered by the
emulator may be used to set microcontroller ports or external MMUs in the target system. The bank file
consists of a code number defining the bank operation mode and a code area which consists of a subroutine
to set the correct bank state. The internal bank number is placed in register AL when calling the subroutine.
The reason for the call is placed in AH. It can be initialization (0), read (1), write (2), or start execution (3).
Writes to internal CPU ports may be executed directly, while ports in target systems must be accessed by a
special system call (see end of this chapter). The internal bank address is placed in accu A when calling the
subroutine. The PP (Program Pointer) register hold the logical 24-bit PC address. The translation between
logical bank and physical bank (also for the common areas and I/O space) is done by the MMU command.

Format: SYStem.Bank <option>

<option>: OFF
EXTernal

On the 80x86 banking can only be done in external mode. External banked systems use a register or output
pins of the CPU to generate the upper memory addresses. These lines must be feedback to the emulator
with the bank probe (lines 0 to 3). Unused inputs of the bank probe must be grounded (or jumpered to
ground pin).

; This example uses a common program/data area on a:0x0--0x0bffffh

;a banked area from a:0x0c0000--0x0fffff with 16 banks

map.res ; reset mapper

map.mirror ap:0--0bffff ap:100000 ; mirror for common area

map.mirror ap:0--0bffff ap:200000
...
map.mirror ap:0--0bffff
ap:0e00000
map.mirror ap:0--0bffff
ap:0f00000

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 56
 map.mirror aio:0--ffff aio:100000 ; mirror I/O area (not banked)
map.mirror aio:0--ffff aio:200000
...
map.mirror aio:0--ffff
aio:0e00000
map.mirror aio:0--ffff
aio:0f00000

map.ram ap:0c0000--0fffff ; map bank #0

map.ram ap:1c0000--1fffff ; map bank #1
...
map.intern

symbol.reset ; clear old symbols first

system.bankfile banksel.bnk ; load bank file
system.up

d.load.o bank0.omf 0:0:0 /mf

d.load.o bank1.omf 1:0:0 /mf /nc
d.load.o bank2.omf 2:0:0 /mf /nc
...
d.load.o bank14.omf 0e:0:0 /mf /nc
d.load.o bank15.omf 0f:0:0 /nc

This example selects the bank by writing the left shifted bank to io:204:

org 0:3effH ; pseudo org (use inline assembler)

db 0x2 ; select external mode

bank: ; AL is bank address, AH is reason

org 0:3f00H ; destination area in system memory

shl al,1
mov dx,204H ; set DX to io register
call 0d30H ; subroutine to write byte to i/o
; DX is address, AL is data
ret ; return

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 57
Memory and I/O Access Routines

The following routines are available in the emulation control monitor to access external memory or i/o:

Addr Function Address Data Result

0d00H ReadMemByte ES:SI - AL

0d04H ReadMemWord ES:SI - AX
0d10H WriteMemByte ES:DI AL -
0d14H WriteMemWord ES:DI AX -
0d20H ReadIOByte DX - AL
0d24H ReadIOWord DX - AX
0d30H WriteIOByte DX AL -
0d34H WriteIOWord DX AX -

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 58
Monitor Extensions

A monitor extension is a piece of code that’s extending the emulation control monitor. The emulation monitor
is responsible for starting and stopping the target program and accessing memory and registers when the
target program is stopped. This monitor is running in a hidden memory inside the ECU unit. Extensions must
be made available in a binary program. This program must be loaded before activating the emulation by the
following command:

Format: SYStem.MonFile <file>

The program can contain the following extensions:

Start Target This part is executed before the target program is started. It can enable timers
in the target or reset watchdogs.

Stop Target This part is executed after the emulation in the target has stopped. It can
disable timers or external watchdogs.

Read Memory User specific memory read. Allows access to special memories, e.g. serial
connected EEPROMs. The access is made by the USR: memory class.

Write Memory User specific memory write. Allows write access to special memories, e.g.
programming EEPROM or FLASH memories. The access is made by the USR:
memory access class.

For more details about the definition of the monitor extension and parameter passing see the example file
'./demo/i86/etc/monext.asm'.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 59
State Analyzer

When the bus size of the processor is changed, an existing analyzer recording, sampled with a different bus
size, will be displayed wrong.

Keywords for the Trigger Unit

General Keywords for the Trigger Unit

Input Event Meaning Analyzer Hardware

ECC8 HAC HA120 SA120
BYTE Byte transfer X X
PORT Input line from port analyzer X X
Wait0..Wait6 Waitstates 0..6 X X
WaitX Waitstates greater 6 X X
WORD Word transfer X X

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 60
8086/8088/V20/V30MAX Keywords for the Trigger Unit

Input Event Meaning Analyzer Hardware

ECC8 HAC HA120 SA120
Data Data access (MRD or MWR) X X X
FETCH Program fetch cycle X X X
IE Interrupt enable bit X X
INTA INTA line X X X
INTR Interrupt request X X
IO IO cycle (IORD or IOWR) X X X
IORD IO read access cycle X X X
IOWR IO write access cycle X X X
LOCK Lock signal X X
MRD Memory read access cycle X X X
MWR Memory write access cycle X X X
Read Read access (FETCH or INTA or IORD X X X
or MRD)
STACK Stack access X X
TEST Test line X X
Write Write access (IOWR or MWR) X X X

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 61
8086/8088/V20/V30MIN Keywords for the Trigger Unit

Input Event Meaning Analyzer Hardware

ECC8 HAC HA120 SA120
Data Data access (MRD or MWR) X X X
FETCH Program fetch cycle X X
IE Interrupt enable bit X X
INTR Interrupt request X X
IO IO cycle (IORD or IOWR) X X X
IORD IO read access cycle X X X
IOWR IO write access cycle X X X
MRD Memory read access cycle X X X
MWR Memory write access cycle X X X
Read Read access (IORD or MRD) X X X
STACK Stack access X X
TEST Test line X X
WR Write line X X
Write Write access (IOWR or MWR) X X X

80(C)186(XL)/80(C)188(XL)/EA/EB/EC/EM/ES/ER Keywords for the Trigger Unit

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 62
 Input Event Meaning Analyzer Hardware
ECC8 HAC HA120 SA120
Data Data access (MRD or MRDDMA or X X X
MWR or MWRDMA)
DMA DMA cycle (IORDDMA or IOWRDMA or X X X
MRDDMA or MWRDMA)
FETCH Program fetch cycle X X X
HALT Halt cycle X X X
IACK Interrupt acknowledge X X X
INT Interrupt request (INT0 or INT1 or INT2 X X
or INT3)
INT0..INT3 X X
IO IO cycle (IORD or IORDDMA or IOWR X X X
or IOWRDMA)
IORD IO read access cycle X X X
IORDDMA IO read access cycle by DMA X X X
IOWR IO write access cycle X X X
IOWRDMA IO write access cycle by DMA X X X
MRD Memory read access cycle X X X
MRDDMA Memory read access cycle by DMA X X X
MWR Memory write access cycle X X X
MWRDMA Memory write access cycle by DMA X X X
Read Read access (FETCH or IACK or IORD X X X
or IORDDMA or MRD or MRDDMA)
REFRESH X X
TEST Test line X X
Write Write access (IOWR or IOWRDMA or X X X
MWR or MWRDMA)

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 63
V40/V50 Keywords for the Trigger Unit

Input Event Meaning Analyzer Hardware

ECC8 HAC HA120 SA120
Data Data access (MRD or MRDDMA or X X X
MWR or MWRDMA)
DMA DMA cycle (IORDDMA or IOWRDMA or X X X
MRDDMA or MWRDMA)
FETCH Program fetch cycle X X X
HALT Halt cycle X X X
IACK Interrupt acknowledge X X X
INT Interrupt request (INTP1 or INTP2 or X X
INTP3)
INTAK INTAK line X X
INTP1..INTP3 X X
IO IO cycle (IORD or IORDDMA or IOWR X X X
or IOWRDMA)
IORD IO read access cycle X X X
IORDDMA IO read access cycle by DMA X X X
IOWR IO write access cycle X X X
IOWRDMA IO write access cycle by DMA X X X
MRD Memory read access cycle X X X
MRDDMA Memory read access cycle by DMA X X X
MWR Memory write access cycle X X X
MWRDMA Memory write access cycle by DMA X X X
POLL Poll line X X
Read Read access (FETCH or IACK or IORD X X X
or IORDDMA or MRD or MRDDMA)
REFRESH X X
Write Write access (IOWR or IOWRDMA or X X X
MWR or MWRDMA)

For not CPU-specific keywords, see non-declarable input variables in “ICE/FIRE Analyzer Trigger Unit
Programming Guide” (analyzer_prog.pdf).

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 64
Keywords for the Display

General Keywords

AAddress Absolute (physical) address

Wait Number of inserted wait cycles, for more than 6 a 'X' appears.

8086/8088/V20/V30MAX Keywords

RESET Reset cycle

QS0, QS1 Queue state lines
NMI NMI line
RQGT0, RQGT1 CPU lines
IE Interrupt enable bit
INTR Interrupt line
LOCK LOCK line
TEST TEST line

8086/8088/V20/V30MIN Keywords

INTA INTA line

HOLD, HLDA CPU lines
IE Interrupt enable bit
INTR Interrupt line
WR WR line
TEST TEST line
DMA DMA access

80(C)186(XL)/80(C)188(XL)/EA/EB/EC/EM/ES/ER/ED/CC Keywords

RESIN RESIN line

RESET Reset cycle
TMRIN0, TMRIN1 Timer inputs
NMI NMI line

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 65
 HOLD, HLDA CPU lines
INT0 .. INT3 Interrupt lines
TEST TEST line

V40/V50MIN Keywords

RESIN RESIN line

RESET Reset cycle
TCLK,TCTL2,TOUT2 Timer lines
NMI NMI line
HOLD, HLDA CPU lines
INTP1 .. INTP3 Interrupt lines
POLL POLL line
INTAK Interrupt line

Dequeueing

The disassembled lines in the analyzer are displayed prior to the resulting data cycles. This dequeueing fails
for commands which have not a constant number of data cycles. Long data sequences during REP SCAS
or REP MOVS can cause missing mnemonics in the disassembly.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 66
Port Analyzer

Keywords for the Port Analyzer (8086/8088/V20/V30)

INTA INTA line (MIN)

ALE ALE (MIN)
HOLD HOLD (MIN)
HLDA HLDA (MIN)

RESET RESET output (MAX)

INTR Interrupt line (MAX)
NMI NMI (MAX)
QS0, QS1 Queue state (MAX)
RQGT0, RQGT1 RQGTx lines (MAX)

DEN DEN (MIN)

DTR DTR (MIN)
IOM IOM (MIN)
S0 .. S2 State lines (MAX)
RD
WR WR (MIN)
READY READY
BHE BHE
LOCK LOCK (MAX)

CRQGT0, CRQGT1 CRQGTx (MAX)

CINT CINT(MAX)
CBUSY CBUSY (MAX)
TEST TEST (MAX)

A0 .. A7 Free Trace Channels A

B0 .. B7 Free Trace Channels B
C0 .. C7 Free Trace Channels C

BNK0 .. BNK7 Bank Probe Channels

©1989-2019 Lauterbach GmbH
ICE Emulator for the 80186 and 80196 67
Keywords for the Port Analyzer (80(C)186(XL)/80(C)188(XL)/EA)

RESIN RES input

RESET RESET output
TMRIN0 Timer In 0
TMRIN1 Timer In 1
NMI NMI
ALE ALE
HOLD HOLD
HLDA HLDA
DRQ0 DMA Request 0
DRQ1 DMA Request 1
TMROUT0 Timer Out 0
TMROUT1 Timer Out 1
LCS Lower Chip Select
UCS Upper Chip Select
PCS0 .. 6 Peripheral Chip Selects
MCS0 .. 3 Middle Chip Selects
INT0 .. INT3 Interrupt 0 .. 3

A0 .. A7 Free Trace Channels A

B0 .. B7 Free Trace Channels B
C0 .. C7 Free Trace Channels C

BNK0 .. BNK7 Bank Probe Channels

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 68
Keywords for the Port Analyzer (80186EB/80188EB)

RESIN RES input

RESET RESET output
TMRIN0 Timer In 0
TMRIN1 Timer In 1
NMI NMI
ALE ALE
HOLD HOLD
HLDA HLDA
RXD0, TXD0, CTS0 Serial interface
10 .. 17 Port 1
20 .. 27 Port 2
LCS Lower Chip Select
UCS Upper Chip Select
TMROUT0 Timer Out 0
TMROUT1 Timer Out 1
TEST TEST line
NCS NCS line
ERROR ERROR line
PEREQ PEREQ line
INT0 .. INT4 Interrupt 0 .. 3

A0 .. A7 Free Trace Channels A

B0 .. B3 Free Trace Channels B

BNK0 .. BNK7 Bank Probe Channels

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 69
Keywords for the Port Analyzer (80186EC/80188EC)

RESIN RES input

RESET RESET output
TMRIN0 Timer In 0
TMRIN1 Timer In 1
NMI NMI
ALE ALE
HOLD HOLD
HLDA HLDA
DRQ0 .. DRQ3 DMA request lines
MCS0,MCS1,MCS3 Chip selects
10 .. 17 Port 1
20 .. 27 Port 2
30 .. 35 Port 3
INTA Interrupt line
WDTOUT WDTOUT line
LCS Lower Chip Select
UCS Upper Chip Select
TMROUT0 Timer Out 0
TMROUT1 Timer Out 1
TEST TEST line
INT0 .. INT7 Interrupt 0 .. 7

BNK0 .. BNK7 Bank Probe Channels

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 70
Keywords for the Port Analyzer (18xEM/18xES/18xER/186ED)

18xEM/ER 18xES/ED

RESET RES- input RES- input

TMRIN0 TMRIN0/PIO11 TMRIN0/PIO11
TMRIN1 TMRIN1/PIO0 TMRIN1/PIO0
NMI NMI NMI
ALE ALE ALE
HOLD HOLD HOLD
HLDA HLDA HLDA
INT0 INT0 INT0
IRQ INT3/INTA1/IRQ INT3/INTA1/IRQ
SELECT INT1/SELECT INT1/SELECT
LCS Lower Chip Select Lower Chip Select
UCS Upper Chip Select Upper Chip Select

0 TMRIN1/PIO0 TMRIN1/PIO0
1 TMROUT1/PIO1 TMROUT1/PIO1
2 PCS6/A2/PIO2 PCS6/A2/PIO2
3 PCS5/A1/PIO3 PCS5/A1/PIO3
4 DTR/PIO4 DTR/PIO4
5 DEN/PIO5 DEN/DS/PIO5
6 SRDY/PIO6 SRDY/PIO6
7 A17/PIO7 A17/PIO7

8 A18/PIO8 A18/PIO8
9 A19/PIO9 A19/PIO9
10 TMROUT0/PIO10 TMROUT0/PIO10
11 TMRIN0/PIO11 TMRIN0/PIO11
12 DRQ0/PIO12 DRQ0/INT5/PIO12
13 DRQ1/PIO13 DRQ1/INT6/PIO13
14 MCS0/PIO14 MCS0/PIO14
15 MCS1/PIO15 MCS1/PIO15

16 PCS0/PIO16 PCS0/PIO16

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 71
 17 PCS1/PIO17 PCS1/PIO17
18 PCS2/PIO18 PCS2/CTS1/ENRX1/PIO18
19 PCS3/PIO19 PCS3/RTS1/RTR1/PIO19
20 SCLK/PIO20 RTS0/RTR0/PIO20
21 SDATA/PIO21 CTS0/ENRX0/PIO21
22 SDEN0/PIO22 TXD0/PIO22
23 SDEN1/PIO23 RXD0/PIO23

24 MCS2/PIO24 MCS2/PIO24
25 MCS3/RFSH/PIO25 MCS3/RFSH/PIO25
26 UZI/PLLBYPS/PIO26 UZI/PLLBYPS/PIO26
27 TXD/PIO27 TXD1/PIO27
28 RXD/PIO28 RXD1/PIO28
29 S6/CLKDIV2/PIO29 S6/LOCK/CLKDIV2/PIO29
30 INT4/PIO30 INT4/PIO30
31 INT2/INTA0/PIO31 INT2/INTA0/PWD/PIO31

A0 .. A7 Free Trace Channels

BNK0 .. BNK7 Bank Probe Channels

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 72
Keywords for the Port Analyzer (V40/V50)

RESIN RES input

TCLK,TCTL2,TOUT2 Timer lines
NMI NMI
ALE ALE
HOLD HOLD
HLDA HLDA
INTAK INTAK line
TC TC line
POLL POLL line
REFRQ REFRQ line
DRQ0 .. DRQ3 DMA Request 0 .. 3
DACK0 .. DACK3 DMA Acknowledge 0 .. 3
INTP1 .. INTP7 Interrupt 1 .. 7

A0 .. A7 Free Trace Channels A

B0 .. B7 Free Trace Channels B
C0 .. C7 Free Trace Channels C

BNK0 .. BNK7 Bank Probe Channels

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 73
Input Connector for free Channels (8086/8088/80186/80188)

25 23 21 19 17 15 13 11 9 7 5 3 1
26 24 22 20 18 16 14 12 10 8 6 4 2

1 A0 17 C0
2 A1 18 C1
3 A2 19 C2
4 A3 20 C3
5 A4 21 C4
6 A5 22 C5
7 A6 23 C6
8 A7 24 C7

9 B0 25 GND
10 B1 26 GND
11 B2
12 B3
13 B4
14 B5
15 B6
16 B7

Input Connector for free Channels (80186EB/80188EB)

15 13 11 9 7 5 3 1
16 14 12 10 8 6 4 2

1 A0 9 B0
2 A1 10 B1
3 A2 11 B2
4 A3 12 B3
5 A4 13 GND
6 A5 14 GND
7 A6 15 GND
8 A7 16 GND

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 74
Input Connector for free Channels (18xEM/18xES/18xER/186ED/CC)

9 7 5 3 1
10 8 6 4 2

1 A0 9 GND
2 A1 10 GND
3 A2
4 A3
5 A4
6 A5
7 A6
8 A7

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 75
Compilers

Language Compiler Company Option Comment

ASM AXLS HP Source level
debugging
C BORLANDC Borland Software EOMF-86 with Paradigm
Corporation LOCATE
C ORGANON CAD-UL EOMF-86 Banking support
ElectronicServices
GmbH
C IC86 Intel Corporation OMF-86
C MCC86 Mentor Graphics EOMF-86 incl. Microtec ext.
Corporation
C MSC/MSVC-16BIT Microsoft Corporation EOMF-86 with Paradigm
LOCATE
C MSC/MSVC Microsoft Corporation EXE/TD with Paradigm
LOCATE
C ICC86 TASKING OMF-86
C ICC86 TASKING IEEE
C++ BORLANDC Borland Software EXE/TD
Corporation
C++ MSVC-16BIT Microsoft Corporation EXE/CV
MODULA LOGITECH-M2 Terra Datentechnik MAP/REF
PASCAL TEK-PASCAL Tektronix TEK
PLM PL/M86 Intel Corporation OMF-86 reads src or list file

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 76
3rd-Party Tool Integrations

CPU Tool Company Host

WINDOWS CE PLATF. - Windows
BUILDER
CODE::BLOCKS - -
C++TEST - Windows
ADENEO -
X-TOOLS / X32 blue river software GmbH Windows
CODEWRIGHT Borland Software Windows
Corporation
CODE CONFIDENCE Code Confidence Ltd Windows
TOOLS
CODE CONFIDENCE Code Confidence Ltd Linux
TOOLS
EASYCODE EASYCODE GmbH Windows
ECLIPSE Eclipse Foundation, Inc Windows
RHAPSODY IN MICROC IBM Deutschland GmbH Windows
RHAPSODY IN C++ IBM Deutschland GmbH Windows
CHRONVIEW Inchron GmbH Windows
LDRA TOOL SUITE LDRA Technology, Inc. Windows
UML DEBUGGER LieberLieber Software Windows
GmbH
SIMULINK The MathWorks Inc. Windows
ATTOL TOOLS MicroMax Inc. Windows
VISUAL BASIC Microsoft Corporation Windows
INTERFACE
LABVIEW NATIONAL Windows
INSTRUMENTS
Corporation
TPT PikeTec GmbH Windows
CANTATA QA Systems Ltd Windows
RAPITIME Rapita Systems Ltd. Windows
TESSY Razorcat Development Windows
GmbH
DA-C RistanCASE Windows
TRACEANALYZER Symtavision GmbH Windows
ECU-TEST TraceTronic GmbH Windows
UNDODB Undo Software Linux
TA INSPECTOR Vector Windows
VECTORCAST UNIT Vector Software Windows
TESTING
VECTORCAST CODE Vector Software Windows
COVERAGE

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 77
 ©1989-2019 Lauterbach GmbH
ICE Emulator for the 80186 and 80196 78
Realtime Operation Systems

Company Product Comment

Oracle Corporation ChorusOS
Mentor Graphics Nucleus PLUS
Corporation
Wind River Systems pSOS+ 2.1 to 2.5, 3.0
Quadros Systems Inc. RTXC 3.2
Wind River Systems VxWorks 5.x and 6.x

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 79
Emulation Frequency

The emulation probe is designed for running with CPU's up to 40 MHz. However the max. speed is limited by
the CPU chip used in the emulator. TRACE32 modules are delivered with the fastest CPU available. The
following values of emulation frequencies refer to the 'standalone' mode (memory is mapped internal).

The maximum operation frequency of TRACE32-ICE depends on:

• The max. frequency of the CPU

• The access time of the overlay memory (15 ns or 35 ns)

• The mapper mode (Slow or Fast)

• The number of waitstates

(WO = 0 waitstates W1 = 1 waitstate)

Module CPU F-W0- F-W0- S-W0- S-W0- S-W1- S-W1- DRAM

15 35 15 35 15 35
LA-6673 V40 16.0 13.8 14.3 12.5 16.0+ 16.0+ 16.0

NOTE: The cycle speed of the SA120 unit is limited to 150ns.

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 80
Emulation Modules

Module Overview

LA-6670 LA-6673 V40 PLCC68 0.0..5.5V

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 81
Order Information

Order No. Code Text

LA-6670 ICE-186 ICE-186 Base Module

LA-6671 M-80C186XL Module 80C186XL
LA-7070 M-80C188XL Module 80C188XL
LA-7071 M-80C186EA Module 80C186EA
LA-7072 M-80C188EA Module 80C188EA
LA-6672 M-80C186EB Module 80C186EB
LA-6697 M-80C186EB-3.3V Module 80C186EB 3.3V
LA-7075 M-80C188EB Module 80C188EB
LA-6698 M-80C188EB-3.3V Module 80C188EB 3.3V
LA-6678 M-80C186EC Module 80C186EC
LA-7076 M-80C188EC Module 80C188EC
LA-6696 M-80186EM Module 186EM
LA-7090 M-80188EM Module 188EM
LA-7091 M-80186ES Module 186ES
LA-7092 M-80188ES Module 188ES
LA-7093 M-80186ER Module 186ER
LA-7094 M-80188ER Module 188ER
LA-7099 M-80186ED Module 186ED
LA-7077 M-80186CC/CU/CH Module 186CC/CU/CH
ET-1200 ET-80186PLCC-C PLCC to PLCC Clip Over Adapter for 80C186
ET-1202 ET-80186/88PLCC-SQFP PLCC to SQFP80 Surface Mountable Adapter
LA-6673 M-V40 Module V40
LA-7095 M-V50 Module V50
LA-6677 M-8086 Module 8086
LA-7096 M-8088 Module 8088
LA-7097 M-V20 Module V20
LA-7989 M-V20/3.3V Module V20 3.3 Volt
LA-7098 M-V30 Module V30
LA-6695 M-196EN Module 196EN
LA-6674 M-196KB Module 196KB
LA-7080 M-196KD Module 196KD
LA-7081 M-196KC Module 196KC
LA-7082 M-194 Module 194
LA-7083 M-198 Module 198
LA-7084 M-196KDS Module 196KDS

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 82
Operating Voltage

This list contains information on probes available for other voltage ranges. Probes not noted here supply an
operation voltage range of 4.5 … 5.5 V.

No other voltage ranges available !

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 83
Physical Dimensions

Dimension

LA-7077 M-80186CC/CU/CH

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 84
 Dimension

LA-6671 M-80C186XL
LA-7070 M-80C188XL
LA-7071 M-80C186EA
LA-7072 M-80C188EA

cable (350)

66
80186/80188/XL/EA
37

13

9
24

92
105

SIDE VIEW

PLCC 68

74
1

22

14

TOP VIEW (all dimensions in mm)

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 85
 Dimension

LA-6672 M-80C186EB
LA-6697 M-80C186EB-3.3V
LA-7075 M-80C188EB
LA-6698 M-80C188EB-3.3V

cable (350)

74
80186EB/80188EB
37

13

9
24

99
112

SIDE VIEW

PLCC 84

74
1

19

16

TOP VIEW (all dimensions in mm)

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 86
 Dimension

LA-6678 M-80C186EC
LA-7076 M-80C188EC

cable (350)

79
80186EC/80188EC
37

13

105
117

SIDE VIEW

Female Connectors

for
77
ET-adapter

12

10

TOP VIEW (all dimensions in mm)

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 87
 Dimension

LA-6696 M-80186EM
LA-7090 M-80188EM
LA-7091 M-80186ES
LA-7092 M-80188ES
LA-7093 M-80186ER
LA-7094 M-80188ER
LA-7099 M-80186ED

cable (400)

78

37

13

104
117

SIDE VIEW

A
1
B

A B A B
78

1
B
14 A
8
19
22

TOP VIEW (all dimensions in mm)

Adaption A: 100pole TQFP (square)=QF49

Adaption B: 100pole PQFP (rectangular)=QF06

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 88
 Dimension

LA-6673 M-V40
LA-7095 M-V50

cable (350)

74
V40/V50
37

13

100
112

SIDE VIEW

PLCC 68

74
1

22

14

TOP VIEW (all dimensions in mm)

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 89
 Dimension

LA-6677 M-8086
LA-7096 M-8088
LA-7097 M-V20
LA-7098 M-V30

cable (350)

74
8086/88/V20/V30
37

13

10 8087

99
113

SIDE VIEW

target 8087

74

12

14

TOP VIEW (all dimensions in mm)

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 90
 Dimension

LA-6695 M-196EN

cable (400)

86

37

13

111
125

SIDE VIEW

78

13

13
TOP VIEW (all dimensions in mm)

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 91
 Dimension

LA-6674 M-196KB
LA-7080 M-196KD
LA-7081 M-196KC
LA-7082 M-194
LA-7083 M-198

cable (350)

65

37

13

9
26

92
105

SIDE VIEW

PLCC 68

74

1
36

PLCC 52
8

13

TOP VIEW (all dimensions in mm)

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 92
Adapter

No adapters necessary !

©1989-2019 Lauterbach GmbH

ICE Emulator for the 80186 and 80196 93