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EA
Lockdown Period
Open Practice Test Series
(Also useful for Other Exams)
E

CS: COMPUTER SCIENCE & IT

AD

TEST No. - 10 | DIGITAL LOGIC

Read the following instructions carefully

1. This question paper contains 33 MCQ’s & NAQ’s. Bifurcation of the questions are given
M

below:

17 to 28

29 to 33

2. Choose the closest numerical answer among the choices given.

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Multiple Choice Questions : Q.1 to Q.10 carry 1 mark each

Q.1 Which one of the following is the correct sequence of numbers represented in the series (2)3, (3)4,
(14)5, (15)6 ?
(a) 2, 5, 10, 12 (b) 2, 3, 9, 11
(c) 3, 7, 10, 14 (d) 3, 8, 13, 17

1. (b)
Converting into decimal,
(2)3 = 2 × 3° = 2
(3)4 = 3 × 4° = 3
(14)5 = 1 × 51 +4 × 5° = 9
(15)6 = 1 × 61 + 5 × 6° = 11

SY
Q.2 Let F (A,B) = A + B , then the value of f(f (x + y, y), z) = ?
(a) y + z (b) y + z
(c) y + z (d) y + z

2. (c)
A = x+y
B = y
EA
f( x + y, y) = (x + y ) + y = x .y + y

So, f ( y ,z ) = y + z = y + z

Q.3 In the circuit shown below, the propagation delay of each NOT gate is 2 nsec (2 nano sec), then
E

the time period of generated square wave is –

Output
AD

(a) 10 nsec (b) 14 nsec

(c) 18 nsec (d) 20 nsec

3. (d)
N = 5,
M

tpd = 2 nsec
T = 2 N tpd
⇒ T = 2 × 5 × 2 × 10–9
= 20 nsec

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Q.4 The minimal logic expression corresponding to the K-map shown below is
YZ
W X 00 01 11 10
00 1
01 1 1 1
11 1 1 1
10 1

(a) X Z (b) WXY + WYZ + WY Z + WXY

(c) WXY + WYZ + WY Z + W XY (d) XZ + WYZ + WXY + W XY + WYZ

4. (b)
YZ
W X 00 01 11 10

SY
00 1
01 1 1 1
11 1 1 1
10 1

Z = WXY + WXY + WYZ + WYZ

EA
Q.5 The output of the given 4 : 1 MUX will be

C I0
1
I1 4:1
Y
0 MUX
I2

I3 S S0
1
E

A B

(a) Σm (1,2, 3, 6) (b) Σm (2, 4, 5, 7)

AD

(c) Σm (1,3, 4, 7) (d) Σm (1,2, 6, 7)

5. (a)
Y = S0S1I 0 + S0S1I1 + S0S1I2 + S0S1I 3
= ABC + AB ⋅ 1 + AB ⋅ 0 + AB ⋅ C
= ABC + AB ⋅ (C + C ) + ABC
M

= ABC + ABC + ABC + ABC

≈ 001, 011, 010, 110
f (A,B,C) = Σm (1,2, 3, 6)

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Q.6 How many numbers of 8 : 1 MUX is required to implement 256 : 1 MUX ?

(a) 25 (b) 31
(c) 37 (d) 40

6. (c)
256 32
Number of MUX = = 32 ⇒ = 4
8 8
4
⇒ = 1
8
Total = 32 + 4 + 1 = 37

Q.7 If M represents total number of states and n represents total no. of FFs, then for a nonbinary
counter, which relation holds true ?

SY
(a) M ≤ 2n (b) M = 2n
(c) M > 2n + 1 (d) M = 2 2n

7. (a)
M = total number of states
n = total number of FF’s
M
M
=
≤
EA
2n ; Binary counter
2n ; Non-Binary counter

Q.8 A circuit is designed with 2 – J-K FF’s. If the output θA θB = 10 at starting, what will be the output
(θA θB) after 13th clock pulse.

JA QA JB QB
E

KA QA KB QB
AD

CLOCK

(a) 0 0 (b) 1 0
(c) 1 1 (d) 0 1

8. (c)
N = 2, K = 13
M

K%3=1

FFA FFB
Clock QA QB
JA = QB, KA = 0 JB = QA, KB = QA
1 0 0 0 1 1
1 1 1 1 0 1 1
2 1 0

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Q.9 A 4-bit Down counter is used to control the output of the multiplexer as shown in figure. The
counter is initially at (1111)2, then the output of the multiplexer will follow the sequence –
I7 I6 I5 I4 I3 I2 I1 I0

A3 7 6 5 4 3 2 1 0
S2
4-bit A2
S1 8:1 Output
UP counter A MUX (Y)
1
S0
CLK A0
Enable

(a) I7, 0, I6, 0, I5, 0 ... (b) I7, 0, 0, I6, 0, 0, I5 ...

(c) I7, I6, I5, I4, I3 ... (d) I7, I6, 0, 0, I5, I4, 0, 0 ...

SY
9. (d)
Counter output = S2 S1 E S0
A3 A2 A1 A0
st
1 clock 1 1 1 1 – 15 I7
nd
2 1 1 1 0 – 14 I6
rd
3 1 1 0 1 – 13 0
th
4
5
6
th

th
EA 1
1
1
1
0
0
0
1
1
0
1
0
– 12
– 11
– 10
0
I5
I4

For 1st and 2nd clock pulses, enable is 1

S2 S1 S0
st
1 clock pulse – 1 1 1 → 17
2nd clock pulse – 1 1 0 → 16
For 3rd and 4th clock pulse, enable is 0,
E

So, Y is 0

Q.10 Which of the following statement is Incorrect for the range of n bits binary numbers?
AD

(a) Range of unsigned numbers is 0 to 2n – 1.

(b) Range of signed numbers is –2n – 1 + 1 to 2n – 1 – 1
(c) Range of signed 1’s complement numbers is –2n – 1 + 1 to 2n – 1
(d) Range of signed 2’s complement numbers is –2n – 1 to 2n – 1 – 1

10. (c)
Range of signed 1’s complement number is –2n – 1 + 1 to 2n – 1 – 1.
M

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Numerical Data Type Questions : Q. 11 to Q. 16 carry 1 mark each

Q.11 Consider the following boolean expression:

F = ⎡⎣ x + z {y + (z + xy )}⎤⎦ ⎡⎣{ x + z ( x + y )}⎤⎦ = 1

If x = 1 in above expression then the value of z is _______.

11. (1)
Given boolean expression
⎡⎣ x + z {y + (z + xy )}⎤⎦ ⎡⎣{ x + z ( x + y )}⎤⎦ = 1

put x = 1 and x = 0

SY
⎡⎣1+ z {y + (z + y )}⎤⎦ [ 0 + z(1+ y )] = 1
 
1 z

So minimum expression is [1][z ([1]] = 1

Then to satisfy equation z must be 1.

Q.12 The number of minimum terms of the following function F which is implemented by MUX _______.
EA 0 I0

1 I1
F
C I2

1 I3 S S0
1

A B
E

12. (5)
F = AB ⋅ 0 + AB ⋅ 1 + ABC + AB ⋅ 1
AD

= AB+ ABC+ AB
2, 3 4 6,7

= Σm (2, 3, 4, 6, 7)

Q.13 The lowest frequency in kHz, if a 6 MHz clock frequency is applied to a cascaded counter of
modulus-2 counter and modulus-3 counter are ________.
M

13. (1000)
Resulting mode in cascade counter
= M×N=2×3=6
6 × 106
Lowest output frequency = = 1000 kHz
6

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Q.14 Total number of AND gates present inside a 6-bit carry look ahead generator circuit is _______

14. (21)

n(n + 1)
Total AND gates for a n-bit carry look ahead generator is 1 + 2 + 3 + 4 + ... + n =
2
Here n = 6
6×7
∴ Total AND gates = = 21
2

Q.15 The base of the number system for the addition 13 + 24 = 42 to be true will be _______.

15. (5)

SY
Let base be x, then
(13) x + (24) x = (42) x
(1x1 + 3x0) + (2x1 + 4x0) = 4x1 + 2x0
3x1 + 7x0 = 4x1 + 2x0
x = 5 EA
Q.16 A Boolean function of two variables X and Y is defined as follows:
f (0, 0) = f (0, 1) = f (1, 1) = 1 and f (1, 0) = 0
Assume complement of X and Y are not available, then the minimum cost solution for implement
f using 2 input Nand gate and 2 input OR gate is (Total cost) _______. (Let each 2 input OR or
Nand gate have 2 unit cost).

16. (4)
The Boolean function of two variables X and Y are
E

f (0, 0) = f (0, 1) = f (1, 1) = 1 and f (1, 0) = 0

Truth table is:
AD

X Y F
0 0 1
0 1 1
1 0 0
1 1 1

Function f boolean expression is = XY + XY + XY

M

= X + XY
= X +Y
Since function implement using 2 input Nand gate or OR gate
X
X+Y
Y 2 unit
So total cost = (2 + 2) unit = 4 unit

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Multiple Choice Questions : Q.17 to Q.28 carry 2 marks each

Q.17 Which of the following circuit connection represents J – K Flip-Flop ?

(a) (b)
S Qn S Q
J J
CLK
CLK
K K
R Qn R Qn

(c) (d)
S Q

SY
S Q
J
J

K CLK CLK
R Qn K
R Qn

17. (c)
EA
The characteristics tabel with J, K, Q n , Qn + 1 and the excitation table for S and R is shown below
–

J K Qn Qn + 1 S R
0 0 0 0 0 ×
0 0 1 1 × 0
0 1 0 0 0 ×
E

0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 1 × 0
AD

1 1 0 1 1 0
1 1 1 0 0 1

The K-map for S and R is shown as –

For S,
S (J, K, Qn) = Σm(4, 6) + d(1, 5) = JQn
M

KQn
J 00 01 11 10
0

1 1 1

S = JQn
For R,
R (J, K, Qn) = Σm(3, 7) + d(0, 2) = KQn
KQn
J 00 01 11 10
0 1

1 1

R = KQn
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Q.18 Consider the Boolean function f(A,B,C,D) = Σm (0, 1, 2, 5, 7, 8, 10, 12, 14, 15). Function is having
how many number of essential prime implicants?
(a) 2 (b) 3
(c) 4 (d) 5

18. (a)

I V
CD IV
III
AB

1 1 1

1 1
VI

SY
1 1 1 VII

I EPI 1 1
II EPI
EA II

III VI

IV VII NEPI’s
V

EPI = Essential Prime Implicant [which cover a minterm not covered by any other prime implicants]
NEPI = Non Essential Prime Implicant. Number of EPI’s = 2, number of NEPI’s = 5.
E

Q.19 Decimal equivalent of (1000)2 = – 2n

Decimal equivalent of (10000)2 = –2m
So, (n + m)2 would be
AD

(a) 1 1 1 (b) 0 1 1
(c) 0 0 1 (d) 1 0 1

19. (a)
Decimal equivalent of (1000)2 = –23
⇒ n = 3
Decimal equivalent of (10000)2 = –24
M

⇒ m = 4
So, (n + m)2 = (3 + 4)2 = (7)2 = 111

Q.20 The Boolean function can be expressed in canonical SOP and POS forms. So, for Y = AB + BC , the
SOP and POS forms will be –
(a) Y = Σ (0, 2, 4, 6); Y = π (1, 3, 7) (b) Y = Σ (1, 2, 5, 7); Y = π (0, 3, 4, 6)
(c) Y = Σ (2, 4, 5, 6); Y = π (0, 1, 3, 7) (d) Y = Σ (1, 2, 4, 5); Y = π (0, 3, 6)

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20. (c)
Plotting the K-map for Y = AB + BC

BC BC BC BC
A 0 1 3
12

A 14 1 5 7 1 6

So, Σm (2, 4, 5, 6) = SOP

Σπ (0, 1, 3, 7) = POS

Q.21 A half adder is implement with XOR and AND gates. A full adder is implemented with two half
adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate.
The propagation delay of an AND/OR gate is 1.2 μsec. A 4-bit ripple carry binary adder is

SY
implemented by using full adders. The total propagation delay of this 4-bit binary adder is
(a) 19 μsec (b) 19.2 μsec
(c) 12 μsec (d) 38.4 μsec

21. (c)
For one full Adder : EA HA1 HA2
A 0 sec 2.4 μs
External 2.4 4.8 μs
input μs 2.4
B 0 sec μs s

Cin 0 sec 0 sec

3.6 μs
2.4 μs 1.2 4.8 μs
μs 1.2
μs c
E
1.2
μs
1.2 μs

The propagation delay of AND / OR gate tpd = 1.2 μ sec.

AD

The propagation delay of EX-OR gate 2tpd = 2.4 μ sec.

• Binary Adder external inputs are available to all HA1’s simultaneously.
• First HA1 output of all full adders are available simultaneously with delay of 2.4 μsec (i.e.,
2tpd).
• Carry generate from previous Full adder is passing only through HA2 of next full adder.
• The delay of LSB full adder = 4tpd.
M

• The 4 bit ripple carry binary delay:

A3 B3 A2 B2 A1 B1 A0 B0

1-bit FA 1-bit FA 1-bit FA 1-bit FA

C4 C3 C2 C1 C0

S3 S2 S1 S0

= 4tpd + 2tpd + 2tpd + 2tpd = 10tpd

= 10 × 1.2 μsec = 12 μsec

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Q.22 Consider the following synchronous counter made up of JK, D, T Flip-Flops.

J Q2 D Q1 T Q0

I K Q2 Q1 Q0

CLK
The modulus value of the counter is
(a) 5 (b) 8
(c) 7 (d) 4

22. (a)

SY
Present state FF2 FF1 FF0
Clock
Q2 Q1 Q0 J2 = Q0, K2 = 1 D1 = Q2 T0 = Q1
0 0 0 1 1 0 0
1 1 0 0 1 1 1 0
2 0 1 0 1 1 0 1
3 1 EA0 1 0 1 1 0
4 0 1 1 0 1 0 1
5 0 0 0

100
000 010

011 101
E

The number of used states = 5

∴ modulus value = 5
AD
M

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Q.23 What will be the output of multiplexer shown below –

I0 A I0
1
I1 X1 0 I1
4×1 4×1 Y
I2 MUX I2 MUX
0
I3 0 I3
S1 S0 S1 S0

A B D 0

(a) A ⊕ D (b) A  D  B
(c) A + D + B (d) A . D

23. (a)

SY
For 1st 4 × 1 MUX –
X1 = AB ⋅ 1B + AB ⋅ 1 + AB ⋅ 0 + AB ⋅ 0

⇒ = AB + AB = A(B + B ) = A
For 2nd 4 × 1 MUX –
EA
Y = D 0 ⋅ A + D ⋅ 0 ⋅ 0 + D0 ⋅ X1 + D ⋅ 0 ⋅ 0

= D ⋅ 1⋅ A + D ⋅ 1⋅ A = A ⊕ D

Q.24 The circuit shown below is used to implement the function z = f(A, B) = A + B . The values of P and
Q are
Q
E
P
A Z
AD

(a) P = A, Q = B (b) P = B, Q = A
(c) P = B, Q = O (d) P = O, Q = B

24. (d)
Z = (P + A)(Q + A)
M

Z = PQ + AQ + AP
If Z = A+B
Z = A + B = AB
Q = B, P =O

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Q.25 The initial content of serial IN parallel OUT, right shift, shift register shown below is 0011.
After how many clock pulses, the content of register will return to its initial value.
Clock
0 0 1 1
Serial In
Q3 Q0

I0

1 I1
4×1
I2 MUX Y
0
I3 S S
1 0

SY
(a) 7 (b) 8
(c) 11 (d) 13

25. (b)
S1 S0 MUX inputs
Clock S.I = Y Q3 Q2 Q1 Q0

1
EA 0
0
0
0
0
1
0
1
1
Initial
state

2 0 0 0 0 0
3 1 1 0 0 0
4 1 1 1 0 0
5 1 1 1 1 0
6 1 1 1 1 1
7 0 0 1 1 1
E

8 0 0 0 1 1

After 8 clock pulse.

AD

Q.26 Match List-I with List-II and select the correct answer using the codes given below the lists:
List-I List-II
A. (A ⊕ B) ⊕ (B ⊕ C) 1. (A  C)
B. AB + AC + BC 2. (A + B)  (A + C)
C. (A  B)  (B  C) 3. AB + AC
D. A + (B  C) 4. (A ⊕ C)
M

5. AB ⊕ AC
Codes
A B C D
(a) 4 3 1 2
(b) 3 4 1 2
(c) 2 3 1 2
(d) 4 3 5 2

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26. (a)
(A ⊕ B) ⊕ (B ⊕ C)
⇒ (A ⊕ B)(B ⊕ C) + (A ⊕ B)(B ⊕ C)

⇒ (AB + AB)(ABC + BC) + (AB + AB)(BC + BC)

⇒ ABC + ABC + ABC + ABC

⇒ AC(B + B) + AC(B + B)
(AC + AC) = A ⊕ C
(A) matches with (4)
AB + AC + BC = AB + AC
This is concensus law in XOR algebra.

SY
(C) matches with (1)
(B) matches with (3)
(A + B)  (A + C)
A + (B  C) = 
Follows distributive law

(D) matches with (2) EA

Q.27 The 3-bit ripple counter (shown below) is to be designed as a MOD 4 counter
Logic 1

T0 Q0 T1 Q1 T2 Q2
Clock
Cr Q0 Cr Q1 Cr Q2

Logic
Gate
E

What is the best architecture of the ‘Logic gate’?

(a) a 3-bit input AND gate
AD

(b) a 2-input AND gate

(c) a NOT gate
(d) a wire connection (no logic gate needed)

27. (d)

Q2 Q1 Q0 Cr
M

0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1

So the output Q2 can be directly connected to clear.

∴ Best architecture is a wire connection.

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Q.28 Consider a clocked sequential circuit as shown in the figure below. Assuming initial state to be
Q1 Q0 = 00
For an input sequence X = 1010, the respective output sequence will be _______.

Input
A D1 Q1
sequence
‘X’=1010
(LSB enters first)
Q1

B D0 Q0

SY
Q0

Clock

28. (1001)
FF1 FF0
Clock X Q1 Q0 Y = XQ1+Q0
D1 = Q1⊕X D0 = Q1⊕Q0

1
0
1
EA0
0
0
0
0
1
0
0
1
0
2 0 1 0 1 1 0
3 1 1 1 0 0 1
4 0 0

Answer is 1001.

Numerical Data Type Questions : Q. 29to Q. 33 carry 2 marks each

E

Q.29 The maximum number of Boolean expressions that can be formed for the function f(x, y, z) satisfying
the relation f(x,y,z) = f(x,y,z) is ___________.
AD

29. (16)
For every combination of x, y, z the function value remains same for input x,y,z .

x y z f(x, y, z) = f(x, y, z)
0 0 0 ⎫
⎬ either 0 or 1
1 0 1 ⎭
M

0 0 1 ⎫
⎬ either 0 or 1
1 0 0 ⎭
0 1 0 ⎫
⎬ either 0 or 1
1 1 1 ⎭
0 1 1 ⎫
⎬ either 0 or 1
1 1 0 ⎭
Effectively there are only four rows for the truth table of the function f (x, y, z).
∴ Total Boolean expressions possible is 24 = 16.

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Q.30 When (–89)10 is converted in binary, the sum of bits in binary will be ___________.

30. (5)
Binary representation of (89)10 = (01011001)
(–89)10 = 2’s compliment of (01011001)
So,2’s complement of (01011001) = (10100110) + (1) = 10100111
Sum of bits = 5

Q.31 Consider the digital circuit shown below. What will be the output Y, if the number B3 B2 B1 B0 =
0101

Logic 1 B3 B2 B1 B0

SY
A3 A2 A1 A0 Addend
Cin = 0
4-bit binary parallel adder

C4 EA S3 S2 S1 S0

I0 A B E
I1 4:1
Y
I2 MUX
I3

31. (1)
E

Addend will be = 1010

S3 S2 S1 S0 = 1010 + A3 A2 A1 A0 + Cin
AD

= 1010 + 1001
= 0011 (C4 = 1)
AB = 00
and E = C4 = 1
So, Y = 1
M

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Q.32 For a Mod-10 counter, Jhonson counter uses X FF′s, ring counter uses y FF′s, and ripple counter
uses Z FF′s. Then X + Y + Z will ________.

32. (19)
For MOD - 10 counter –
X = Jhonson counter required = 5 FF′s
Y = ring counter required = 10 FF′s
Z = ripple counter required = 4 FF′s
X+Y+Z = 5 + 10 + 4
= 19 FF′ s.

Q.33 Consider the digital circuit shown below

SY
DC QC JB QB DA QA

QC KB QB QA

Clk
EA
If initially QAQBQC is at 110 then minimum number of clock required to get QAQBQC equal to 011
is _______.

33. (6)
Given that, DA = QB,
JB = Q C ,
E

KB = QC ,
D C = QC  QA
AD

So, the state table is

Present state Next state
Clock D J K D
QA QB QC QA QB QC A B B C
1 1 1 0 1 0 0 1 0 1 0
2 1 0 0 0 0 0 0 0 1 0
3 0 0 0 0 0 1 0 0 1 1
4 0 0 1 0 1 0 0 1 0 0
M

5 0 1 0 1 0 1 1 0 1 1
6 1 0 1 0 1 1 0 1 0 1

Hence 6 clock pulses are required.

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