INTRODUCTION

TO
DIGITAL IC DESIGN
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 Outline
• Evolution of Digital IC Design
— Semiconductor History & Moore’s Law
— Evolutions in Semiconductor Industry
— Technology Shrink & ITRS Updates
— Technology Innovations
• Basics of Digital IC Design
— Design Styles and Abstracts
— BJT vs. MOSFET
— MOSFET Fundamentals
— CMOS Basics

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 Evolution of Digital IC Design

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 Evolution of Digital IC Design
Semiconductor History - a look back
• Transistor
— Vacuum tubes ruled in first half of 20th century
— Large, expensive, power-hungry and unreliable
— First Point Contact Transistor, December 16, 1947
— William Shockley, John Bardeen, and
Walter H. Brattain, at Bell Laboratories
• Integrated Circuit
— First Integrated Circuit (IC), September 12, 1958 First Point Contact Transistor

— Flip-flop in a solid bar of Germanium with

size 1.6 x 11.1 mm by Jack Kilby,
Texas Instruments
— First IC with Silicon by Robert Noyce,
Fairchild Semiconductor Corporation
— First commercial IC, Fairchild
Semiconductor Corporation, 1961
First Integrated Circuit
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 Evolution of Digital IC Design
Moore’s Law
As a result of continuous miniaturization, Transistor count would
double every 18 months; area and cost remains the same.
- Gordon E. Moore, 1965

 α is the scaling factor 6

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 Evolution of Digital IC Design
Evolution in Circuit Size
• SSI, Small Scale Integration
— Less than 10 Gates; Less than 64 components; 1964
• MSI, Medium Scale Integration
— Less than 100 Gates; Less than 2K components; 1968
• LSI, Large Scale Integration
— Less than 10,000 Gates; Less than 64K components; 1971
• VLSI, Very Large Scale Integration
— Less than 1 Million Gates; Less than 2M components; 1980
• ULSI, Ultra Large Scale Integration
— More than 1 Million Gates; More than 2M components; 1990
• GSI, Grand Scale Integration
— More than 1 Billion Gates; 2010
• 3D IC/ Non-planar IC
— More than 2 layers of active devices
• WLI, Wafer Level Integration
— An entire Silicon Wafer to produce a single "super-chip" 7
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 Evolution of Digital IC Design
Evolution in Device Technology

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 Evolution of Digital IC Design
Evolution
`
in EDA Tools
1950 – 1965 • Manual Design
• Layout Editors
1965 – 1975
• P&R tools 1st developed for PCB
1975 – 1985 • Sophisticated algorithms used in P&R tool
• First performance driven P&R tool
1985 – 1990
• Parallel optimization algorithms used in P&R tool
• First Over-the-Cell Routing
• First 3D and Multilayer P&R tool
• Automated circuit synthesis
1990 – 2000
• Routability oriented designs
• Emergence of Physical Synthesis
• Parallelizing workloads
• DFM, OPC
2000 – 2013 • Increased reusability
• IP reusability
2013 onwards • Double/ Multiple patterning

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 Evolution of Digital IC Design
Evolution in Fabrication Technology
Silicon
• Silicon to Silicon Wafer
— First chips were fabricated on 2-inch Wafers
— Now both 300-millimeter (12-inch) and
200-millimeter (8-inch) Wafers are using,
resulting in larger chip yields and decreased costs
— The larger Wafers can yield more than Wafer
twice as many chips, achieving an
economy of scale that will save 30%
in manufacturing costs for each Wafer
— 450mm Wafer as a recent advancement
• Wafer to Chip
— Using Photolithography the design in the Mask
is fabricated on the Wafer Chip
— Immersion Lithography for lower nodes
— Recent advancement is in
Extreme Ultra-violet (EUV) Lithography
— The Chip thus manufactured is packed with the
IO Pins connected
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 Evolution of Digital IC Design
Evolution in Processors
• 1971, Intel 4004, 108 KHz Clock, PMOS only 2,300 Transistors, 10 μm process Intel 4004
• 1976, Intel 8085, 3 MHz Clock , 6,500 Transistors, 3 µm process
• 1985, Intel 80386, 33 MHz Clock , 275,000 Transistors, 1 µm process
• 1993, Intel Pentium P54, 75 MHz Clock, 3.2 million Transistors, 0.6 µm process
• 1995, AMD Am5x86, 150 MHz Clock , 0.35 µm process
• 1997, Intel Pentium II, 300 MHz Clock , 7.5 million Transistors, 0.35 µm process
Intel Pentium 4
• 1999, AMD Athlon, 500 MHz Clock, 22 million Transistors, 0.25 µm process
• 2000, Intel Pentium 4, 2 GHz Clock, 42 million Transistors, 0.18 µm process
• 2003, Intel Pentium M, 1.7 GHz Clock, 77 million Transistors, 0.13 µm process
• 2006, Intel Core 2, 1.86 GHz Clock, 291 Million Transistors, 65 nm process
• 2008, Intel Core 2 Quad, 2.83 GHz Clock, 820 Million Transistors, 45 nm process
ARM Cortex A15
• 2010, ARM Cortex A15, 2.5 GHz Clock, 32nm and 22 nm process
• 2011, Core i7 3970X, 3.5 GHz Clock, 1.16 Billion Transistors, 32nm process
• 2012, Core i7 4960X, 3.6 GHz Clock, 1.4 Billion Transistors, 22nm Tri-gate process
• 2012, AMD FX-8350, 4.0 GHz Clock, 1.2 Billion Transistors, 32nm SOI process
• 2013, Intel Core i7 4771, 3.5 GHz Clock, 1.4 Billion Transistors, 22nm Tri-gate process
• 2013, ARM Cortex-A57, 16nm FinFET processes (Taped out with TSMC library)

• 2014, Intel, 14nm (anticipation)

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 Evolution of Digital IC Design
System-on-Chip (SoC)
• Complex designs with multiple embedded processors,
memory subsystems, and application specific peripherals on a
single piece of Silicon
• Extensive no. of Intellectual Properties (IPs) are used for an
SoC Design
• The Evolution of SoC
— 1995 - NEC, AT&T and Phillips proposed SoC
— 1996 - STi5500 Omega, first commercial SoC,
SGS-Thomson (STMicroelectronics)
— 2011 - Freeman, first Digital TV SoC,
STMicroelectronics
— 2013 - Speedster22i, first FinFET-based
System-on-Chip, Taped-out by Achronix
• Leading Smart Phone SoCs
— Snapdragon 800, Qualcomm, 28 nm, 2.3 GHz
— Atom Bay Trail, Intel, 22 nm, 2.1 GHz
— Tegra 4i, Nvidia, 28nm, 2.3 GHz
— Exynos 5 Octa, Samsung, 1.8 GHz, 28 nm HKMG
— MT6592, MediaTek, 2 GHz
— BCM7445, Broadcom, 28nm, 2.4 GHz Typical SoC Architecture
— A7 Apple, 28nm HKMG, 1.3 GHz, Over 1B Transistors, 102mm2

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 Evolution of Digital IC Design
Technology Shrink
• Technology Shrink/ Process Shrink refers to scaling of
semiconductor devices
• Technology Shrink makes products with less power
consumption (less heat dissipation), and lower prices, but with
higher operating frequency
• Classical Feature Size for calculating Technology Node is the
Channel Length Scaling in 0.7x (1/√2 x), so that the Effective Area
Scaling will be 0.5x
— Channel Area = (W . L) = (1/√2 . 1/√2) = 1/2, so to reduce ½ the Area,
scale at 0.7x
— The area reduces by ½ for Full/ Main Node and 1/√2 for Stopgap Half
Node
— Next Full Node = [Current Node Feature Size]/√2
e.g., 45x45 = 2025 to 32x32 = 1024

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 Evolution of Digital IC Design
Technology Shrink
• Issues due to Scaling
— Source/Drain overlap has been quickly shrinking
— Good Current (Current that can be controlled by Gate) reduces
— Bad Current (Current that cannot be controlled by Gate) will be far from Gate
— Stress Engineering is huge; e.g. at 32nm node, stress enhances Hole Mobility
by 3.5x
— Second Order Effects will become prominent

Scanning Electron Microscopic (SEM) Images

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 Evolution of Digital IC Design
ITRS
• International Technology Roadmap For Semiconductors (ITRS)
insisted on extrapolating Gate Length to zero if scaling in 0.7X
pace; to avoid it, industry kept a much slower, 0.9X scaling pace
(e.g. 32*0.9 ~ 28, 32*0.7 ~ 22)
• The Classical Shrinking trend cannot continue, as there’s no
space left for the Contact in conventional Planar MOSFET and
the Effective Channel Length kept unchanged for the best ION/IOFF
ratio
• Smaller Transistors with LEFF<25nm is possible but their
performance is inferior to that of MOSFET’s with LEFF = 25nm
• Due to performance reason MOSFET Channel Length is fixed
as ~ 25nm
• Technology Scaling by scaling the Metal 1 Pitch (vertical
scaling by 0.7X) and contacted Gate Pitch (horizontal scaling by
0.7X) to give a total of 0.5X area scaling
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 Evolution of Digital IC Design
ITRS Update
• For Logic designs, the Gate Length became the smallest
Feature, but for Memory designs the Half-Pitch remained the
smallest Feature
• For Logic designs Feature Size is kept as Contacted Poly Pitch,
the 1st Metal Layer Pitch
• For Memory designs Feature Size is kept as adjacent memory
cells ½ Pitch
• ITRS abandoned the term Technology Node in 2005, but its
usage has persisted
• Memory Chips are 1 full chip generation ahead of Logic Chips

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 Evolution of Digital IC Design
ITRS Update
Half Gate Half
Node
Year Node Length* Pitch
(nm)
(nm) (nm) (nm)
1992d 500 – 500 500
1995d 350 – 350 350
1997d 250 220 200 250
1999c 180 150 140 230
2001c 130 110 65 150
2004b 90 80 37 90
2005b 65 55 32 90
2007a 45 40 38 68
2009a 32 28 29 52
2012 22 20 24 34 Illustration of Gate Length and Pitch
2015 16 14 – –
2017 11 10 – – In 45nm node the Gate Length of a micro-
2020 8 7 – – processor is 38nm, but the half-pitch for
the 1st Metal Layer is 40nm
2022 5 – – –
a- ITRS 2008; b- ITRS 2006; c- ITRS 2001; d- ITRS 1997
* The physical length has become smaller than printed length

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 Evolution of Digital IC Design
Technology Innovations
• Closer Gate to Channel and Bad Current reduction can be achieved by
Silicon-on-Insulator (SOI) or FinFET (3D Device)
• FinFET benefits
— S/D underlap, not overlap (FinFET is necessary at 15nm Node onwards)
— Provides high performance and are insensitive to random dopant fluctuations, but
need change in Process and Design, also FinFETs are sensitive to geometry and requires
Spacer Lithography
• SOI benefits
— Very low Stress Transfer Efficiency for both SiGe Source/Drain and Strained Gate, so only
12% stress is transferred to the Channel where Planar FETs and FinFET are having >50%
Stress Transfer Efficiency
— The unique feature of FD-SOI is the ability to tune the VTH in a wide range with Backbias
• Individual companies are on different technology implementation timing
paces based on their product market needs, competitive position, and
Technology Roadmap
• Recent trend is 3D ICs i.e., more than 2 layers of active devices
• Industry is waiting for the mass production of Extreme Ultra Violet
Lithography (EUVL) and FD-SOI wafers
• Till then Multiple Patterning Techniques are required in designs below
20nm
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 Basics of Digital IC Design

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 Basics of Digital IC Design
Design Style
• Full Custom Design
— The entire design of the IC, down to the smallest detail of the layout
— The geometry, orientation and placement of every transistor is done individually by the designer
• Standard Cell Design
— Designer uses a library of
developed and characterized
Standard Cells
— Standard-cells based design is
often called semi-custom design
— An automatic Place and
Route tool does the Layout
• Gate Array Design
— Pre-fabricated array of
Gates (NAND)
— Gates already created on a
Wafer, only need to add the
interconnections
• Field Programmable Gate Array (FPGA) Design
— Pre-fabricated array of Programmable Logic and interconnections
— Field Programmable devices are arrays of Logic Components whose connectivity can be established
simply by loading appropriate configuration data into device’s internal memory
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 Basics of Digital IC Design
Design Abstraction Levels

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 Basics of Digital IC Design
BJT vs. MOSFET
BJT MOSFET
3 terminal device 4 terminal device
Current Controlled Device Voltage Controlled Device
Lower Integration Density Higher Integration Density
Low Input Impedance High Input Impedance
Less Noise Margins Excellent Noise Margins
Faster operation Slower operation
Higher power dissipation Low power dissipation
Poor switch Good switch

BJT MOSFET
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 Basics of Digital IC Design
MOSFET
• Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
— The 4 Terminals of MOSFET are Gate (G), Source (S), Drain (D), Body or
Bulk (B) or Substrate (Sub)
— Voltage Controlled Device
— The control Voltages are VGS & VDS
— Unipolar Device: Conduction only by one type of charge carrier
— Vertical Electric field (EV) between Gate & Substrate makes the Channel
— The electrical conduction through the induced Channel
— Horizontal Electric field (EH) between Source and Drain sweeps the
carries through the Channel

MOSFET 23
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 Basics of Digital IC Design
MOSFET
• Types of MOSFETs
— Enhancement Type (E-MOSFET)
 Normally OFF
 In Enhancement Type MOSFET the
Channel has to get enhanced by the
Voltage applied at the Gate Terminal
— Depletion Type (D-MOSFET)
 Normally ON
 In Depletion Type MOSFET the Channel is
already depleted during manufacturing
• Both Enhancement Type and Depletion Type MOSFETs are
further classified as:
— N Channel MOSFET (NMOS)
— P Channel MOSFET (PMOS)
• Enhancement type NMOS
and PMOS are used commonly
in Digital Designs
MOS Symbols
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 Basics of Digital IC Design
MOSFET Characteristics

• n-type Source & Drain and p-type Substrate • p-type Source & Drain and n-type Substrate
• n-type channel and Substrate always connecting to GND • p-type channel and Substrate always connecting to VDD
• Thus NMOS conducts when a logic 1 at the Gate terminal • Thus PMOS conducts when a logic 0 at the Gate terminal
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 Basics of Digital IC Design
MOSFET – Regions of Operation
• Cutoff Region
— No channel
• Linear/
Non-Saturation/
Weak Inversion
— The shape of the
channel alters
— Similar to a
linear resistor
• Saturation/
Strong Inversion
— Channel Pinch-off
occurs
— Similar to a
Constant Current ;where VΔ = VGS – VTH
Source

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 Basics of Digital IC Design
MOSFET – Modes of Operation
• Accumulation Mode
— When the Gate-Source voltage (VGS) is zero, the Drain-Source voltage
(VDS) prevents current from the drain to the source

• Depletion Mode
— Deplete the NMOS & PMOS channels with small values of VGS
— Majority carriers in Substrate starts repelled away from the Gate

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 Basics of Digital IC Design
MOSFET – Modes of Operation
• Inversion Mode
— Creating the conducting channel for NMOS and PMOS
— Minority Carriers in substrate attracts towards Gate and a channel is
forming

• Channel Pinch-off for NMOS and PMOS devices

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 Basics of Digital IC Design
MOSFET – Second Order Effects
• As the Technology Scaling reaches Channel Lengths less than a
micron (L<1μ), Second Order Effects become very prominent
• MOSFET‘s with L<1μ are called “Short Channel Devices” with
prominent Short Channel Effects (SCE)
• The Second Order Effects are considered during Cell
Characterization
• The Second Order Effects –
— Body Effect — Drain Punch Through
— Channel Length Modulation — Sub-Threshold Conduction
— Velocity Saturation — Mobility Variation
— Flower-Nordheim Tunneling — Avalanche Breakdown
— Impact Ionization — Ballistic Transport
— Drain Induced Barrier Lowering

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 Basics of Digital IC Design
MOSFET Parasitic Capacitances
• Cgb, Gate to Bulk
Capacitance
— Gate and Channel
Charge Capacitance
+ Channel and
Bulk Capacitance
• Cgd or Cgs, Gate to Drain/
Source Capacitance
— Also called Overlap
Capacitance, Cov MOSFET Parasitic Capacitances
• Cj,sb or Cj,db, Source/ Drain Junction
Capacitance to Bulk
— Across Reverse-biased PN Junction
• Cjsw,sb or Cjsw,db, Source and Drain
Junction Sidewall Capacitance to Bulk
— Across Reverse-Biased PN Junction

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 Basics of Digital IC Design
MOSFET C-V Characteristics
• The 3 modes of operation of the MOS Capacitor change as a
function of the applied voltage
• Accumulation
— When VGS < VTH
• Depletion
— When majority carriers in Substrate start repelled away from Gate
• Inversion
— When VGS > VTH with VD=0, minority carriers in Substrate attracts
towards Gate and the Channel is forming

<-Accumulation->
<-Inversion-> <-Accumulation-> <-Inversion->
<-Depletion-> <-Depletion->
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 Basics of Digital IC Design
CMOS
• Complementary Metal Oxide Semiconductor (CMOS)
• Complementary and Symmetrical pairs of P-type and N-type MOSFETs
of Enhancement type are using in CMOS
— NMOS for Pull-down (Connects to VSS)
— PMOS for Pull-up (Connects to VDD)
• CMOS Special Features
— Low Static Power consumption
— High noise immunity
— Power dissipation only during switching
CMOS Schematic
— High density of logic functions
— Low to High time (Rise Time) & High to Low time (Fall Time) are faster than in
NMOS technology
— If the input is logic 1, then the output will be logic 0 and vice versa, which makes
the CMOS identical to an Inverter
• If Gate terminal = Logic 0 (A=0), then high resistance between Output
(Q) and GND (VSS) & low resistance between Output (Q) and PWR (VDD)
• If Gate terminal = Logic 1 (A=1), then high resistance between Output
(Q) and PWR (VDD) & low resistance between Output (Q) and GND (VSS)
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 Basics of Digital IC Design
Layout & Cross-section of CMOS Inverter

L L

W W

L L

• Connect to most negative • Connect to most positive supply

supply voltage in most circuits voltage in most circuits
• Reverse Bias the PN Junction • Reverse Bias the PN Junction
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 Basics of Digital IC Design
Layout of CMOS Inverter
• Oxide Diffusion (OD) is the actual Transistor and is so called
the Active Area
• OD will provide the information regarding the region where we
need the appropriate Diffusion
• N+/ P+ implant is a requirement for
making the mask and will provide the
information about the type of implant
required for the Diffusion
• Poly is the Gate area, underneath
the Channel is forming
PMOS
• In fabrication process Poly will be
created before the Active Area creation
• Contact will provide the connectivity
between OD and the Metal Layer
NMOS 34
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 Basics of Digital IC Design
CMOS Inverter Voltage-Transfer-Curve (VTC)
• Current will be max. at the Transition Region of CMOS Inverter
i.e., when both MOSFETs are in Saturation Region
• The VTC is classified into 5 regions as shown

CMOS Inverter Voltage-Transfer-Curve (VTC)

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 Basics of Digital IC Design
CMOS Dynamic Power Dissipation
• Increased operating frequency and shrinking technology increases the
Dynamic Power (PDYN) and can be classified as below:
• Switching Power
– Power required for charging and discharging of output capacitances
– A function of load capacitance and switching activity
– Not a function of transistor size
• Internal Power
– Current required to charge the internal capacitance of the cell
– When both NMOS and PMOS are ON
– A function of power supply, Peak current, clock frequency and Short-Circuit time period

PDYN = (CEFF VDD2 IPEAK fCLK)+ (tSC VDD IPEAK fCLK)

• To reduce the Dynamic Power (PDYN)

– Lower the operating voltage (VDD) : Quadratic effect
– Reduce the operating frequency (fCLK) : By reducing clock frequency/ lower signal activity
– Reduce the load capacitance (CEFF) : By short interconnect lengths/ drive small gate load
– Reduce the Short Circuit Time (tSC) duration: By optimizing slope/slew of the input

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 Basics of Digital IC Design
CMOS Static Power Dissipation
• Aggressive scaling of CMOS circuits in recent times has led to dramatic
increase in leakage currents
• To reduce the Static Power (PSTATIC)
– Use smaller Transistors (Leakage α Width)

– Lower the Operating Voltage (VDD)

– Increase the Threshold Voltage (VTH)
– Use HKMG
PSTATIC = VDD IOFF
CMOS Leakage Currents
• CMOS leakage components (IOFF Components)
 I1 PN-Junction Leakage (IREV)  I5 Punch-through Current
 Due to minority carrier drift and electron-hole  Punch Through condition: High Drain voltage
pair generation in the depletion region causes the Drain Depletion Region to extend up
to Source
 I2 Sub-threshold Leakage (ISUB)
 Weak Inversion Drain to Source Leakage  I6 Narrow Width Effects
 MOSFET won’t get OFF completely  I7 Gate Leakage (IGATE)
 I3 DIBL and contribution from SCE  Tunneling through Gate Oxide
 Drain Induced Barrier Lowering (DIBL) caused by  I8 Hot Carrier Injection
high Drain potential consequently decreases VTH  Due to Electron-Hole pair generation during
 I4 Gate Induced Drain Leakage (GIDL) Impact Ionization
 Leakage from Drain to Substrate due to high field  Hot Carrier Induced (HCI) degradation
at Drain 37
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 Basics of Digital IC Design
MOS Capacitor
• MOSFET Capacitor forming by shorting Drain & Source
— MOS Cap is SiO2 placed between the Substrate and the Gate
— The Substrate and the Gate are the two plates of the Capacitor
— MOSFET in active region of operation
— The area of the Gate defines the area of the Capacitor
C = CGS = Cox W L
• NMOS caps are superior to PMOS caps because of the high
frequency operation and effective capacitance
• NMOS cap and PMOS cap together forms CMOS cap

NMOS Cap
Parallel CMOS Cap Cross Coupled CMOS Cap 38
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 Basics of Digital IC Design
MOS Diode
• The integral PN-Junctions in MOS is utilized to form a Diode
• Advantage is no need of a separate mask set to fabricate Diode
• MOS Diode can be:
— N+/PSUB Diode using NMOS
— P+/NWELL Diode using PMOS
(low noise)
• MOS as Diode can also possible
as Diode Connected configuration
— Always in Saturation
— Never operates in Triode Mode
— Gate and Drain/Source shorted

NMOS and PMOS as Diode Connected

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 Thank You

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