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Lab#2 (3x8 Decoder Using Gate Level and Data Flow Abstraction) Objectives

This document describes the design and verification of 2x4 and 3x8 decoders using gate level and dataflow abstraction in ModelSim. It presents the code for a 2x4 decoder module using gates, its testbench, and a screenshot of its output. It then shows the code for a 3x8 decoder module using gates, its testbench, and an output screenshot. Finally, it provides the code for 2x4 and 3x8 decoder modules using dataflow abstraction, their testbenches, and output screenshots. The objective is to implement and verify 2x4 and 3x8 decoders at both the gate level and using dataflow abstraction.

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Amina Tabassum
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176 views4 pages

Lab#2 (3x8 Decoder Using Gate Level and Data Flow Abstraction) Objectives

This document describes the design and verification of 2x4 and 3x8 decoders using gate level and dataflow abstraction in ModelSim. It presents the code for a 2x4 decoder module using gates, its testbench, and a screenshot of its output. It then shows the code for a 3x8 decoder module using gates, its testbench, and an output screenshot. Finally, it provides the code for 2x4 and 3x8 decoder modules using dataflow abstraction, their testbenches, and output screenshots. The objective is to implement and verify 2x4 and 3x8 decoders at both the gate level and using dataflow abstraction.

Uploaded by

Amina Tabassum
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Lab#2

(3x8 Decoder using Gate Level and Data flow Abstraction)

Objectives:
“Design and verification of 2x4 & 3x8 Decoder using Gate Level and Data flow Abstraction in
ModelSim”

Decoder 2x4 using Gates Level


module decoder2x4 (O, S, E);
input[1:0] S; input E;
output[3:0] O;
wire w1, w2;
not (w1, S[1]);
not (w2, S[0]);
and (O[3], S[1],S[0],E);
and (O[2], S[1],w2,E);
and (O[1], w1,S[0],E);
and (O[0], w1,w2,E);
endmodule

module t_decoder2x4;
reg[1:0] S;
reg E;
wire[3:0] O;
decoder2x4 d1(O, S, E);
initial begin
S=2'b0; E=1'b1;
repeat(4)
#100 S=(S+2'b01);
#100 $finnish;
end
endmodule

Figure 1 2x4 decoder output


Decoder 3x8 using Gates Level
module decoder3x8(O,S);
input[2:0] S;
output[7:0] O;
wire w1;
not (w1, S[2]);
decoder2x4 d1(.O(O[3:0]), .S(S[1:0]), .E(w1));
decoder2x4 d0(.O(O[7:4]), .S(S[1:0]), .E(S[2]));
endmodule

module t_decoder3x8;
reg[2:0] S;
wire[7:0] O;
decoder3x8 d1(O,S);
initial begin
S=3'b0;
repeat(8)
#100 S=(S+3'b001);
#100 $finnish;
end
endmodule

Figure 2 3x8 Decoder output


Decoder 2x4 using Dataflow Abstraction
module decoder2x4_dataflow(O,E,S);
input[1:0] S; input E;
output[3:0] O;
assign O[0] = (~S[0] & ~S[1] & E);
assign O[1] = (S[0] & ~S[1] & E);
assign O[2] = (~S[0] & S[1] & E);
assign O[3] = (S[0] & S[1] & E);
endmodule

module t_decoder2x4_df;
reg[1:0] S; reg E;
wire[3:0] O;
decoder2x4_dataflow d1(O, E, S);
initial begin
S=2'b0; E=1'b1;
repeat(4)
#100 S=(S+2'b01);
#100 $finnish;

Figure 3 2x4 decoder output


Decoder 3x8 using Dataflow Abstraction
module decoder3x8_dataflow(O,S);
input[2:0] S;
output[7:0] O;
assign w1 = ~S[2];
decoder2x4_dataflow d1(.O(O[3:0]), .S(S[1:0]), .E(w1));
decoder2x4_dataflow d2(.O(O[7:4]), .S(S[1:0]), .E(S[2]));
endmodule

end
endmodule

module t_decoder3x8_df;
reg[2:0] S;
wire[7:0] O;
decoder3x8_dataflow d1(O,S);
initial begin
S=3'b0;
repeat(8)
#100 S=(S+1'b1);
#100 $finnish;
end
endmodule

Figure 4 3x8 Decoder output

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