FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Current Mode PWM Controller

February 2013

FAN6921MR
Integrated Critical Mode PFC and Quasi-Resonant
Current Mode PWM Controller

Features Description
 Integrated PFC and Flyback Controller The highly integrated FAN6921MR combines Power
Factor Correction (PFC) controller and Quasi-Resonant
 Critical Mode PFC Controller PWM controller. Integration provides cost effect design
 Zero-Current Detection for PFC Stage and allows for fewer external components.

 Quasi-Resonant Operation for PWM Stage For PFC, FAN6921MR uses a controlled on-time
technique to provide a regulated DC output voltage and
 Internal Minimum tOFF 8 µs for QR PWM Stage to perform natural power factor correction. With an
 Internal 10 ms Soft-Start for PWM innovative THD optimizer, FAN6921MR can reduce
input current distortion at zero-crossing duration to
 Brownout Protection improve THD performance.
 High / Low Line Over-Power Compensation For PWM, FAN6921MR provides several functions to
 Auto-Recovery Over-Current Protection enhance the power system performance: valley
detection, green-mode operation, high / low line over
 Auto-Recovery Open-Loop Protection power compensation. FAN6921MR provides many
 Externally Latch Triggering (RT Pin) protection functions as well: secondary-side open-loop
and over-current with auto recovery protection, external
 Adjustable Over-Temperature Latched (RT Pin) latch triggering, adjustable over-temperature protection
 VDD Pin and Output Voltage OVP (Latched) by RT pin and external NTC resistor, internal over-
temperature shutdown, VDD pin OVP, and DET pin over-
 Internal Over-Temperature Shutdown (140°C) voltage for output OVP, and brown-in / out for AC input
voltage UVP.
Applications The FAN6921MR controller is available in a 16-pin small
outline package (SOP).
 AC/DC NB Adapters
 Open-Frame SMPS
 Battery Charger

Ordering Information

OLP Operating Packing

Part Number Package
Mode Temperature Range Method
FAN6921MRMY Recovery -40°C to +105°C 16-Pin Small Outline Package (SOP) Tape & Reel

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Application Diagram

Figure 1. Typical Application

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 2
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Internal Block Diagram

Figure 2. Functional Block Diagram

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 3
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Marking Information

Figure 3. Marking Diagram

Pin Configuration

Figure 4. Pin Configuration

Pin Definitions
Pin # Name Description
RANGE pin’s impedance changes according to VIN pin voltage level. When the input voltage
1 RANGE detected by VIN pin is lower than a threshold voltage, it sets to high impedance; whereas it sets
to low impedance if input voltage is high level.
Output pin of the error amplifier. It is a transconductance type error amplifier for PFC output
voltage feedback. Proprietary multi-vector current is built-in to this amplifier. Therefore the
2 COMP
compensation for PFC voltage feedback loop allows a simple compensation circuit between this
pin and GND.
Inverting input of the error amplifier. This pin is used to receive PFC voltage level by a voltage
3 INV
divider and provides PFC output over- and under-voltage protections.
Input to the PFC over-current protection comparator that provides cycle-by-cycle current limiting
4 CSPFC protection. When the sensed voltage across the PFC current sensing resistor reaches the internal
threshold (0.82 V typical), the PFC switch is turned off to activate cycle-by-cycle current limiting.
Input to the comparator of the PWM over-current protection and performs PWM current-mode
control with FB pin voltage. A resistor is used to sense the switching current of PWM switch and
5 CSPWM the sensing voltage is applied to the CSPWM pin for the cycle-by-cycle current limit, current-
mode control, and high / low line over-power compensation according to DET pin source current
during PWM tON time.
Continued on the following page…

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 4
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Pin Definitions (Continued)
Pin # Name Description
Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage
6 OPFC
is 15.5 V.
Power supply. The threshold voltage for startup and turn-off is 18 V and 7.5 V, respectively. The
7 VDD
startup current is less than 30μA and the operating current is lower than 10 mA.
Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped
8 OPWM
gate output voltage is 17.5 V.
9 GND The power ground and signal ground.
This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for
the following purposes:
 Producing an offset voltage to compensate the threshold voltage of PWM current limit for
providing over-power compensation. The offset is generated in accordance with the input
voltage when PWM switch is on.
10 DET  Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley
voltage switching and minimize the switching loss on PWM switch.
 Providing output over-voltage protection. A voltage comparator is built-in to the DET pin. The
DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This
flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output
OVP and this flat voltage is higher than 2.5 V, the controller enters latch mode and stops all
PFC and PWM switching operation.
Feedback voltage pin. This pin is used to receive output voltage level signal to determine PWM
gate duty for regulating output voltage. The FB pin voltage can also activate open-loop, over-load
protection, and output-short circuit protection if the FB pin voltage is higher than a threshold of
11 FB
around 4.2 V for more than 50 ms.The input impedance of this pin is a 5 kΩ equivalent
resistance. A 1/3 attenuator is connected between the FB pin and the input of the CSPWM/FB
comparator.
Adjustable over-temperature protection and external latch triggering. A constant current is flowed
12 RT out of the RT pin. When RT pin voltage is lower than 0.8 V (typical), latch mode protection is
activated and stops all PFC and PWM switching operation until the AC plug is removed.
Line-voltage detection for brown-in / out protections. This pin can receive the AC input voltage
13 VIN level through a voltage divider. The voltage level of the VIN pin is not only used to control
RANGE pin’s status, but it can also perform brown-in / out protection for AC input voltage UVP.
Zero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to
PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current discharges
to zero. When the ZCD voltage signal is detected, the controller starts a new PFC switching
14 ZCD
cycle. When the ZCD pin voltage is pulled to under 0.2 V (typical), it disables the PFC stage and
the controller stops PFC switching. This can be realized with an external circuit if disabling the
PFC stage is desired.
15 NC No connection
High-voltage startup. HV pin is connected to the AC line voltage through a resistor
16 HV
(100 kΩ typical) for providing a high charging current to VDD capacitor.

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 5
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VDD DC Supply Voltage 30 V
VHV HV 500 V
VH OPFC, OPWM -0.3 25.0 V
VL Others (INV, COMP, CSPFC, DET, FB, CSPWM, RT) -0.3 7.0 V
VZCD Input Voltage to ZCD Pin -0.3 12.0 V
PD Power Dissipation 800 mW
θJA Thermal Resistance (Junction-to-Air) 104 °C/W
θJC Thermal Resistance (Junction-to-Case) 41 °C/W
TJ Operating Junction Temperature -40 +150 °C
TSTG Storage Temperature Range -55 +150 °C
TL Lead Temperature (Soldering 10 Seconds) +260 °C
(3)
Human Body Model, JESD22-A114 (All Pins Except HV Pin) 4500
ESD V
Charged Device Model, JESD22-C101 (All Pins Except HV Pin)(3) 1250
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to GND pin.
3. All pins including HV pin: CDM=750 V, HBM 1000 V.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Max. Unit

TA Operating Ambient Temperature -40 +105 °C

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 6
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Electrical Characteristics
VDD=15 V, TA=-40°C~105°C (TA=TJ), unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

VDD Section
VOP Continuously Operating Voltage 25 V
VDD-ON Turn-On Threshold Voltage 16.5 18.0 19.5 V
VDD-PWM-OFF PWM Off Threshold Voltage 9 10 11 V
VDD-OFF Turn-Off Threshold Voltage 6.5 7.5 8.5 V
VDD=VDD-ON - 0.16 V,
IDD-ST Startup Current 20 30 µA
Gate Open
VDD=15 V,
IDD-OP Operating Current OPFC, OPWM=100 kHz, 10 mA
CL-PFC, CL-PWM=2 nF
VDD=15 V,
Green-Mode Operating Supply
IDD-GREEN OPWM=450 Hz, 5.5 mA
Current (Average)
CL-PWM=2 nF
Operating Current at PWM-Off
IDD-PWM-OFF VDD=VDD-PWM-OFF - 0.5 V 70 120 170 µA
Phase
VDD Over-Voltage Protection
VDD-OVP 26.5 27.5 28.5 V
(Latch-Off)
tVDD-OVP VDD OVP Debounce Time 100 150 200 µs
VDD Over-Voltage Protection
IDD-LATCH VDD=7.5 V 120 µA
Latch-Up Holding Current
HV Startup Current Source Section
Minimum Startup Voltage on HV
VHV-MIN 50 V
Pin
VAC=90 V (VDC=120 V),
1.3 mA
VDD=0 V
IHV Supply Current Drawn from HV Pin
HV=500 V,
1 µA
VDD= VDD-OFF +1 V
VIN and RANGE Section
Threshold Voltage for AC Input
VVIN-UVP 0.95 1.00 1.05 V
Under-Voltage Protection
Under-Voltage Protection Reset VVIN-UVP VVIN-UVP VVIN-UVP
VVIN-RE-UVP V
Voltage (for Startup) +0.25V +0.30V +0.35V
Under-Voltage Protection
tVIN-UVP Debounce Time (No Need at 70 100 130 ms
Startup and Hiccup Mode)
High VVIN Threshold for RANGE
VVIN-RANGE-H 2.40 2.45 2.50 V
Comparator
Low VVIN Threshold for RANGE
VVIN-RANGE-L 2.05 2.10 2.15 V
Comparator
Range-Enable/ Disable Debounce
tRANGE 70 100 130 ms
Time
VRANGE-OL Output Low Voltage of RANGE Pin IO=1 mA 0.5 V
Output High Leakage Current of
IRANGE-OH RANGE=5 V 50 nA
RANGE Pin
tON-MAX-PFC PFC Maximum On Time RMOT=24 kΩ 22 25 28 µs

Continued on the following page…

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FAN6921MR Rev. 1.0.4 7
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Electrical Characteristics (Continued)
VDD=15 V, TA=-40°C ~105°C (TA=TJ), unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

PFC Stage
Voltage Error Amplifier Section
Gm Transconductance(4) 100 125 150 µmho
Feedback Comparator Reference
VREF 2.465 2.500 2.535 V
Voltage
RANGE=Open 2.70 2.75 2.80
VINV-H Clamp High Feedback Voltage V
RANGE=Ground 2.60 2.65 2.70
VINVH / VREF,
1.06 1.14
(4) RANGE=Open
VRATIO Clamp High Output Voltage Ratio V/V
VINVH / VREF,
1.04 1.08
RANGE=Ground
VINV-L Clamp Low Feedback Voltage 2.25 2.35 2.45 V
Over-Voltage Protection for INV RANGE=Open 2.90 2.95
VINV-OVP V
Input RANGE=Ground 2.75 2.80
Over-Voltage Protection Debounce
tINV-OVP 50 70 90 µs
Time
Under-Voltage Protection for INV
VINV-UVP 0.35 0.45 0.55 V
Input
Under-Voltage Protection
tINV-UVP 50 70 90 µs
Debounce Time
PWM and PFC Off Threshold for
VINV-BO 1.15 1.20 1.25 V
Brownout Protection
Limited Voltage on COMP Pin for
VCOMP-BO 1.55 1.60 1.65 V
Brownout Protection
VCOMP Comparator Output High Voltage 4.8 6.0 V
Zero Duty Cycle Voltage on COMP
VOZ 1.10 1.25 1.40 V
Pin
Comparator Output Source VINV=2.3 V, VCOMP=1.5 V 15 30 45 µA
Current VINV=1.5 V 0.50 0.75 1.00 mA
ICOMP RANGE=Open,
20 30 40
VINV=2.75 V, VCOMP=5 V
Comparator Output Sink Current µA
RANGE=Ground,
20 30 40
VINV=2.65 V, VCOMP=5 V
PFC Current Sense Section
Threshold Voltage for Peak
VCSPFC VCOMP=5 V 0.82 V
Current Cycle-by-Cycle Limit
tPD Propagation Delay 110 200 ns
tBNK Leading-Edge Blanking Time 110 180 250 ns
CSPFC Compensation Ratio for
AV 0.90 0.95 1.00 V/V
THD

Continued on the following page…

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 8
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Electrical Characteristics (Continued)
VDD=15 V, TA=-40°C ~105°C (TA=TJ), unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

PFC Output Section
PFC Gate Output Clamping
VZ VDD= 25 V 14.0 15.5 17.0 V
Voltage
VOL PFC Gate Output Voltage Low VDD=15 V, IO=100 mA 1.5 V
VOH PFC Gate Output Voltage High VDD=15 V, IO=100 mA 8 V
VDD=12 V, CL=3 nF,
tR PFC Gate Output Rising Time 30 65 100 ns
20~80%
VDD=12 V, CL=3 nF,
tF PFC Gate Output Falling Time 30 50 70 ns
80~20%
PFC Zero Current Detection Section
Input Threshold Voltage Rising
VZCD VZCD Increasing 1.9 2.1 2.3 V
Edge
VZCD-HYST Threshold Voltage Hysteresis VZCD Decreasing 0.25 0.35 0.45 V
VZCD-HIGH Upper Clamp Voltage IZCD=3 mA 8 10 V
VZCD-LOW Lower Clamp Voltage 0.40 0.65 0.90 V
Starting Source Current
VZCD-SSC 1.3 1.4 1.5 V
Threshold Voltage
Maximum Delay from ZCD to
tDELAY VCOMP=5 V, fS=60 kHz 100 200 ns
Output Turn-On
tRESTART-PFC Restart Time 300 500 700 µs
Inhibit Time (Maximum Switching
tINHIB VCOMP=5 V 1.5 2.5 3.5 µs
Frequency Limit)
PFC Enable/ Disable Function
VZCD-DIS 0.15 0.2 0.25 V
Threshold Voltage
PFC Enable/ Disable Function
tZCD-DIS VZCD=100 mV 100 150 200 µs
Debounce Time

Continued on the following page…

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 9
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Electrical Characteristics (Continued)
VDD=15 V, TA=-40°C ~105°C (TA=TJ), unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

PWM STAGE
Feedback Input Section
Input-Voltage to Current Sense AV=△VCSPWM /△VFB,
AV 1/2.75 1/3.00 1/3.25 V/V
Attenuation(4) 0<VCSPWM<0.9
ZFB Input Impedance(4) FB>VG 3 5 7 kΩ
IOZ Bias Current FB=VOZ 1.2 2.0 mA
VOZ Zero Duty-cycle Input Voltage 0.7 0.9 1.1 V
Open-Loop Protection Threshold
VFB-OLP 3.9 4.2 4.5 V
Voltage
The Debounce Time for Open
tFB-OLP 40 50 60 ms
Loop Protection
tFB-SS Internal Soft-Start Time(4) VFB=0 V~3.6 V 8.5 9.5 10.5 ms
DET Pin OVP and Valley Detection Section
VDET-OVP Comparator Reference Voltage 2.45 2.50 2.55 V
(4)
Av Open-Loop Gain 60 dB
(4)
BW Gain Bandwidth 1 MHz
Output OVP(Latched) Debounce
tDET-OVP 100 150 200 µs
Time
IDET-SOURCE Maximum Source Current VDET=0 V 1 mA
VDET-HIGH Upper Clamp Voltage IDET=-1 mA 5 V
VDET-LOW Lower Clamp Voltage IDET=1 mA 0.5 0.7 0.9 V
Delay Time from Valley Signal
tVALLEY-DELAY 150 200 250 ns
Detected to Output Turn-on(4)
Leading-Edge Blanking Time for
DET-OVP (2.5 V) and Valley
tOFF-BNK 3 4 5 µs
Signal when PWM MOS Turns
Off(4)
tTIME-OUT Time-Out After tOFF-MIN 8 9 10 µs
PWM Oscillator Section
tON-MAX-PWM Maximum On Time 38 45 52 µs
VFB≧VN, TA=25°C 7 8 9
tOFF-MIN Minimum Off Time µs
VFB=VG 32 37 42
Beginning of Green-On Mode at
VN 1.95 2.10 2.25 V
FB Voltage Level
Beginning of Green-Off Mode at
VG 1.00 1.15 1.30 V
FB Voltage Level
Hysteresis for Beginning of
∆VG Green-Off Mode at FB Voltage 0.1 V
Level

Continued on the following page…

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 10
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Electrical Characteristics (Continued)
VDD=15 V, TA=-40℃~105℃ (TA=TJ), unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

RANGE Pin Internally
1.70 1.75 1.80
Threshold Voltage on FB Pin for Open
VCTL-PFC-OFF V
PFC EnableDisable RANGE Pin Internally
1.60 1.65 1.70
Ground
RANGE Pin Internally
1.85 1.90 1.95
Threshold Voltage on FB Pin for Open
VCTL-PFC-ON V
PFC Disable  Enable RANGE Pin Internally
1.70 1.75 1.80
Ground
PFC Enable 
tPFC-OFF PFC Disable Debounce Time 400 500 600 ms
Disable
PFC Disable 
tPFC-ON PFC Enable Debounce Time 2.0 2.5 3.0 ms
Enable
VFB ＜VG 1.85 2.25 2.65 ms
tSTARTER-PWM Start Timer (Time-Out Timer)
VFB ＞VFB-OLP 22 28 34 µs
PWM Output Section
PWM Gate Output Clamping
VCLAMP VDD=25 V 16.0 17.5 19.0 V
Voltage
VOL PWM Gate Output Voltage Low VDD=15 V, IO=100 mA 1.5 V
VOH PWM Gate Output Voltage High VDD=15 V, IO=100 mA 8 V
CL=3 nF, VDD=12 V,
tR PWM Gate Output Rising Time 80 110 ns
20~80%
CL=3 nF, VDD=12 V,
tF PWM Gate Output Falling Time 40 70 ns
20~80%
Current Sense Section
tPD Delay to Output 150 200 ns
IDET ＜75 µA, TA=25°C 0.81 0.84 0.87
The Limit Voltage on CSPWM IDET=185 µA, TA=25°C 0.69 0.72 0.75
VLIMIT Pin for Over Power V
Compensation IDET=350 µA, TA=25°C 0.55 0.58 0.61
IDET=550 µA, TA=25°C 0.34 0.40 0.46
tON=45 µs,
0.25 0.30 0.35
VSLOPE Slope Compensation(4) RANGE=Open V
tON=0 µs 0.05 0.10 0.15
tON-BNK Leading-Edge Blanking Time 300 ns
CSPWM Pin Floating VCSPWM
VCS-FLOATING CSPWM Pin Floating 4.5 5.0 V
Clamped High Voltage
The Delay Time once CSPWM
tCS-H CSPWM Pin Floating 150 µs
Pin Floating

Continued on the following page…

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FAN6921MR Rev. 1.0.4 11
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Electrical Characteristics (Continued)
VDD=15V, TA=-40°C~105°C (TA=TJ), unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

RT Pin Over-Temperature Protection Section
Internal Threshold Temperature
TOTP 125 140 155 °C
for OTP(4)
Hysteresis Temperature for
TOTP-HYST 30 °C
Internal OTP(4)
IRT Internal Source Current of RT Pin 90 100 110 µA
VRT-LATCH Latch-Mode Triggering Voltage 0.75 0.80 0.85 V
VRT-LATCH VRT-LATCH VRT-LATCH
VRT-RE-LATCH Latch-Mode Release Voltage V
+0.15 +0.20 +0.25
Threshold Voltage for Two-level
VRT-OTP-LEVEL 0.45 0.50 0.55 V
Debounce Time
tRT-OTP-H Debounce Time for OTP 10 ms
Debounce Time for Externally
tRT-OTP-L VRT<VRT-OTP-LEVEL 70 110 150 µs
Triggering
Note:
4. Guaranteed by design.

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 12
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Typical Performance Characteristics
These characteristic graphs are normalized at TA=25°C.

18.5 11.0

18.0 10.5

V DD-PWM-OFF (V)
V DD-ON (V)

17.5 10.0

17.0 9.5

16.5 9.0
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature(o C) Temperature(o C)

Figure 5. Turn-On Threshold Voltage Figure 6. PWM Off Threshold Voltage

8.5 29.0

8.0 28.5
V DD-OFF (V)

V DD-OVP (V)
7.5 28.0

7.0 27.5

6.5 27.0
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature(o C) Temperature(o C)

Figure 7. Turn-Off Threshold Voltage Figure 8. VDD Over-Voltage Protection Threshold

16.0 8.0

14.0
7.0
IDD-OP (mA)
IDD-ST (μA)

12.0
6.0
10.0
5.0
8.0

6.0 4.0
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature(o C) Temperature(o C)

Figure 9. Startup Current Figure 10. Operating Current

2.60 17.0

16.5
2.55
16.0
V REF (V)

V Z(V)

2.50 15.5
15.0
2.45
14.5

2.40 14.0
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
o o
Temperature( C) Temperature( C)

Figure 11. PFC Output Feedback Reference Voltage Figure 12. PFC Gate Output Clamping Voltage

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FAN6921MR Rev. 1.0.4 13
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Typical Performance Characteristics (Continued)
These characteristic graphs are normalized at TA=25°C.

28.0 0.95

27.0
tON-MAX-PFC (μsec)

0.90
26.0

V CSPFC (V)
25.0 0.85
24.0
0.80
23.0

22.0 0.75
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature(o C) Temperature( C) o

Figure 13. PFC Maximum On-Time Figure 14. PFC Peak Current Limit Voltage

19.0 50.0

18.5 48.0

tON-MAX-PWM (μsec)
18.0
V CLAMP (V)

46.0
17.5
44.0
17.0

16.5 42.0

16.0 40.0
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature(o C) Temperature(o C)

Figure 15. PWM Gate Output Clamping Voltage Figure 16. PWM Maximum On-Time

2.3 1.4

2.2 1.3
V G (V)
V N(V)

2.1 1.2

2.0 1.1

1.9 1.0
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature(o C) Temperature(o C)

Figure 17. Beginning of Green-On Mode at VFB Figure 18. Beginning of Green-Off Mode at VFB

9.0 42.0

40.0
8.5
tOFF-MIN (μsec)

tOFF-MIN (μsec)

38.0
8.0
36.0
7.5
34.0

7.0 32.0
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature(o C) Temperature(o C)

Figure 19. PWM Minimum Off-Time for VFB > VN Figure 20. PWM Minimum Off-Time for VFB=VG
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6921MR Rev. 1.0.4 14
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Typical Performance Characteristics (Continued)
These characteristic graphs are normalized at TA=25°C.

1.0 2.60

0.9
2.55
V DET-LOW (V)

V DET-OVP (V)
0.8
2.50
0.7
2.45
0.6

0.5 2.40
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature(o C) Temperature(o C)

Figure 22. Reference Voltage for Output

Figure 21. Lower Clamp Voltage of DET Pin
Over-Voltage Protection of DET Pin

110 0.90

105 0.85

V RT-LATCH (V)
I RT (μA)

100 0.80

95 0.75

90 0.70
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature(o C) Temperature(o C)

Figure 24. Over Temperature Protection Threshold

Figure 23. Internal Source Current of RT Pin
Voltage of RT Pin

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 15
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Functional Description
PFC Stage
Multi-Vector Error Amplifier and THD Optimizer
For better dynamic performance, faster transient
response, and precise clamping on PFC output,
FAN6921MR uses a trans-conductance type amplifier + 
with proprietary innovative multi-vector error amplifier
The schematic diagram of this amplifier is shown in +
Figure 25. The PFC output voltage is detected from the
INV pin by an external resistor divider circuit that
consists of R1 and R2. When PFC output variation
voltage reaches 6% over or under the reference voltage Figure 26. Multi-Vector Error Amplifier with
2.5 V, the multi-vector error amplifier adjusts its output THD Optimizer
sink or source current to increase the loop response to
simplify the compensated circuit.

Figure 25. Multi-Vector Error Amplifier

The feedback voltage signal on the INV pin is compared
with reference voltage 2.5 V, which makes the error Figure 27. Operation Waveforms of Fixed On-Time
amplifier source or sink current to charge or discharge with and without THD Optimizer
its output capacitor CCOMP. The COMP voltage is
compared with the internally generated sawtooth
waveform to determine the on-time of PFC gate.
Normally, with lower feedback loop bandwidth, the
variation of the PFC gate on-time should be very small
and almost constant within one input AC cycle.
However, the power factor correction circuit operating at
light load condition has a defect, zero crossing
distortion; which distorts input current and makes the
Current (A)

system’s Total Harmonic Distortion (THD) worse. To

improve the result of THD at light load condition,
especially at high input voltage, an innovative THD
Optimizer is inserted by sampling the voltage across the
current-sense resistor. This sampling voltage on
current-sense resistor is added into the sawtooth
waveform to modulate the on-time of PFC gate, so it is
not constant on-time within a half AC cycle. The method
of operation block between THD Optimizer and PWM
are shown in Figure 26. After THD Optimizer processes,
around the valley of AC input voltage, the compensated
on-time becomes wider than the original. The PFC on-
time, which is around the peak voltage, is narrowed by Figure 28. Calculated Waveforms of Fixed On-Time
the THD Optimizer. The timing sequences of the PFC with and without THD Optimizer During a Half
MOS and the shape of the inductor current are shown in AC Cycle
Figure 27. Figure 28 shows the difference between
calculated fixed on-time mechanism and fixed on-time
with THD Optimizer during a half AC cycle.

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 16
 FAN6921 — Integrated Critical Mode PFC/Quasi-Resonant Flyback PWM Controller
RANGE Pin
A built-in low voltage MOSFET can be turned on or off
according to VVIN voltage level. The drain pin of this
internal MOSFET is connected to the RANGE pin.
Figure 29 shows the status curve of VVIN voltage level
and RANGE impedance (open or ground).

Figure 29. Hysteresis Behavior between RANGE Pin

and VIN Pin Voltage
Zero Current Detection (ZCD Pin)
Figure 30 shows the internal block of zero-current
detection. The detection function is performed by
sensing the information on an auxiliary winding of the
PFC inductor. Referring to Figure 31, when PFC MOS is
off, the stored energy of the PFC inductor starts to Figure 31. Operation Waveforms of PFC Zero-
release to the output load. Then the drain voltage of Current Detection
PFC MOS starts to decrease since the PFC inductor
resonates with parasitic capacitance. Once the ZCD pin Protection for PFC Stage
voltage is lower than the triggering voltage (1.75V
PFC Output Voltage UVP and OVP (INV Pin)
typical), the PFC gate signal is sent again to start a new
switching cycle. FAN6921MR provides several kinds of protection for
If PFC operation needs to be shut down due to PFC stage. PFC output over- and under-voltage are
abnormal condition, it is suggested to pull the ZCD pin essential for PFC stage. Both are detected and
LOW, voltage under 0.2 V (typical), to activate the PFC determined by INV pin voltage, as shown in Figure 32.
disable function to stop PFC switching operation. When INV pin voltage is over 2.75 V or under 0.45 V,
due to overshoot or abnormal conditions and lasts for a
For preventing excessive high switching frequency at de-bounce time around 70 µs, the OVP or UVP circuit is
light load, a built-in inhibit timer is used to limit the activated to stop PFC switching operation immediately.
minimum tOFF time. Even if the ZCD signal has been
detected, the PFC gate signal still would not be sent The INV pin is not only used to receive and regulate
during the inhibit time (2.5 µs typical). PFC output voltage, but can also perform PFC output
OVP/ UVP protection. For failure-mode test, this pin can
shut down PFC switching if pin floating occurs.
1.4V
PFC VO
PFC Gate D eboun ce
D river
Drive Time
Q R
0.2V ZCD VREF (2.5V)
S V AC R1
5 COMP VCOMP
1.75V
RZCD INV
2 V oltage
CO
Lb 1
10V Error D etector
S
CCOMP R2
2.1V Amplifier
Q R PFC Gate On 1:n OVP = (VINV ≥ 2.75V)
FAN6921 UVP = (VINV ≤ 0.45V)
FAN6921

Figure 30. Internal Block of the Zero-Current

Detection Figure 32. Internal Block of PFC Over-and Under-
Voltage Protection

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 17
 FAN6921 — Integrated Critical Mode PFC/Quasi-Resonant Flyback PWM Controller
PFC Peak Current Limiting (CSPFC pin)
During PFC stage switching operation, the PFC switch
current is detected by current-sense resistor on the
CSPFC pin and the detected voltage on this resistor is
delivered to input terminal of a comparator and
compared with a threshold voltage 0.82 V (typical).
Once the CSPFC pin voltage is higher than the
threshold voltage, PFC gate is turned off immediately.
The PFC peak switching current is adjustable by the
current-sense resistor. Figure 33 shows the measured
waveform of PFC gate and CSPFC pin voltage.

PFC MOS Current Limit

0.82V
CSPFC

OPFC

Figure 33. Cycle-by-Cycle Current Limiting

Brown-In / Out Protection (VIN Pin) Figure 34. Operation Waveforms of Brown-In/ Out
With AC voltage detection, FAN6921MR can perform Protection
brown-in/ out protection (AC voltage UVP). Figure 34
shows the key operation waveforms of brown-in / out
protection. Both use the VIN pin to detect AC input
voltage level and the VIN pin is connected to AC input
by a resistor divider (refer to Figure 1); therefore, the VDD VDD Hiccup Mode
VVIN voltage is proportional to the AC input voltage.
When the AC voltage drops, and VVIN voltage is lower
than 1 V for 100 ms, the UVP protection is activated and
Brownout Brown-In
the COMP pin voltage is clamped to around 1.6 V.
Because PFC gate duty is determined by comparing
sawtooth waveform and COMP pin voltage, lower AC Input
COMP voltage results in narrow PFC on-time, so that
the energy converged is limited and the PFC output OPWM
voltage decreases. When INV pin is lower than 1.2 V,
FAN6921MR stops all PFC and PWM switching OPFC
operation immediately until VDD voltage drops to turn-off
voltage then raises to turn-on voltage again (UVLO).
When the brownout protection is activated, all switching
operation is turned off, VDD voltage enters hiccup mode
Figure 35. Measured Waveform of Brown-In/ Out
up and down continuously. Until VVIN voltage is higher
Protection (Adapter Application)
than 1.3 V (typical) and VDD reaches turn-on voltage
again, the PWM and PFC gate is sent out.
The measured waveforms of brown-in / out protection
are shown in Figure 35.

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 18
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
valley on the drain voltage of the PWM switch. When
PWM Stage the valley signal is detected, FAN6921MR outputs PWM
HV Startup and Operating Current (HV Pin) gate signal to turn on the switch and begin a new
The HV pin is connected to AC line through a resistor switching cycle.
(refer to Figure 1). With a built-in high-voltage startup With green mode operation and valley detection, at light
circuit, when AC voltage is applied to power system, load condition; power system can perform extended
FAN6921MR provides a high current to charge external valley switching at DCM operation and can further
VDD capacitor to speed up controller’s startup time and reduce switching loss for getting better conversion
build up normal rated output voltage within three efficiency. The FB pin voltage versus tOFF-MIN time
seconds. To save power consumption, after VDD voltage characteristic curve is shown in Figure 38. As Figure 38
exceeds turn-on voltage and enters normal operation; shows, FAN6921MR can narrow down to 2.25 ms tOFF
this high voltage startup circuit is shut down to avoid time, which is around 440 Hz switching frequency.
power loss from startup resistor.
Referring to Figure 1 and Figure 2, FB pin voltage is not
Figure 36 shows the characteristic curve of VDD voltage only used to receive secondary feedback signal to
and operating current IDD. When VDD voltage is lower determine gate on-time, but also determines PFC stage
than VDD-PWM-OFF, FAN6921MR stops all switching on or off status. At no-load or light-load conditions, if PFC
operation and turns off some internal unnecessary stage is set to be off; that can reduce power consumption
circuit to reduce operating current. By doing so, the from PFC stage switching device and increase
period from VDD-PWM-OFF to VDD-OFF can be extended and conversion efficiency. When output loading is decreased,
the hiccup mode frequency can be decreased to reduce the FB pin voltage becomes lower and, therefore, the
the input power in case of output short circuit. Figure 37 FAN6921MR can detect the output loading level
shows the typical waveforms of VDD voltage and gate according to the FB pin voltage to control the on / off
signal at hiccup mode operation. status of the PFC part.

tOFF-MIN
2.25ms

PFC On

PFC OFF
37µs V CTL-PFC-ON
V CTL-PFC-OFF
8µs

Figure 36. VDD vs. IDD-OP Characteristic Curve 1.15V(VG ) 2.1V(VN)

Figure 38. VFB Voltage vs. tOFF-MIN Time Characteristic

Curve
Valley Detection (DET Pin)
When FAN6921MR operates in green mode, tOFF-MIN
time is determined by the green mode circuit according
to FB pin voltage level. After tOFF-MIN time, the internal
valley detection circuit is activated. During the tOFF time
of PWM switch, when transformer inductor current
discharges to zero, the transformer inductor and
Figure 37. Typical Waveform of VDD Voltage and Gate parasitic capacitor of PWM switch start to resonate
Signal at Hiccup Mode Operation concurrently. When the drain voltage on the PWM
switch falls, the voltage across on auxiliary winding VAUX
Green-Mode Operation and PFC-ON / OFF Control also decreases since auxiliary winding is coupled to
(FB Pin) primary winding. Once the VAUX voltage resonates and
Green mode mechanism is used to further reduce falls to negative, VDET voltage is clamped by the DET pin
power loss in the system (e.g. switching loss). It uses an (refer to Figure 39) and FAN6921MR is forced to flow
off-time modulation technique to regulate switching out a current IDET. FAN6921MR reflects and compares
frequency according to FB pin voltage. When output this IDET current. If this source current rises to a
loading is decreased, FB voltage becomes lower due to threshold current, PWM gate signal is sent out after a
secondary feedback movement and the tOFF-MIN is fixed delay time (200 ns typical).
extended. After tOFF-MIN (determined by FB voltage), the
internal valley detection circuit is activated to detect the

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 19
 FAN6921 — Integrated Critical Mode PFC/Quasi-Resonant Flyback PWM Controller
Auxiliary As the input voltage increases, the reflected voltage on
Winding the auxiliary winding VAUX becomes higher as well as
the current IDET and the controller regulates the VLIMIT to
+ a lower level.
DET RDET
The RDET resistor is connected from auxiliary winding to
0.3V 10 VAUX the DET pin. Engineers can adjust this RDET resistor to
+
IDET RA get proper VLIMIT voltage to fit power system needs. The
VDET
- characteristic curve of IDET current vs. VLIMIT voltage on
CSPWM pin is shown in Figure 42.
FAN6921 -
I DET = VIN × ( N A NP )  RDET (1)
Figure 39. Valley Detection
where VIN is input voltage; NA is turn number of
auxiliary winding; and NP is turn number of primary
Start to Idet flow out
VAUX detect valley from DET pin winding.

0V
Delay time
and then
trigger Gate
VDET signal

Valley
Switching
0V
OPWM
tOFF

Figure 40. Measured Waveform of Valley Detection

High / Low Line Over-Power Compensation (DET Pin)
Generally, when the power switch turns off, there is a Figure 41. Relationship between VAUX and VIN
delay time from gate signal falling edge to power switch
off. This delay is produced by an internal propagation
delay of the controller and the turn-off delay time of
PWM switch due to gate resistor and gate-source
capacitor CISS of PWM switch. At different AC input
voltage, this delay time produces different maximum
output power under the same PWM current limit level.
Higher input voltage generates higher maximum output
power since applied voltage on primary winding is
higher and causes higher rising slope inductor current. It
results in higher peak inductor current at the same delay
time. Furthermore, under the same output wattage, the
peak switching current at high line is lower than that at
low line. Therefore, to make the maximum output power
close at different input voltages, the controller needs to
regulate VLIMIT voltage of the CSPWM pin to control the
PWM switch current.
Referring to Figure 41, during tON time of the PWM Figure 42. IDET Current vs. VLIMIT Voltage
switch, the input voltage is applied to primary winding Characteristic Curve
and the voltage across on auxiliary winding VAUX is
Leading-Edge Blanking (LEB)
proportional to primary winding voltage. So as the input
voltage increases, the reflected voltage on auxiliary When the PFC or PWM switches are turned on, a
winding VAUX becomes higher as well. FAN6921MR also voltage spike is induced on the current sense resistor
clamps the DET pin voltage and flows out a current IDET. due to the reciprocal effect by reverse recovery energy
Since the current IDET is in accordance with VAUX of the output diode and COSS of power MOSFET. To
voltage, FAN6921MR can depend on this current IDET prevent this spike, a leading-edge blanking time is built-
during tON time period to regulate the current limit level in to FAN6921MR and a small RC filter is also
of PWM switch to perform high / low line over-power recommended between the CSPWM pin and GND (e.g.
compensation. 100 Ω, 470 pF).

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 20
 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Protection for PWM Stage Output Over-Voltage Protection (DET Pin)
VDD Pin Over-Voltage Protection (OVP) Referring to Figure 44, during the discharge time of
PWM transformer inductor; the voltage across on
VDD over-voltage protection is used to prevent device
auxiliary winding is reflected from secondary winding
damage once VDD voltage is higher than device stress
and therefore the flat voltage on the DET pin is
rating voltage. In case of VDD OVP, the controller stops
proportional to the output voltage. FAN6921MR can
all switching operation immediately and enters latch-off
sample this flat voltage level after a tOFF blanking time to
mode until the AC plug is removed.
perform output over-voltage protection. This tOFF
Adjustable Over-Temperature Protection and blanking time is used to ignore the voltage ringing from
Externally Latch Triggering (RT Pin) leakage inductance of PWM transformer. The sampling
flat voltage level is compared with internal threshold
Figure 43 is a typical application circuit with an internal voltage 2.5 V and, once the protection is activated,
block of RT pin. As shown, a constant current IRT flows FAN6921MR enters latch mode.
out from the RT pin, so the voltage VRT on RT pin can
be obtained as IRT current multiplied by the resistor, The controller can protect rapidly by this kind of cycle-
which consists of NTC resistor and RA resistor. If the RT by-cycle sampling method in the case of output over
pin voltage is lower than 0.8 V and lasts for a de-bounce voltage. The protection voltage level can be determined
time, latch mode is activated and stops all PFC and by the ratio of external resistor divider RA and RDET. The
PWM switching. flat voltage on DET pin can be expressed by the
following equation:
RT pin is usually used to achieve over-temperature
protection with a NTC resistor and provides external RA
latch triggering for additional protection. Engineers can
VDET = ( N A N S ) × VO × (2)
RDET + RA
use an external triggering circuit (e.g. transistor) to pull
low the RT pin and activate controller latch mode.
Generally, the external latch triggering needs to activate
rapidly since it is usually used to protect power system
from abnormal conditions. Therefore, the protection
debounce time of the RT pin is set to around 110 µs
once RT pin voltage is lower than 0.5 V.
For over-temperature protection, because the
temperature would not change immediately; the RT pin
voltage is reduced slowly as well. The debounce time VO ⋅
NA
for adjustable OTP should not need a fast reaction. To NS
prevent improper latch triggering on the RT pin due to
exacting test condition (e.g. lightning test), when the RT
pin triggering voltage is higher than 0.5 V, the protection
debounce time is set to around 10 ms. To avoid
improper triggering on the RT pin, it is recommended to
add a small value capacitor (e.g. 1000 pF) paralleled
with NTC and RA resistor.
NA
PFC _ VO ⋅
FAN692 1 NP
Adjustable Over- NA RA
Temperature protection & VO ⋅ ⋅
External Latch triggering N S R DET + R A
I RT=100µA

12
Deboun ce
Latched
RT 0.8V time
NTC

R RT 0.5V 110µs
10ms

Figure 43. Adjustable Over-Temperature Protection

Figure 44. Operation Waveform of Output Over-
Voltage Detection

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 21
 FAN6921 — Integrated Critical Mode PFC/Quasi-Resonant Flyback PWM Controller
Open-Loop, Short-Circuit, and Overload Protection As the output loading is increased, the output voltage is
(FB Pin) decreased and the sink current of transistor of opto-
coupler on primary side is reduced. So the FB pin
voltage is increased by internal voltage bias. In the case
of an open loop, output short circuit, or overload
conditions, this sink current is further reduced and the
FB pin voltage is pulled to high level by internal bias
voltage. When the FB pin voltage is higher than 4.2 V
for 50 ms, the FB pin protection is activated.
Under-Voltage Lockout (UVLO, VDD Pin)
Referring to Figure 36 and Figure 37, the turn-on and
turn-off VDD threshold voltages of FAN6921MR are fixed
at 18 V and 10 V, respectively. During startup, the hold-
up capacitor (VDD cap.) is charged by HV startup current
until VDD voltage reaches the turn-on voltage. Before the
Figure 45. FB Pin Open-Loop, Short Circuit, and output voltage rises to rated voltage and delivers energy
Overload Protection to the VDD capacitor from auxiliary winding, this hold-up
capacitor has to sustain the VDD voltage energy for
Referring to Figure 45, outside of FAN6921MR, the FB operation. When VDD voltage reaches turn-on voltage,
pin is connected to the collector of transistor of an opto- FAN6921MR starts all switching operation if no
coupler. Inside of FAN6921MR, the FB pin is connected protection is triggered before VDD voltage drops to turn-
to an internal voltage bias through a resistor around off voltage VDD-PWM-OFF.
5 kΩ.

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6921MR Rev. 1.0.4 22
 10.00 A
9.80 8.89
8.89
16 9
B 1.75

6.00 4.00 3.85

3.80
7.35

1 0.51 8
PIN #1
1.27 0.31 1.27 0.65
(0.30)
0.25 C B A LAND PATTERN RECOMMENDATION
TOP VIEW

1.75 MAX
1.50 SEE DETAIL A
1.25 0.25
0.05
C
0.25
0.10 C 0.19
FRONT VIEW

NOTES:
0.50 A) THIS PACKAGE CONFORMS TO JEDEC
0.25
R0.10 GAGE PLANE MS-012, VARIATION AC, ISSUE C.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
R0.10 0.36 C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR PROTRUSIONS
D) CONFORMS TO ASME Y14.5M-2009
E) LANDPATTERN STANDARD:
0.90 SEATING PLANE
SOIC127P600X175-16AM
0.50 (1.04) F) DRAWING FILE NAME: M16AREV13.
DETAIL A
SCALE: 2:1
 TRADEMARKS
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intended to be an exhaustive list of all such trademarks.
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CTL ISOPLANAR Quiet Series TinyWire
Current Transfer Logic Making Small Speakers Sound Louder RapidConfigure TranSiC
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Datasheet contains the design specifications for product development. Specifications may change
Advance Information Formative / In Design
in any manner without notice.
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Preliminary First Production
Semiconductor reserves the right to make changes at any time without notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make
No Identification Needed Full Production
changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.
Obsolete Not In Production
The datasheet is for reference information only.
Rev. I77

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