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Eee421: Power Electronics: Power Semiconductor Devices: MOSFET

1) The MOSFET has become widely used in power electronics due to its high switching speeds and high input impedance as a voltage controlled device. 2) Power MOSFETs have a vertical double diffused structure (VDMOS) with p-well and n+ source diffused layers, and an n- epitaxial layer whose thickness determines the blocking voltage. 3) When a sufficiently large gate voltage is applied, a channel forms under the gate, allowing current to flow from the n- region through the channel and into the n+ source.

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0% found this document useful (0 votes)
79 views9 pages

Eee421: Power Electronics: Power Semiconductor Devices: MOSFET

1) The MOSFET has become widely used in power electronics due to its high switching speeds and high input impedance as a voltage controlled device. 2) Power MOSFETs have a vertical double diffused structure (VDMOS) with p-well and n+ source diffused layers, and an n- epitaxial layer whose thickness determines the blocking voltage. 3) When a sufficiently large gate voltage is applied, a channel forms under the gate, allowing current to flow from the n- region through the channel and into the n+ source.

Uploaded by

Rafat Shams
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EEE421: POWER ELECTRONICS

Lecture 4
Power Semiconductor
Devices: MOSFET
INTRODUCTION

Metal-oxide semiconductor field effect transistor


(MOSFET) has the attractive features of
being a voltage controlled device, having high input
impedance and being capable of switching at
high speeds, the MOSFET has revolutionized the IC
industry.
For power supply applications, the power MOSFET is
widely employed, which has characteristics similar to
that of a traditional MOSFET.
STRUCTURE OF POWER MOSFET

• The structure of power MOSFET is known as vertical


(source and drain on opposite sides)double
diffusion (VDMOS). The diffused layers are p-wwll
and n+ source.
• The size of the n- epitaxial layer depends on the
blocking voltage capability in reverse direction.
• A power MOSFET usually consists of multiple parallel-
connected cells.
PHYSICAL STRUCTURE OF
ENHANCEMENT TYPE POWER MOS
I-V CH.

When the potential at the gate


terminal is less than the threshold voltage,
the MOSFET remains off. Under this
condition, both the p-n+ and the p-n- regions
are reverse-biased. Any applied drain to-
source voltage VDS appears across the p-n-
region.

When a sufficiently large gate to-


source voltage, VGS, is applied, a channel is
formed at the surface of the p–region,
underneath the gate terminal. This channel
conducts current, leading to the flow of
electrons from the n- region, through the
channel, into the n+ source, and out of the
external source contacts.
IMPORTANT FEATURES

• A power MOSFET usually consists of multiple parallel-


connected cells. The source is constructed hos
many(thousands) small polygon shaped areas that
are connected in parallel and surrounded by gate
region. It maximize the width of the gate and gain
of the device.
• There is a parasitic npn BJT between drain to souce.
So the p type body region is shorted to source by
overlapping source metallization on to the p type
body. It creates a parasitic diode connected
between drain to source.
BODY DIODE

• It can be turned on when a negative voltage is


applied across the gate-to source terminal. While
the body diode is capable of conducting the full
rated current of the power MOSFET, it is not
optimized with respect to its switching speed. This
body diode can be used in half bridge and full
bridge converters.
• To overcome the drawback os body diode in high
speed operation many modern power MOSFETs are
designed with fast recovery body diodes.
DETAILED STRUCTURE
SWITCHING SPEED

The parasitic capacitances for the power MOSFET are


critical since it affects the switching characteristics
directly. A power MOSFET is a majority carrier device,
and hence minority charge carriers do not influence
the switching speeds. The switching characteristics of
such a device is determined based on the time
duration required to charge and discharge the
parasitic capacitances.

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