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Ejemplos VHDL Latch: Ieee Ieee STD - LOGIC - 1164

The document contains examples of VHDL code including latches, D flip-flops, 8-bit register using D flip-flops, ROM memory, RAM memory, 0-9 counter with reset and load, frequency division, and Mealy finite state machine. The examples demonstrate basic digital logic components and their implementation in VHDL including sequential and combinational logic, memory, counters, and finite state machines.

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Moriarty
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80 views

Ejemplos VHDL Latch: Ieee Ieee STD - LOGIC - 1164

The document contains examples of VHDL code including latches, D flip-flops, 8-bit register using D flip-flops, ROM memory, RAM memory, 0-9 counter with reset and load, frequency division, and Mealy finite state machine. The examples demonstrate basic digital logic components and their implementation in VHDL including sequential and combinational logic, memory, counters, and finite state machines.

Uploaded by

Moriarty
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Ejemplos VHDL

Latch

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity latch is
Port ( D, clk : IN STD_LOGIC;
Q : OUT STD_LOGIC);
end latch;

architecture Behavior of latch is


begin
process (D,clk)
begin

if clk='1'then
Q <= D;
end if;
end process;
end Behavior;

Biestable D

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity flipflop is
Port ( D, clk : IN STD_LOGIC;
Q : OUT STD_LOGIC);
end flipflop;

architecture Behavior of flipflop is


begin
process (clk)
begin

if (clk'event and clk='1') then


Q <= D;
end if;
end process;
end Behavior;

Registro de señal de 1 byte con biestables D

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity flipflop is
Port ( clk : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(7 downto 0);
Q : OUT STD_LOGIC(7 downto 0));
end flipflop;

architecture Behavior of flipflop is


begin
process (clk)
begin
if (clk'event and clk='1') then
Q <= D;
end if;
end process;
end Behavior;

Memoria ROM

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity myROM is
Port ( clk : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR(11 downto 0);
data_out : OUT STD_LOGIC VECTOR(7 downto 0));
end myROM;

architecture Behavior of myROM is


constant size : natural := 2**12;
type rom_type is array (size-1 downto 0) of std_logic_vector (7
downto 0);
constant mem : rom_type :=
(0=> x"aa", 1=> x"ee", 2 => x"77", 3 => x"01",
4=> x"a4", 5=> x"ff", 6 => x"22", 7 => x"f2",
8=> x"11", 9=> x"99", 10=> x"55", 11=> x"6666",
12=> "01011101",
13=> std_logic_vector(to_unsigned (1234,16)),
others => x"00");
begin
process (clk)
begin
if (clk'event and clk='1') then
data_out <= mem(to_integer(unsigned(address)));
end if;
end process;
end Behavior;

Memoria RAM

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity myRAM is
Port ( clk : IN STD_LOGIC;
we : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR(11 downto 0);
data_in : IN STD_LOGIC VECTOR(7 downto 0);
data_out : OUT STD_LOGIC VECTOR(7 downto 0));
end myROM;

architecture arch of myRAM is


constant size : natural := 2**12;
type ram_type is array (size-1 downto 0) of std_logic_vector (7
downto 0);
signal mem : ram_type;
signal read_address : std_logic_vector (11 downto 0);
begin
process (clk)
begin
if (clk'event and clk='1') then
if we='1' then
mem(to_integer(unsigned(address))) <= data_in;
end if;
read_address <= address;
end if;
end process;
data_out <=mem(to_integer(unsigned(read_address)));
end arch;

Contador de 0 a 9 con reset y carga de datos

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity contador is
port ( clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
load : IN STD_LOGIC;
data : IN STD_LOGIC VECTOR(3 downto 0);
cnt_out : OUT STD_LOGIC VECTOR(3 downto 0));
end contador;

architecture Behavioral of contador is


signal cnt_tmp : STD_LOGIC VECTOR(3 downto 0) := "0000";
begin
process (clk, reset, load, data)
begin
if reset = '1' then
cnt_tmp <= "0000";
elsif load ='1' then
cnt_tmp <= data;
elsif (clk'event and clk='1') then
if cnt_tmp = "1001" then
cnt_tmp <= "0000";
else
cnt_tmp <= cnt_tmp + 1;
end if;
end if;
end process;
cnt_out <= cnt_tmp;
end Behavioral;

División de frecuencia

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity div_clk is
port ( reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
clk_out : OUT STD_LOGIC);
end div_clk;

architecture arch of div_clk is


signal clk_cnt : unsigned(25 downto 0);
signal clk_bit : std_logic;

begin
gen_clock: process (clk, reset) is
begin
if (reset = '0') then
clk_cnt <= "00000000000000000000000000"; -- <= (others =>
'0')
clk_bit <= '0';
elsif (clk'event and clk='1') then
if (clk_cnt = 49999999) then
ck_cnt <= "00000000000000000000000000"; -- <= (others
=> '0')
clk_bit <= not clk_bit;
else
clk_cnt <= clk_cnt + 1;
end if;
end if;
end process;
clk_out <= clk_bit;
end arch;

Otro divisor de frecuencia

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity delay_clock is
port (
Clk50Mhz: in STD_LOGIC;
Clk: out STD_LOGIC
);
end delay_clock;

architecture arch of delay_clock is


constant max: INTEGER := 50000000;
constant half: INTEGER := max/2;
signal count: INTEGER range 0 to max;

begin
process
begin
wait until Clk50Mhz'event and Clk50Mhz = '1';
if count < max then
count <= count + 1;
else
count <= 0;
end if;

if count < half then


Clk <= '0';
else
Clk <= '1';
end if;
end process;
end arch;
Máquina de Estados tipo Mealy

library ieee;
use IEEE.std_logic_1164.all;

entity fsm_mealy is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic
);
end fsm_mealy;

architecture behavioral of fsm_mealy is

type state_type is (s0,s1,s2,s3); --Tipo Maquina de Estado


signal current_s,next_s: state_type; --Estado actual y proximo estado

begin

process (clk,reset)
begin
if (reset='1') then
current_s <= s0; --Estado inicial.
elsif (rising_edge(clk)) then --o elsif (clk'event and clk = '1')
then
current_s <= next_s; --Cambio de estado.
end if;
end process;

--Process de la Maquina de Estado.


process (current_s,input)
begin
case current_s is
when s0 => --Cuando el estado actual es "s0"
if(input ='0') then
output <= '0';
next_s <= s1;
else
output <= '1';
next_s <= s2;
end if;

when s1 =>; --Cuando el estado actual es "s1"


if(input ='0') then
output <= '0';
next_s <= s3;
else
output <= '0';
next_s <= s1;
end if;

when s2 => --Cuando el estado actual es "s2"


if(input ='0') then
output <= '1';
next_s <= s2;
else
output <= '0';
next_s <= s3;
end if;

when s3 => --Cuando el estado actual es "s3"


if(input ='0') then
output <= '1';
next_s <= s3;
else
output <= '1';
next_s <= s0;
end if;
end case;
end process;

end behavioral;

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