ITEC Asia-Pacific 2014 1569950487

Modeling of SiC MOSFET in Matlab/Simulink

Yang Cao, Liqiang Yuan, Kainan Chen, Zhengming Zhao, Ting Lu, Fanbo He
State Key Laboratory of Power System, Dept. of Electrical Engineering, Tsinghua Univ., Beijing, China

Abstract- New power semiconductor devices, such as SiC

MOSFET, have widely fascinated people in recent years. They
are playing more and more important roles in modern power
electronic converters. Most of current SiC MOSFET models are II. MODEL STRUCTURE
implemented in simple simulator, such as PSPICE, and have
A picture of CMF20120D CREE MOSFET and its internal
problems in some applications, for example, the accuracy of
these models can not satisfy the demand with the increasing of structure are given in Fig 2. The device has three terminals,
main circuit complexity. A novel model of SiC MOSFET gate, drain and source. There’s a highly doped N+ region
implemented in Matlab/Simulink is proposed in this paper, between the drain and the source so that more carriers can be
where its physical mechanism of the device is considered. Firstly provided. Also the vertical structure is used so that a higher
the model is established based on its static and transient
current can be achieved in on-state, as mentioned in [4, 5].
characteristics. Then the parameters in the model are extracted.
And finally simulation and experiment results are compared to
validate the model.
Keywords: SiC devices, modeling, Matlab/Simulink.

I. INTRODUCTION
Silicon power[1][1] semiconductor devices have been
widely used in power electronic converters. The
performances of silicon-based devices has been improving
over the last century. However, as the current technology is
reaching the theoretical limits of silicon, new semiconductor
devices such as silicon carbide (SiC) are being increasingly
fascinating to researchers. One of those devices that has been
used in industry is SiC MOSFET. More and more studies
have been conducted on SiC MOSFET models A classical
Fig. 1. A classical SiC MOSFET model
SiC MOSFET model was raised in [1], as is shown in fig.1.
This model is a scripture in simulation of SiC MOSFET and
is widely used. Some effective improvements are proposed in
[2]. However, the existing models are mostly implemented in
PSPICE and have usability problems in some cases, as
mentioned in [3]. Those problems can be well solved in
Matlab/Simulink. So a novel MOSFET model in
Matlab/Simulink should be researched. This paper proposes a
model for the commercial SiC MOSFET CMF20120D(1200
V/33 A) from CREE and simulation results are achieved via
Matlab/Simulink. Firstly the model is established based on its
static and transient characteristics. Then the parameters in the
model are extracted. Finally both the simulation and the
experiment results are compared to validate the model.

Supported by the National High Technology Research and Development

Program of China (863 Program, No. 2011AA050402 ) and by the Program
Fig. 2. Commercial SiC MOSFET and its internal structure
of State Key Laboratory of Power System in Tsinghua University
(SKLD13M09).

1
 References [6, 7] demonstrate the turn-on principle of a
MOSFET. When Vds is positive and Vgs goes up gradually, the
MOSFET experiences 3 stages before it is on.
Stage (1): when Vgs just begins to rise, holes below the
silicon dioxide layer are pushed off by the electric field
generated by Vgs and result in a depletion layer.
Vgs Vds
Stage (2): Vgs keep rising, the depletion layer turns to
inversion layer, which means the carriers in this region are
electronics but not holes in the previous. But there are too few
of them to form a circuit.
State (3): Vgs rises to a voltage that is higher than the turn-
on voltage(VT) and the number of electronics in the inversion
Matlab S-function
layer is big enough to form a circuit from drain to source, or
Id. Channel emerges in the P semiconductor below the
insulation layer. The higher Vgs is, the wider the channel is Calculation result
and the better its conductivity is.
In a SiC MOSFET, the PN junction is charged under a
reverse voltage and can be equivalent to a capacitance. The
barrier capacitance effect is the charging effect caused by the
VCCS
change of width of space-charge region when the voltage
over PN junction changes. The change of voltage over PN Current signal
junction causes movement of majority carrier in both N
region and P region, which is equivalent to a charging process
to a capacitance at the PN junction. The barrier capacitance
parameters are related to the frequency and amplitude of the
external voltage; The diffusion capacitance effect is caused
by the time delay of electronic mobility. When PN junction is Fig. 3. Static model process
offset positively, electronics enter N region from P region to
combine with the holes. But the combinations couldn’t
complete immediately, for the electronics need to diffuse in P
region, which causes accumulation of electronics in the
diffusion region. Obviously the accumulation is related with
the circuit through the junction. The larger the circuit is, the
more electronics are accumulated. This process is also like a
charging process in a capacitance, so it is defined as diffusion
capacitance. These parasitics capacitances have obvious
impact on transient performance. References [8-10] state the
impact specifically.
Based on the principles above, static and transient models
are established.
The static model describes the U-I characteristics in on-
state. On-state current is determined by Vgs as well as Vds . Fig. 4. Transient model of SiC MOSFET
The model is built up via Matlab/Simulink by solving on-
state function in a S-function. Vgs and Vds are the inputs of the III. PARAMETER EXTRACTION
function. Then the calculation result is delivered to a VCCS,
where a current signal is produced. This process is shown in In the formal section, the SiC MOSFET model based on
Fig 3. Matlab/Simulink has been attained. In this section, the
Then gate driver, stray inductance, base resistance and parameters in the model are extracted.
parasitics capacitances are added to the external circuit of the In the static model, output current Id is described as the
static model to establish a transient model, as depicted in Fig formula below, mentioned in [11].
4.
In this model, Cgd, Cgs and Cds are respectively gate-to- ⎧ 0, U GS < U T
⎪
drain, gate-to-source and drain-to-source capacitances I D = ⎨ K p (U GS − U T − U DS / 2)U DS ,U GS ≥ U T ,U DS < U GS − U T
respectively. Ld is the stray inductance inside the device, ⎪ K p (U GS − U T ) 2 / 2,U GS ≥ U T ,U DS ≥ U GS − U T
⎩
while Rds is the stray resistance of the base.

2
 The static model describes the U-I characteristics when v. Internal inductance Ls
MOSFET is in static state. The output I is determined by Vgs This parameter can be estimated from the overshoot of the
as well as VP, as described in the formul. UT and KP are given voltage waveforms in the progress of switching on and off. In
parameters in the model. Using the least square method to this paper, Ls =20mH.
extract them.
In this model, UT=2.122V, KP =0.745. IV. SIMULATION AND EXPERIMENT RESULTS
The parameters in the transient model are also extracted,
listed in Table1. Firstly the on-state characteristics of the SiC MOSFET are
tested using a SONY 371A instrument. The U-I curves are
Table. 1. Parameters in the transient model drawn and compared with the simulation results. Fig 5 a)
Parameter Symbol Unit Value shows the test curves of the commercial SiC MOSFET
External stray inductance Ls nH 90
CMF20120D（1200 V/33 A）from CREE. It can be seen
External stray resistance Rs Ω 3
Resistance of diode Rdiode Ω 0.2 that the function in the formula mentioned above fits the
Parasitic capacitance of diode Cdiode pF 70 experiment static characteristics well.
Gate-to-source capacitance Cgs pF 1902
Drain-to-source capacitance Cds pF 40
Gate-to-drain capacitance Cgd pF 70
Internal inductance of the device Ld nH 20

It is crucial for the validity of the model that the parameters

in the circuit are reasonably decided. In this paper, those
parameters are decided by the following principles:
i. External stray inductance Ls :
For an inductance, it is known that its voltage and current
can be described by

According to this law, the experimental di⁄dt is firstly a)

abstracted, secondly the experimental ∆V is obtained. Finally
Ls is estimated with the two parameters. In this paper, Ls
=70mH.
ii. Oscillation resistance Rs and on-resistance of diode
Rdiode
These two parameters can be estimated by the number the
waveform oscillate in a single switch and the oscillation time.
In this paper, Rs =3Ω, Rdiode =0.2Ω.
iii. Capacitance inside diode, Cdiode
According to [12], the frequency of oscillation in a single
switch is determined by

Therefore Cdiode can be estimated using the experimental b)

oscillation frequency and the estimated Ls. In this paper Cdiode Fig. 5. Comparison of simulation and experiment results of V-A
=70pF . characteristic
iv. Cds, Cgs and Cgd
Those capacitance parameters inside the SiC MOSFET Then a test circuit is designed to validate the established
could be obtained from the datasheet. In this paper, Cds model, as shown in Fig 6. Four waveforms are observed as
=40pF, Cgs =1902pF , Cgd =70pF . indicated by the numbers in the circuit, namely Vds , Vgs , Id
and Vload .

3
 700

600

500

400

Voltage (V)
VDSexp
300
VDSsim
200

100

-100
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (μs)
a)
30
a)
25

20

Current (A) 15

10

b) 0 IDexp
Fig. 6. Test circuit of the established model (a: equivalent circuit b: IDsim
PCB) -5
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (μs)
The parameters in the test circuit are given in table2. b)
Fig. 7. Turn-on waveforms (a: voltage waveform b: current waveform)
Table. 2. Parameters in the test circuit
Name of the Numerical value or detailed 800
parameters information
SiC MOSFET CMF20120D 700

SiC SBD C4D30120D

Lload 1.296mH 600

Rload 1Ω，100W 500

Voltage (V)

Internal resistance of Lload 0.93Ω

400

Also, simulation results are obtained at a bus voltage of 300

VDSexp
600V and a load current of 20A. The simulation and the 200 VDSsim
experiment are compared in Fig. 7 and Fig. 8.
It can be seen that the simulation waveforms are very 100

similar to the experimental waveforms, in peak voltage, peak 0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
current, rise/fall time and the oscillation. It concludes that the Time (μs)
established model has a good performance. a)

4
 [9]. Liu Ping, et al., Impact of nonlinear output capacitance of a MOSFET
to oscillation frequency, Microcomputer information
25 2007(29):Page258-259. 刘平等, MOSFET 输出电容的非线性对振荡
频率的影响. 微计算机信息, 2007(29): 第 258-259 页.
[10]. Bakowski, M., Status and prospects of SiC power devices. IEEJ
20 Transactions on Industry Applications, 2006. 126: p. 391-399.
[11]. Funaki, T., et al. Characterization of SiC JFET for temperature
dependent device modeling. in Power Electronics Specialists
15
Conference, 2006. PESC'06. 37th IEEE. 2006: IEEE.
Current (A)

[12]. Wang, R., et al. Transformer-isolated gate drive design for SiC JFET
IDexp
10 phase-leg module. in Energy Conversion Congress and Exposition
IDsim (ECCE), 2011 IEEE. 2011: IEEE.

-5
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (μs)

b)
Fig. 8. Turn-off waveforms (a: voltage waveform b: current
waveform)

V. CONCLUSIONS
As the existing models for SiC MOSFET are mostly in
PSPICE and have problems in some applications, this paper
presents a model for the high-voltage SiC MOSFET in
Matlab/Simulink. To validate the model, a buck circuit is
designed and the transient experiment results of the SiC
MOSFET are obtained. The comparison results show that the
established model can well describe the performance of the
SiC MOSFET in its dynamic transient.

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