SDRAM 64Mb H-die (x32) CMOS SDRAM

64Mb H-die (x32) SDRAM Specification

Revision 1.3
February 2004

*Samsung Electronics reserves the right to change products or specification without notice.

-1- Rev. 1.3 February. 2004

SDRAM 64Mb H-die (x32) CMOS SDRAM
Revision History
Revision 0.0 (June, 2003)
- Target spec First release.

Revision 0.1 (July, 2003)

- Delete speed 4.5ns.

Revision 0.2 (September, 2003)

- Preliminary spec release.

Revision 1.0 (November, 2003)

- Final spec release.

Revision 1.1 (December, 2003)

- Corrected typo.

Revision 1.2 (December, 2003)

- Modified load cap 50pF -> 30pF & Typo.

Revision 1.3 (February, 2004)

- Corrected typo.

-2- Rev. 1.3 February. 2004

SDRAM 64Mb H-die (x32) CMOS SDRAM

512K x 32Bit x 4 Banks SDRAM

FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period(4K Cycle)

GENERAL DESCRIPTION
The K4S643232H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated
with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock.
I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable
latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Ordering Information
Part No. Orgainization Max Freq. Interface Package
K4S643232H-TC/L70 143MHz(CL=3)
K4S643232H-TC/L60 166MHz(CL=3)
512K x 32 LVTTL 86pin TSOP(II)
K4S643232H-TC/L55 183MHz(CL=3)
K4S643232H-TC/L50 200MHz(CL=3)

Organization Row Address Column Address

2Mx32 A0~A10 A0-A7

Row & Column address configuration

-3- Rev. 1.3 February. 2004

SDRAM 64Mb H-die (x32) CMOS SDRAM

Package Physical Dimension

0~8°C
0.25
TYP
#86 #44 0.010

0.018~0.030
0.463±0.008
11.76±0.20

0.45~0.75
0.400
10.16
#1 #43

( 0.50 )
0.125+0.075

0.020
-0.035

22.62 0.005+0.003
-0.001
MAX
0.891
22.22 ± 0.10 0.21 ± 0.05 1.00 ± 0.10 1.20
0.875 ± 0.004 ± 0.002 ± 0.004
MAX
0.008 0.039 0.047

0.10
MAX
0.004 0.05
+0.07
0.61 0.20 -0.03 0.50 MIN
( ) 0.002
0.024 0.0079 +0.003
-0.001
0.0197

86Pin TSOP(II) Package Dimension

-4- Rev. 1.3 February. 2004

SDRAM 64Mb H-die (x32) CMOS SDRAM

FUNCTIONAL BLOCK DIAGRAM

I/O Control
LWE
Data Input Register
LDQM
Bank Select

512K x 32
Refresh Counter

Output Buffer
Row Decoder

Sense AMP
Row Buffer

512K x 32
DQi
Address Register

512K x 32
CLK
512K x 32

ADD
Column Decoder
LRAS
LCBR

Col. Buffer

Latency & Burst Length

LCKE
Programming Register
LRAS LCBR LWE LCAS LWCBR LDQM

Timing Register

CLK CKE CS RAS CAS WE DQM

-5- Rev. 1.3 February. 2004

SDRAM 64Mb H-die (x32) CMOS SDRAM
PIN CONFIGURATION (Top view)

VDD 1 86 VSS
DQ0 2 85 DQ15
VDDQ 3 84 VSSQ
DQ1 4 83 DQ14
DQ2 5 82 DQ13
VSSQ 6 81 VDDQ
DQ3 7 80 DQ12
DQ4 8 79 DQ11
VDDQ 9 78 VSSQ
DQ5 10 77 DQ10
DQ6 11 76 DQ9
VSSQ 12 75 VDDQ
DQ7 13 74 DQ8
N.C 14 73 N.C
VDD 15 72 VSS
DQM0 16 71 DQM1
WE 17 70 N.C
CAS 18 69 N.C
RAS 19 68 CLK
CS 20 67 CKE
N.C 21 66 A9
BA0 22 65 A8
BA1 23 64 A7
A10/AP 24 63 A6
A0 25 62 A5
A1 26 61 A4
A2 27 60 A3
DQM2 28 59 DQM3
VDD 29 58 VSS
N.C 30 57 N.C
DQ16 31 56 DQ31
VSSQ 32 55 VDDQ
DQ17 33 54 DQ30
DQ18 34 53 DQ29
VDDQ 35 52 VSSQ
DQ19 36 51 DQ28
DQ20 37 50 DQ27
VSSQ 38 49 VDDQ
DQ21 39 48 DQ26
DQ22 40 47 DQ25
VDDQ 41 46 VSSQ
DQ23 42 45 DQ24
VDD 43 44 VSS 86Pin TSOP (II)
(400mil x 875mil)
(0.5 mm Pin pitch)

-6- Rev. 1.3 February. 2004

SDRAM 64Mb H-die (x32) CMOS SDRAM
PIN FUNCTION DESCRIPTION
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CS Chip select
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE Clock enable CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
Row/column addresses are multiplexed on the same pins.
A0 ~ A10 Address
Row address : RA0 ~ RA10, Column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
BA0,1 Bank select address
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
RAS Row address strobe
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
CAS Column address strobe
Enables column access.
Enables write operation and row precharge.
WE Write enable
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
DQM0 ~ 3 Data input/output mask
Blocks data input when DQM active.
DQ0 ~ 31 Data input/output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
VDDQ/VSSQ Data output power/ground
immunity.
NC No Connection This pin is recommended to be left No connection on the device.

-7- Rev. 1.3 February. 2004

SDRAM 64Mb H-die (x32) CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 1 W
Short circuit current IOS 50 mA

Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter Symbol Min Typ Max Unit Note

Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high voltage VIH 2.0 3.0 VDDQ+0.3 V 1
Input logic low voltage VIL -0.3 0 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH = -2mA
Output logic low voltage VOL - - 0.4 V IOL = 2mA
Input leakage current ILI -10 - 10 uA 3

Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)

Pin Symbol Min Max Unit

Clock CCLK - 4 pF
RAS, CAS, WE, CS, CKE, DQM CIN - 4.5 pF
Address CADD - 4.5 pF
DQ0 ~ DQ31 COUT - 6.5 pF

-8- Rev. 1.3 February. 2004

SDRAM 64Mb H-die (x32) CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C

CAS Speed
Parameter Symbol Test Condition Unit Note
Latency 50 55 60 70
3 140 140 130 130
Operating Current Burst Length =1
ICC1 tRC ≥ tRC(min), tCC ≥ tCC(min), Io = 0mA
mA 2
(One Bank Active)
2 110

Precharge Standby Current in ICC2P CKE ≤ VIL(max), tCC = 10ns 2

mA
power-down mode
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 2

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

ICC2N 12
Input signals are changed one time during 30ns
Precharge Standby Current
mA
in non power-down mode
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC2NS 7
Input signals are stable

Active Standby Current ICC3P CKE ≤ VIL(max), tCC = 10ns 4

mA
in power-down mode
ICC3PS CKE ≤ VIL(max), tCC = ∞ 4

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

ICC3N 40
Active Standby Current Input signals are changed one time during 30ns
in non power-down mode mA
(One Bank Active) CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC3NS 35
Input signals are stable

Operating Current Io = 0 mA, Page Burst 3 170 160 150 140

ICC4 mA 2
(Burst Mode) All bank Activated, tCCD = tCCD(min) 2 120

3 150 150 140 120

Refresh Current ICC5 tRC ≥ tRC(min) mA 3
2 120

C 2 mA 4
Self Refresh Current ICC6 CKE ≤ 0.2V
L 450 uA 5

Notes : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

2. Measured with outputs open.
3. Refresh period is 64ms.
4. K4S643232H-TC
5. K4S643232H-TL

-9- Rev. 1.3 February. 2004

SDRAM 64Mb H-die (x32) CMOS SDRAM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter Value Unit
AC input levels (Vih/Vil) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2

3.3V Vtt = 1.4V

1200Ω 50Ω
VOH (DC) = 2.4V, IOH = -2mA
Output Output Z0 = 50Ω
VOL (DC) = 0.4V, IOL = 2mA
30pF 30pF
870Ω

(Fig. 1) DC output load circuit (Fig. 2) AC output load circuit

OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter Symbol Unit Note
50 55 60 70
Row active to row active delay tRRD(min) 2 CLK 1
RAS to CAS delay tRCD(min) 3 2 3 2 3 2 3 2 CLK 1
Row precharge time tRP(min) 3 2 3 2 3 2 3 2 CLK 1
tRAS(min) 8 5 7 5 7 5 7 5 CLK 1
Row active time
tRAS(max) 100 us
Row cycle time tRC(min) 11 7 10 7 10 7 10 7 CLK 1
Last data in to row precharge tRDL(min) 2 CLK 2
Last data in to new col.address delay tCDL(min) 1 CLK 2
Last data in to burst stop tBDL(min) 1 CLK 2
Col. address to col. address delay tCCD(min) 1 CLK 3
Mode Register Set cycle time tMRS(min) 2 CLK
Number of valid CAS Latency=3 2
ea 4
output data CAS Latency=2 1

Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.

- 10 Rev. 1.3 February. 2004

SDRAM 64Mb H-die (x32) CMOS SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
50 55 60 70
Parameter Symbol Unit Note
Min Max Min Max Min Max Min Max
CAS Latency=3 5 5.5 6 7
CLK cycle time tCC 1000 1000 1000 1000 ns 1
CAS Latency=2 10 10 10 10

CLK to valid CAS Latency=3 - 4.5 - 5.0 - 5.5 - 5.5

tSAC ns 1, 2
output delay CAS Latency=2 - 6 - 6 - 6 - 6
Output data hold time tOH 2 - 2 - 2 - 2 - ns 2

CLK high pulse CAS Latency=3 2 - 2 - 2.5 - 3 -

tCH ns 3
width CAS Latency=2 3 - 3 - 3 - 3 -

CLK low CAS Latency=3 2 - 2 - 2.5 - 3 -

tCL ns 3
pulse width CAS Latency=2 3 - 3 - 3 - 3 -
CAS Latency=3 1.5 - 1.5 - 1.5 - 1.75 -
Input setup time tSS ns 3
CAS Latency=2 2.5 - 2.5 - 2.5 - 2.5 -
Input hold time tSH 1 - 1 - 1 - 1 - ns 3
CLK to output in Low-Z tSLZ 1 - 1 - 1 - 1 - ns 2

CLK to output CAS latency=3 - 4.5 - 5.0 - 5.5 - 5.5

tSHZ ns -
in Hi-Z CAS latency=2 - 6 - 6 - 6 - 6

Note : 1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.

- 11 Rev. 1.3 February. 2004

SDRAM 64Mb H-die (x32) CMOS SDRAM
SIMPLIFIED TRUTH TABLE
Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A11, Note
A9 ~ A 0

Register Mode register set H X L L L L X OP code 1,2

Auto refresh H 3
H L L L H X X
Entry L 3
Refresh Self
refresh L H H H 3
Exit L H X X
H X X X 3
Bank active & row addr. H X L L H H X V Row address
Read & Auto precharge disable L Column 4
column address H X L H L H X V address
Auto precharge enable H 4,5
Write & Auto precharge disable L Column 4
column address H X L H L L X V address
Auto precharge enable H 4,5
Burst Stop H X L H H L X X 6
Bank selection V L
Precharge H X L L H L X X
All banks X H
H X X X
Clock suspend or Entry H L X
L V V V X
active power down
Exit L H X X X X X
H X X X
Entry H L X
L H H H
Precharge power down mode X
H X X X
Exit L H X
L V V V
DQM H X V X 7
H X X X
No operation command H X X X
L H H H
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Notes :1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

- 12 Rev. 1.3 February. 2004