Technology@Tdzire
February 15, 2013 • 1 Comment
What Is A Non-Unate Timing Path ?
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A cell is said to have non-unate behaviour, when it propagates both senses (positive or
negative) of the input signal. This is very critical, when you have this signal as clock. Consider a
buffer in the clock tree. The timing analysis tool is sure that, it can propagate the same sense to
output as the input. In case of an inverter in the clock tree, the output will get inverted. Here
also we tell that it is unate. Non-unate behaviour comes in complex combinational cells like
XOR/XNOR etc.
Imagine an XOR gate in the clock path. XOR is having two inputs – A and S.
Output Z = A’S + AS’
Here suppose S is the clock signal, A is some data/enable signal. Z can get S or S’ based on the
logic values of A. ie, The output can get an inverted clock, if A = 1 or a non-inverted clock, if A =
0. Thus when we do timing analysis, were A is not set to any value, the tool propagates both the
senses to the XOR output. Hence we tell that XOR is having a non-unate behaviour.
What issue we face if non-unate path is there ? If by design, the XOR can invert or non invert the
clock, there is no issue. But in most designs, this won’t happen. There will be a specific logic
value for the A input which gets propagated from top hierarchy. So unneccessarily we will end
up, analysing and fixing the timing paths, with both inverted and non-inverted clocks.
How to solve the non-unate behaviour ? Provide appropriate case value to the other inputs, so
that correct unateness of the clock can get propagated.
In Primetime, we get a message PTE-012 for the non-unate paths during update timing. It is
always good to correct this and proceed to the final Timing analysis stage.
Application Form Asic
Behaviour Buffers Cell
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