SECTION H Arithm<ric l.

ocic Shifr Unlr 119

PROBllMS

4-1. Show the block diag,am of the hardware (similar to Fig. 4-2a) that imple­
ments the following register transfer statement

4-1. The outputs of four reg;sters, RO, RI, R2, and R3, are connected through
4-to-1-line multiplexers to the inputs of a filth reg;ster, R5. Each register is
eight bits long. The required transfers are dictated by four timing variables
To through T, as foUows:

To: R5<-RO
T,: R5-Rl
T,: R5-R2
T,: R5 ... R3

The timing variables are mutually e><clusive, which means that only one
variable is equal to I at any given lime, while the other three are equal to
0. Draw • block diagram showing the han:lware Implementation of the
register transfers. Include the con.nection5 neae-,y from the four timing
variables to the selection inputs of the multiplexers and to the load input of
reg;ster R5.
4-3. Represent the following oonditional c:ontTOl &tlt,ement by two reglsttt tm\5-
fer statements with control functions.

If (P • I) then (Rt -RZ) else if (Q • I) then (RI -R3)

4-4. What has to be done 10 the bus system cl Fig. 4-3 to be able to transf,er
In.formation from any register to any other regi.st,er? Specifically, show the
connections that must be Included to provide a path from the outputs cl
register C to the Inputs of register A.
4-5. Draw a diagram of a bu.I system simlla, to the one shown In Fig. 4-3, but use
th,...,.state buffers and a deaxler Instead cl the multiplexen.
U. A digital oomputer has a oommon bus system for 16 regist,,rs of 32 bits each.
The bus Is constructed with multiplexers.
a. How many selection Inputs are there in each multiplexer?
b. What sl,.e of multiplexers are needed?
c. How many multiplexers are there in the bus?
4-7. The foUowing transfer statements specify a memory. Explain the memory
operation in each case.
a. R2+-M(AR]
b. M(AR]<-R3
c. RS <-M(RS]
120 CHAPTER FOUR Register Transfer and Microoperations

4-8. Draw the block diagram for the hardware that implements the following
statements:
x + yz: AR+--AR + BR

where AR and BR are two n-bit registers andx1 y1 and z are control variables.
Include the logic gates for the control function. (Remember that the sym­
bol+designates an OR operation in a control or Boolean function but that
it represents an arithmetic plus in a microoperation.)
4-9. Show the hardware that implements the following statement. Include the
logic gates for the control function and a block diagram for the binary counter
with a count enable input.

ryT,+ T, +y'T2 : AR+--AR+ 1

4-10. Consider the following register transfer statements for two 4-bit registers Rl
and R2.
xT: Rl+--Rl+R2
x'T: Rl+--R2

Every time that variable T = 1, either the content of R2 is added to the

content of Rl ifx = 1, or the content of R2 is transferred to Rl if x = 0. Draw
a diagram showing the hardware implementation of the two statements. Use
block diagrams for the two 4-bit registers, a 4-bit adder, and a quadruple
2-to-1-line multiplexer that selects the inputs to Rl. In the diagram, show
how the control variables x and T select the inputs of the multiplexer and
the load input of register Rl.
4-11. Using a 4-bit counter with parallel load as in Fig. 2-11 and a 4-bit adder as
in Fig. 4-6, draw a block diagram that shows how to implement the following
statements:

x: Rl+--Rl+R2 Add R2 to Rl
x'y: Rl+--Rl+ 1 Increment R1

where Rl is a counter with parallel load and R2 is a 4-bit register.

4-12. The adder-subtractor cirruit of Fig. 4-7 has the following values for input
mode Mand data inputs A and B. In each case, determine the values of the
outputs: S31 S2, S 1 , S01 and C4.

M A B
a. 0 0111 0110
b. 0 1000 1001

..
c. 1 1100 1000
d. 1 0101 1010
0000 0001
 SECTION 4-7 Arithmetic Logic Shift Unit 121

4-13. Design a 4-bit combinational circuit decrementer using four full-adder cir­
cuits.
4-14. Assume that the 4-bit arithmetic circuit of Fig. 4-9 is enclosed in one IC
package. Show the connections among two such !Cs to form an 8-bit arith­
metic circuit.
4-15. Design an arithmetic circuit with one selection variable Sand two n-bit data
inputs A and B. The circuit generates the following four arithmetic opera­
tions in conjunction with the input carry Cln- Draw the logic diagram for the
first two stages.

s
0 D =A+ B (add) D = A + 1 (increment)
D = A - 1 (decrement) D = A + lf + 1 (subtract)

4-16. Derive a combinational circuit that selects and generates any of the 16 logic
functions listed in Table 4-5.
4-17. Design a digital circuit that performs the four logic operations of exclusive­
OR, exclusive-NOR, NOR, and NAND. Use two selection variables. Show
the logic diagram of one typical stage.
4-18. Register A holds the 8-bit binary 11011001. Determine the B operand and the
logic microoperation to be performed in order to change the value in A to:
•- 01101101
b. 11111101
4-19. The 8-bit registers AR, BR, CR, and DR initially have the following values:

AR 11110010
BR 11111111
CR 10111001
DR 11101010

Determine the 8-bit values in each register after the execution of the follow­
ing sequence of microoperations.

AR<--AR + BR Add BR to AR
CR<--CR I\ DR, BR<--BR + 1 AND DR to CR, increment BR
AR<--AR - CR Subtract CR from AR

4-20. An 8-bit register contains the binary value 10011100. What is the register
value after an arithmetic shift right? Starting from the initial number
10011100, determine the register value after an arithmetic shift left, and state
whether there is an overflow.
4-21. Starting from an initial value of R = 11011101, determine the sequence of
binary values in R after a logical shift-left, followed by a circular shift-right,
followed by a logical shift-right and a circular shift-left.
 SECTION S-10 O..iin d. Accumularor J..ocic 167

full-adder with the corresponding input and output carries. The transfer from
INPR to AC is only for bits O through 7. The complement miaooperation is
obtained by inverting the bit value in AC. The shift-right operation transfers
the bit from AC(i + 1), and the shift-left operation transfers the bit from
AC(i - 1). The complete adder and logic circuit consists of 16 stages connected
together.

PROBLEMS

S-1. A computer uses a memory unit with 2.56K wonls of 32 bits each. A binary
instruction code is stored in one won! of memory. The instruction has four
parts: an indirect bit, an operation code, • register code part to specify one
of 64 n,gisters, and an address part.
a. How many bits are there in the operation code, the register code part,
and the address part?
b. Draw the instruction word format and indiate the number of bilS in each
part.
c. How many bits are there in the data and address inputs of the memory?
S-2. What is the difference between a direct and an indirect address instruction?
How many references to memory are needed for each type of instruction to
bring an operand into a p10C1!SS0r n,gistet?
5--3. The following control lnpulS are active In the bus system shown In Fig. 5-4,
For each case, spedly the register transfer that-will be executed during the
next dock tn,nsition.

s, S, So LO o( regis1er Memory Adder

a. I I I JR Read
b. I I 0 PC
C. l 0 0 DR Write
d. 0 0 0 AC Add

5-4. The following register transfe.n..,.. to be executed in the system of Fig. 5-4.
For each transfer, specify: (I) the bina ry value that mu.,t be applied to bus
s
select inputs ,, 5,, and So; (2) the register whose LD conlJOI in.put must be
active (If a.ny): (3) a memory read or write operation (if needed); and (4) the
operation in the adder and logic citcuit (if any�
a. AR<-PC
b. IR-M(AR)
c. M(AR].-TR
d. AC -DR, DR <--AC (done simultaneously)
S-5. Explain why each of the following rnicrooperations cannot be executed