Scribd
Upload
93 views5 pages

VD - Lab 5 Assignment

This document contains the lab assignment questions and solutions for a CMOS inverter circuit design and analysis. It includes: 1) Designing a CMOS inverter circuit to meet delay constraints and verifying the design matches theoretical delay calculations. 2) Computing output voltages for 3 NMOS transistors connected in series under different input conditions and verifying results match theory. 3) The document contains the questions, design calculations, SPICE codes used, output waveforms, and conclusions drawing comparisons between theoretical and simulated results.

Uploaded by

Kunal Katariya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
93 views5 pages

VD - Lab 5 Assignment

This document contains the lab assignment questions and solutions for a CMOS inverter circuit design and analysis. It includes: 1) Designing a CMOS inverter circuit to meet delay constraints and verifying the design matches theoretical delay calculations. 2) Computing output voltages for 3 NMOS transistors connected in series under different input conditions and verifying results match theory. 3) The document contains the questions, design calculations, SPICE codes used, output waveforms, and conclusions drawing comparisons between theoretical and simulated results.

Uploaded by

Kunal Katariya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

U17EC133 – Kunal Katariya

Lab 5 Assignment
Date: 09/09/2020

Ques 1: Design CMOS inverter circuit which satisfies given delay constraints. Design the
circuits and verify your design for 1μ technology using a suitable WINSPICE code.

VDD = 5V CLOAD = 200pF VTON = |VTOP| = 0.8V


TpHL ≤ 5.86 μS ; TpLH ≤ 4.14
UNCOX = 40uA/V2 UPCOX = 20uA/V2
μS

Calculations:

Code:
*CMOS inverter transient analysis
.model nmos NMOS vt0=0.8 kp=40u
.model pmos PMOS vt0=-0.8 kp=20u
M1 out in 1 1 pmos w=0.74715u l=1u
M2 out in 0 0 nmos w=0.2634u l=1u
C 0 out 200pf
U17EC133 – Kunal Katariya

Vdd 1 0 dc 5v
Vin in 0 0 pulse (0 5 0.8u 0.8u 0.8u 100u 200u)
.tran 0.1u 800u
.control
run
plot V(out) V(in)
.endc
.end

Output:

Observations:

Theoretical Values Practical Values


Parameters
(uS) (uS)
TPHL 5.86 5.75
TPLH 4.14 4.12
TP 5 4.935

Conclusion:
Hence we performed the transient analysis for the given inverter circuit and computed the
values of Tphl and Tplh. Also, we verified the values from theoretical computation done using
average current method. We found out the high to low value to be greater than the low to high
value leading us to the conclusion that the switching rate of pull-down network is faster than the
pull up network due to the strong pull-down effect of NMOS.
U17EC133 – Kunal Katariya

Ques 2: By writing WINSPICE code compute the voltages Vx, Vy and Vz, in each of the
following cases. Assume Vt,n=1 V.

Calculations:
U17EC133 – Kunal Katariya

Code:
*Case 1
.model nmos NMOS VT0=1
M1 1 1 x 0 nmos W=1u L=1u
M2 x 1 y 0 nmos W=1u L=1u
M3 y 1 z 0 nmos W=1u L=1u
Vin1 1 0 5v
.tran 0.1u 800u
.control
Run
plot v(x) v(y) v(z)
.endc
.end

*Case2
.model nmos NMOS vt0=1V
M1 1 1 x 0 nmos w=1u l=1u
M2 x 2 y 0 nmos w=1u l=1u
M3 y 1 z 0 nmos w=1u l=1u
Vin1 1 0 dc 5v
Vin2 2 0 dc 3V
.tran 0.1u 800u
.control
run
plot v(x) v(y) v(z)
.endc
.end
U17EC133 – Kunal Katariya

*Case 3
.model nmos NMOS vt0=1V
M1 1 1 x 0 nmos w=1u l=1u
M2 x 2 y 0 nmos w=1u l=1u
M3 y 2 z 0 nmos w=1u l=1u
Vin1 1 0 dc 5v
Vin2 2 0 dc 3v
.tran 0.1u 800u
.control
run
plot v(x) v(y) v(z)
.endc
.end

Observations:
Vx Vx Vy Vy Vz Vz
Case
(Theoretical) (Practical) (Theoretical) (Practical) (Theoretica) (Practical)
1 4 3.996 4 3.985 4 3.980
2 4 3.991 2 1.998 2 1.988
3 4 3.989 2 1.996 2 1.985

Conclusion:
Hence, we wrote a code for computing the output missing voltages of 3 NMOS individually
connected in series manner and verified the values from theoretical calculations.

You might also like