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com
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[email protected],
[email protected],
[email protected] Subject Fw : Re: AFE7900 RF frontend enabling low power higher integration designs
Date 07 Oct 2020 11:11:52 AM
Please forward to the team members for study.
From: "Poshala Purnachandar" <[email protected]> MailId : [76089395]
To: "
[email protected]" <
[email protected]>
Cc: "Agarwal,Mohit" <
[email protected]>,"Rajan,Selva Kumaran" <
[email protected]>
Subject: Re: AFE7900 RF frontend enabling low power higher integration designs
Date: 05 Oct 2020 05:15:17 PM
Madam,
Resending again. Please confirm once received.
Purna.
From: Purnachandar Poshala <purnachandar@ .com>
Date: Saturday, 3 October 2020 at 11:41 PM
To: "
[email protected]" <
[email protected]>
Cc: Mohit Agarwal <mohitagarwal@ .com>, Selva hyderabad <selva@ .com>
Subject: AFE7900 RF frontend enabling low power higher integra on designs
Dear Madam,
Hope you are doing great. I would like to share about one of our new part AFE7900 which can be used for VHF/UHF, L Band, S
band, C band and X band applica ons for both Transmi er and Receiver.
Please find the key details of AFE7900. I would like to present about this part to HAL teams over WebEx call for all the teams
reference and for any use case for the new designs.
Configura on: 4 Channel Tx and 4 Channel Rx (+ 2 addi onal Rx) (4 DACs, 6 ADCs)
MAX sample rate:
DACs: 12 GSPS
ADCs: 3 GSPS
Digital Step A enuators
TX: 40 dB range, 1 dB analog steps, 0.125 dB digital steps
RX: 25 dB range, 0.5 dB Steps
DAC/ADC Sample Rate Ra os: 2, 3, 4, 6
RF Frequency Range: 30MHz – 12GHz
Maximum Signal bandwidth:
4TX/2FB: 1200MHz/2T: 2400MHz
4RX (no FB): 1200MHz BW
4RX (with x2 FB): 600 MHz BW
Digital Features:
RX DDC: dual DDC with complex decima on
TX DUC: dual DUC with complex interpola on
Single DUC/DDC mode: 16x NCOs with phase coherence and fast hopping
Dual DUC/DDC mode: 2x NCOs with phase coherence and fast hopping
Interface:
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10/8/2020 hal-india.com User : [email protected]
8 Serdes TRX
Up to 29.5 Gbps
25 dB loss tolerance bump to bump
8b/10b or 64b/66b encoding: JESD204B/C
SYSREF Alignment Detector
Op onal Internal PLL/VCO to generate DAC/ADC clocks (op onal ext. ADC clock)
Package: 17x17 mm, flip-chip BGA, 0.8mm pitch
Power Supplies: +1.8V, +1.2V and +0.9V
Warm Regards,
Purna Chandar Poshala
Field Applica ons Manager – South India
Mobile: +91-8105000442
Do not Remove:
[HID]20201005171517623[-HID]
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