DEM 2020 Midsem Makeup Answer Key
Section A
1. BCD code of 8723 1000 0111 0010 0011
2. F = ∑m(2,4,10,12,13,15) + ∑d(1,6,11,14)
3. 5 x2= 10
4. A 10 kHz square wave
5. 20ns X 5= 100ns
6. 1
Section B
7. Initial data 1011
Serial data 101111
After I shift 1101
After 2 shift 1110
After 3shift 1111
After 4 shift 1111
After 5 shift 0111
After 6 shift 1011
B’
8.
0 OR
1 0 Y
S0
9. The range of 10 bit signed system is -512 to + 511.
Overflow occurs when result >511 ( greater than Max)and
Underflow when result < -512 ( less than min)
a) -266 + 502 ( no overflow or underflow , result is within the range )
In fact no overflow or underflow can occur when a positive and negative
Number gets added .
b) -300 – 408 ( here the underflow will occur)
Student has to represent the decimal numbers into binary or hexadecimal
And perform the operation and need to show that the overflow or underflow is
detected.
10. From the excitation table of TFF , and state table of Jk FF it can be shown that
T = F(J, K, Qn) and by Kmap simplification ( 3 variable kmap) it can be shown to be
T= Jq’ + Kq.
11. The signal lines A,B,C can be treated as the output of the respective lock system , which
Is set to 1 only when the correct key is placed in to the respective lock system.
And the output Z = F(A,B,C ) given by Truth table.
A B CZ
0 0 00
001 0
010 0
011 1
100 0
101 1
110 1
111 1
Z= ∑(3,5,6,7 )
And reduction by Kmap gives the minimum sop solution for Z= AB +BC + CA
12 . reduce by 4 variable Kmap to get the minimum pos. Two quads will be present
F= (A+D).(C+D) .
Section C
13. input clock frequency 80 Mhz.
desired output frequency = 1/50 ns = 20 Mhz . hence scaling by 4.
so a two Flip flop cascaded system can do the scaling .
two Jk FF with J’s and K’s connected to Logic 1 , and the external clk feeded to the clk input
of the LSB FF , and the output (A) of the LSB FF is connected to the clk input of the next FF.
The output B of the second FF will have a frequency scaled by 4 to get 20 Mhz.
Ofcourse any FF can be used for scaling . If it is T FF, then both the T inputs are to be Logic 1.
and if it is D ff , then respective Q’ to be connected to D input. The idea is to have the flip flop
to have the toggle state, so that every clock edge makes the Flip flop output to alternate
between 0 and 1 .
14. a) the logic diagram is a straightforward one , ( just place some combinational block whose
output will feed to Ja, Ka, Jb,Kb ). The accuracy is to be noted 1 mark.
b) the state equations for state variables A and B are
A+ = Ja A’ + Ka’A which will simplify to
A+ = (Bx + B’Y’)A’ + (B+x’ + y).A
A+ = A’Bx + A’B’y’ +AB + Ax’ + Ay
similarly for B+ = A’xB’ + A’x’B + A’yB. correct equation gets 1 mark
c) state table will be as follows
A B x y A+ B+
Where in for each of the l 16 combinations of input variables , need to compute A + and B+
the correct state table can be awarded 2 mark
15. The truth table showing the input 4 bit Gray code and the output 4 bit Binary code should
be shown explicitly. It is a 4 input 4 output combinational system.
For correct truth table , step mark 1 can be awarded.
The input variables can be A B C D , and the output variables can be W ,X, Y, Z.
It can be shown after Kmap reduction ( 4 variable Kmap ) that
W=A
X= A © B where © is the Xor operator.
Y= A©B©C
Z= A©B©C©D. correct solution is 3 marks if Kmaps reduction are shown explicitly
