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Chaogates: Morphing logic gates that exploit dynamical patterns

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 CHAOS 20, 037107 共2010兲

Chaogates: Morphing logic gates that exploit dynamical patterns

William L. Ditto,1 A. Miliotis,2 K. Murali,3 Sudeshna Sinha,4,a兲 and Mark L. Spano5
1
Harrington Department of Bioengineering, Arizona State University, Tempe, Arizona 85287-9309, USA
2
J. Crayton Pruitt Family Department of Biomedical Engineering, University of Florida,
Gainesville, Florida 32611-6131, USA
3
Department of Physics, Anna University, Chennai 600 025, India
4
Indian Institute of Science Education and Research (IISER), Mohali, Transit Campus, MGSIPAP Complex,
Sector 26, Chandigarh 160 019, India
5
NSWC, Carderock Laboratory, W. Bethesda, Maryland 20817, USA
共Received 18 July 2010; accepted 25 August 2010; published online 28 September 2010兲

Chaotic systems can yield a wide variety of patterns. Here we use this feature to generate all
possible fundamental logic gate functions. This forms the basis of the design of a dynamical
computing device, a chaogate, that can be rapidly morphed to become any desired logic gate. Here
we review the basic concepts underlying this and present an extension of the formalism to include
asymmetric logic functions. © 2010 American Institute of Physics. 关doi:10.1063/1.3489889兴

The patterns of chaos are used to encode and to manipu- sequent years there has been much research activity to ex-
late inputs so as to produce a desired output. This is ac- tend this paradigm.1–17
complished by selecting out desired patterns from the in- One of the most promising directions of this computing
finite variety offered by a chaotic system. A subset of paradigm is its ability to reconfigure a single chaotic element
these patterns is then used to map the system inputs (or as different logic gates.2,3 In contrast to a conventional field
initial conditions) to the desired outputs. So this process programmable gate array element,18 where reconfiguration is
offers a method to exploit the richness inherent in non- achieved by switching between multiple single-purpose
linear dynamics in order to design computing devices
gates, reconfigurable chaotic logic gates 共RCLGs兲 are com-
with the capacity to reconfigure into a range of logic
prised of chaotic elements that morph 共or reconfigure兲
gates. The resultant morphing gates are termed cha-
ogates. Arrays of such morphing chaotic logic gates can through the control of the pattern inherent in their constitu-
then be programmed to perform higher order functions tive nonlinear element. Two input RCLGs have recently been
and to rapidly switch between such functions. So this ca- built and shown to be capable of reconfiguring between all
pacity for reconfigurability will conceivably give us the logic gates in discrete circuitry.4–6 Additionally such RCLGs
flexibility of programmable hardware, as well as enable have been realized in prototype very large scale integrated
us to obtain the optimization and speed of application circuits 共VLSI兲 关0.13 ␮m complementary metal-oxide-
specific hardware, within the same computer architec- semiconductor 共CMOS兲, 30 MHz clock cycles兴. Further, re-
ture. Here we briefly review the basic tenets of this com- configurable chaotic logic gate arrays, which morph between
puting paradigm and also provide extensions of the idea higher order functions such as those found in a typical arith-
to obtain asymmetric logic gates. metic logic unit 共ALU兲, have also been designed.17 Thus
architectures based on such logic implementations may serve
as ingredients of a general-purpose reconfigurable computing
I. INTRODUCTION
device more powerful and more fault tolerant10 than stati-
Chaotic systems are renowned for the richness of their cally wired hardware.
dynamics. Whether one describes this richness as a sensitiv- In the following we present the basic concepts underly-
ity to perturbations or as a amalgamation of an infinite num- ing chaos computing and describe methods to design nonlin-
ber of instabilities, even low-dimensional chaotic systems ear systems to flexibly yield all fundamental logic functions
can express a stunning variety of different behaviors as a by “programming” different dynamical systems. We show
function of time, of their initial conditions, or of their param- that the patterns produced by varying the initial conditions
eters. and the parameters of a chaotic system, as well as the pat-
Here we review an emerging computing paradigm which terns produced by its time evolution, are amenable to per-
exploits this pattern generating ability of chaotic dynamics. forming computation. By combining both techniques, one
In 1998 it was noted that chaotic systems may be utilized to can produce a computational device of immense power and
design computing devices.1 In the early years the focus was elegance.
on proof-of-principle schemes that demonstrated the capabil- The outline of this article is as follows. In Sec. II we first
ity of chaotic elements to do universal computing.19 In sub- recall the implementation of all fundamental logical opera-
tions by a threshold control mechanism.2 In Sec. III we de-
a兲
On leave from The Institute of Mathematical Sciences, CIT Campus, Tara- scribe the use of time evolution of the nonlinear system to
mani, Chennai 600113, India. obtain a wide range of logic responses. In Secs. IV and V we

1054-1500/2010/20共3兲/037107/7/$30.00 20, 037107-1 © 2010 American Institute of Physics

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 037107-2 Ditto et al. Chaos 20, 037107 共2010兲

TABLE I. Truth table of the basic logic operations for a pair of inputs: TABLE II. Necessary and sufficient conditions, derived from the logic truth
I1 , I2 共Ref. 19兲. The one-input NOT gate is given by NOT共0兲 is 1; NOT共1兲 tables, to be satisfied simultaneously by the nonlinear dynamical element, in
is 0. order for it to have the capacity to implement the logical operations AND,
OR, XOR, NAND, NOR, and NOT 共cf. Table I兲 with the same chaogate.
I1 I2 NAND NOR XOR AND OR XNOR
Logic Input set Necessary and sufficient
0 0 1 1 0 0 0 1 operation 共I1 , I2兲 Output condition
1 0 1 0 1 0 1 0
0 1 1 0 1 0 1 0 AND 共0,0兲 0 f共xAND兲 ⬍ xⴱ
1 1 0 0 0 1 1 1 共0,1兲/共1,0兲 0 f共xAND + ␦兲 ⬍ xⴱ
共1,1兲 1 f共xAND + 2␦兲 ⱖ xⴱ
OR 共0,0兲 0 f共xOR兲 ⬍ xⴱ
共0,1兲/共1,0兲 1 f共xOR + ␦兲 ⱖ xⴱ
共1,1兲 1 f共xOR + 2␦兲 ⱖ xⴱ
introduce a more general formalism, capable of implement- XOR 共0,0兲 0 f共xXOR兲 ⬍ xⴱ
ing asymmetric operations that distinguish between the in- 共0,1兲/共1,0兲 1 f共xXOR + ␦兲 ⱖ xⴱ
puts, thus extending the earlier formalism for symmetric 共1,1兲 0 f共xXOR + 2␦兲 ⬍ xⴱ
gates. We conclude in Sec. VI with a brief discussion of NOR 共0,0兲 1 f共xNOR兲 ⱖ xⴱ
some on-going technological implementations of these ideas, 共0,1兲/共1,0兲 0 f共xNOR + ␦兲 ⬍ xⴱ
共1,1兲 0 f共xNOR + 2␦兲 ⬍ xⴱ
specifically, a VSLI implementation of chaotic computing in
NAND 共0,0兲 1 f共xNAND兲 ⱖ xⴱ
a demonstration integrated circuit chip.
共0,1兲/共1,0兲 1 f共xNAND + ␦兲 ⱖ xⴱ
共1,1兲 0 f共xNAND + 2␦兲 ⬍ xⴱ

II. GENERAL CONCEPT

The cornerstone of modern computer architecture is bi- 共3兲 Determining the output:
nary digital logic, the logic of the true and the false. Boolean
Logic output is 0 if f共x0兲 ⱕ xⴱ
logic is remarkable for its conceptual simplicity. For in-
stance, it can be rigorously shown that any logic operation and
can be realized by adequate connection of NOR and NAND
gates 共i.e., any Boolean circuit can be built using NOR/ Logic output is 1 if f共x0兲 ⬎ xⴱ ,
NAND gates alone兲. This implies that the capacity for uni- where xⴱ is a prescribed reference threshold.
versal computing can be proven by the implementation of the
fundamental NOR and NAND gates.19 Since the system is strongly nonlinear, in order to
We outline below a theoretical method for obtaining all specify the initial x0 accurately, one needs a control mecha-
basic logic gates with a single nonlinear system. The broad nism, here a threshold controller20,21 to set the initial x0.
aim here is to use, in a controlled manner, the rich temporal In order to obtain all the desired input-output responses
patterns comprising a nonlinear time series in order to obtain of the different gates we need to satisfy the conditions enu-
a computing device that is flexible and reconfigurable. merated in Table I simultaneously. So given a dynamics f共x兲
Consider the chaotic chip or chaotic processor to be a one must find values of the threshold and initial state satis-
one-dimensional system, whose state is represented by x, and fying the conditions derived from the truth tables 共see
whose dynamics is given by a nonlinear map f共x兲. Table II兲.
In our scheme all the basic two-input logic gate opera- A representative example is given in Table III, showing
tions 共NAND, NOR, XOR, AND, OR, and XNOR兲 involve the exact solutions for xgate and the threshold xⴱ that satisfy
the following steps: the conditions in Table II when the dynamical evolution is
governed by the logistic equation,
共1兲 The logic inputs I1 and I2 for two-input logic operations
共see Table I兲 are encoded by the initial state x0 of the f共x兲 = ax共1 − x兲.
system as follows:
Here we choose the nonlinearity parameter a = 4 and constant
␦ = 41 common to all the logic gates.
x0 → xgate + X1 + X2 , This is the essence of chaos computing: for the chaotic
where the physical quantity X1共X2兲 共which could be, for system of interest, one looks for sets of initial conditions and
instance, a voltage兲 has value 0 when logic input I1共I2兲 is
0, and has value ␦ when logic input I1共I2兲 is 1, with ␦ TABLE III. One specific set of solutions of the conditions in Table II which
being a positive constant. Like X1 and X2, xgate is also a yield the logical operations AND, OR, XOR, and NAND with ␦ = 4 . Note
1

physical entity, such as a voltage, which can be varied to that these theoretical solutions have been fully verified in a discrete electri-
yield different logic outputs. cal circuit implementing a logistic map 共Ref. 4兲.
共2兲 Dynamical evolution over n time steps, resulting in the
Operation AND OR XOR NAND
updated state x → f n共x0兲, namely, the nth iterate of the xgate 0 1/8 1/4 3/8
initial state. Specifically we take n = 1 here, i.e., xⴱ 3/4 11/16 3/4 11/16
x = f 1共x0兲 ⬅ f共x0兲.

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 037107-3 Chaogates: Morphing logic gates Chaos 20, 037107 共2010兲

TABLE IV. Necessary and sufficient conditions to be satisfied by a nonlinear system in order to implement the
logical operations NAND, AND, NOR, XOR, and OR at different iterations.

Logic NAND AND NOR XOR OR

Iteration n 1 2 3 4 5
Input 共0,0兲 x1 = f共x0兲 ⬎ xⴱ f共x1兲 ⬍ xⴱ f共x2兲 ⬎ xⴱ f共x3兲 ⬍ xⴱ f共x4兲 ⬍ xⴱ
Input 共0,1兲/共1,0兲 x1 = f共x0 + ␦兲 ⬎ xⴱ f共x1兲 ⬍ xⴱ f共x2兲 ⬍ xⴱ f共x3兲 ⬎ xⴱ f共x4兲 ⬎ xⴱ
Input 共1,1兲 x1 = f共x0 + 2␦兲 ⬍ xⴱ f共x1兲 ⬎ xⴱ f共x2兲 ⬍ xⴱ f共x3兲 ⬍ xⴱ f共x4兲 ⬎ xⴱ

system parameters that produce a result corresponding to a employed to obtain the desired input-output mapping. It may
desired mathematical or logical operation. A given set of happen that certain nonlinear systems will allow a wide
parameters may produce a result that is their logical OR of range of logic responses without actually being chaotic.
the inputs or the logical AND. These parameters can be Proof-of-principle experiments with electronic circuits
stored and used as a ready “look-up table” for future com- have rigorously verified the above concept.4,5 Also note that
putations using this system. Other combinations of inputs the generalization of this concept, described explicitly for
and parameters might lead to results that do not produce a two-input gates here, is easily extended to multiple input
mathematical or logical result. Those initial conditions are gates.14 These morphing multiple input gates would make
discarded. So setting the parameters to be the ones that gave chaogate-based computing machines more power efficient,
the desired functional temporal patterns constitutes program- and would also serve to increase their performance and to
ming of the system to give the right output. widen their range of applications.
Note that it is possible to implement the concept with Lastly contrast this to a conventional field programmable
any 共typical兲 nonlinear function, and there are proof-of- gate array element,18 where reconfiguration is achieved
principle realizations of chaos computing using circuits through switching between multiple single purpose gates,
implementing several different nonlinear maps. For instance, rather than using a single element to perform many different
in Ref. 12 two coupled complementary 共n-channel and logic functions. This latter is expected to be faster and less
p-channel兲 junction field-effect transistors efficiently imple- wasteful of space on an integrated circuit.
ment a nonlinear function of the form xn+1 = 2xn / 共1 + x10 n 兲,
which is then used for chaos computing.
Contrast this use of nonlinear elements here with the III. LOGIC FROM NONLINEAR EVOLUTION:
possible use of linear systems on one hand, and stochastic DYNAMICAL LOGIC OUTPUTS
systems on the other. It is not possible to extract all the
different logic responses from the same element in the case Now we describe a method for obtaining a logic output
of linear components since the temporal patterns are inher- from a nonlinear system using the time evolution of the state
ently very limited. So linear elements do not offer much of the system. This concept uses the nonlinear characteris-
flexibility or versatility. Stochastic elements, on the other tics of the time dependence of the state of the dynamical
hand, have many different temporal sequences. But they are system to elicit different responses from the system. The
not deterministic and so one cannot use them to design com- highlight of this method is that a single system can perform
ponents. Only nonlinear dynamical systems enjoy both rich- complicated logic operations very efficiently.
ness of temporal behavior as well as determinism. We extend the concept in Sec. II by allowing our system
Also note that, while nonlinearity is absolutely necessary to evolve further in time. In doing so we might find that the
for implementing all the logic gates, chaos may not be al- system can perform an AND operation on its first iteration,
ways be necessary. In the representative example of the lo- but a NOR operation on the next iteration, etc. Thus we hope
gistic map presented in Table III solutions for all the gates to perform a sequence of mathematical or logical operations
exist only in the limit of a = 4 when the chaotic attractor almost as easily as a single operation.
covers the entire interval. The degree and form of nonlinear- As before encode the inputs via the initial state: x → x0
ity necessary for obtaining all the desired logic responses + X1 + X2, for two-input logic operations, with X = 0 when
will depend on the system at hand and on the specific scheme logic input I = 0 and X = ␦ 共with ␦ ⬎ 0兲 when logic input I = 1.

TABLE V. Updated state of chaotic logistic map satisfying the conditions in Table IV in order to implement the
logical operations NAND, AND, NOR, XOR, and OR during different iterations with x0 = 0.325, ␦ = 4 , and
1

ⴱ
x = 0.6.

Operation NAND AND NOR XOR OR

Iteration n 1 2 3 4 5
State of the system 共xn兲 x1 x2 x3 x4 x5
Logic input 共0,0兲 x0 = 0.325 0.88 0.43 0.98 0.08 0.28
Logic input 共0,1兲/共1,0兲 x0 = 0.575 0.9775 0.088 0.33 0.872 0.45
Logic input 共1,1兲 x0 = 0.825 0.58 0.98 0.1 0.34 0.9

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 037107-4 Ditto et al. Chaos 20, 037107 共2010兲

method allows combinational logic to be obtained very effi-

ciently with fewer computational modules and no cascading.

IV. ASYMMETRIC INPUTS

Now we describe an extension of the above formalism to

FIG. 1. 共Color online兲 Template showing different logic patterns for the include asymmetric logic operations. In this method the in-
range of x0 共0–0.5兲 vs iteration number n 共0 ⬍ n ⱕ 10兲. Here xⴱ = 0.75 for
puts I1 and I2 of a two-input logic operation are encoded as
1 ⱕ n ⱕ 4 and xⴱ = 0.4 for n ⬎ 4. ␦ is fixed at 0.25 共Ref. 12兲.
follows:

After evolution over n time steps we determine the out- x0 = xgate + X1 + X2 ,

put using the condition: if f n共x兲 ⱕ xⴱ then logic output is 0, where xgate is “programmable” to yield different logic func-
and if f n共x兲 ⬎ xⴱ then logic output is 1, where xⴱ is a refer- tion types.
ence threshold. With no loss of generality we follow the scheme:
The principal difference from the earlier approach is the
following: here we vary the time evolution n to obtain dif- • X1 = 0 when I1 = 0 and X1 = ␦ when I1 = 1.
ferent logic relations: i.e., n is “programmed” to yield differ- • X2 = 0 when I2 = 0 and X2 = 2␦ when I2 = 1,
ent logic. Unlike the earlier idea where n was held constant where ␦ is some positive constant.
共at n = 1 specifically兲 and xgate was tuned to obtain different
logic gate behavior, here we tap the state of the system at a Consider four distinct situations:
longer time n to construct various logic combinations. Case 1: Both I1 and I2 are 0 共row 1 in Table I兲, i.e., the
So the inputs set up the initial state of the nonlinear initial state of the system is x0 = xgate + 0 + 0 = xgate.
system: x0 + I1 + I2. Then the system evolves over n iterative Case 2: I1 = 1, I2 = 0 共row 2 in Table I兲, i.e., the initial
time steps to the final state xn. The evolved state is compared state is x0 = xgate + ␦ + 0 = xgate + ␦.
to a monitoring threshold xⴱ If the state is greater than the Case 3: I1 = 0 , I2 = 1 共row 3 in Table I兲, i.e., the initial
threshold, a logical 1 is the output and, if the state is less than state is x0 = xgate + 0 + 2␦ = xgate + 2␦.
the threshold, a logical 0 is the output 共Table IV兲. This pro- Case 4: Both I1 and I2 are 1 共row 4 in Table I兲, i.e., the
cess is repeated for subsequent iterations 共see Fig. 1 and initial state is x0 = xgate + ␦ + 2␦ = xgate + 3␦.
Table V for an example兲. This encoding of the inputs is capable of distinguishing
between the input sets 共0,1兲 and 共1,0兲 and therefore can treat
asymmetric logic functions correctly.
A. Implementation of half- and full-adder operations
As before, the evolved state x1 = f共x0兲 yields the logic
Combinational logic can also be implemented directly output as described before: logic output= 0 if f共x0兲 ⱕ xⴱ, logic
by the above method. For instance, the ubiquitous bit-by-bit output= 1 if f共x0兲 ⬎ xⴱ. Here the value of x0 共equal to xgate
arithmetic addition 共half-adder兲 involves two logic gate out- + I1 + I2兲 is determined by the input set, and varying xgate can
puts: AND 共to obtain the carry兲 and XOR 共to obtain first digit select out different logic functions.
of the sum兲. Using the scheme above we can obtain this The basic logic gates, which are symmetric 关with input
combinational operation in consecutive iterations, with a set 共0,1兲 being equivalent to 共1,0兲兴, can be obtained as a
single one-dimensional chaotic element. specific case of this general formalism. For instance, in order
Further, the typical full-adder requires two half-adder to obtain all the desired input-output responses of the gates
circuits and an extra OR gate. So in total, the implementation displayed in Table I, we need to satisfy the conditions enu-
of a full-adder requires five different gates 共two XOR gates, merated in Table VI simultaneously. That is, given a dynam-
two AND gates, and one OR gate兲. However, using the dy- ics f共x兲, one must find values of threshold xⴱ, constant ␦, and
namical evolution of a single logistic map, we require only initial state x0 that satisfy the conditions derived from the
three iterations to implement the full-adder circuit. So this truth table to be implemented.

TABLE VI. Necessary and sufficient conditions to be satisfied by a nonlinear system in order to implement the
logical operations AND, OR, XOR, NAND, and NOR consistently on all possible input sets. Considering a = 4
in the logistic map function, iteration n = 1, threshold level xⴱ = 0.95, and ␦ = 0.1, solutions of xgate satisfying the
above conditions simultaneously are 0.1, 0.3, 0.35, 0.4, and 0.6, respectively, for AND, OR, XOR, NAND, and
NOR logic operations.

Inputs AND OR XOR NAND NOR

ⴱ ⴱ ⴱ ⴱ
共0,0兲 f共xgate兲 ⱕ x f共xgate兲 ⱕ x f共xgate兲 ⱕ x f共xgate兲 ⬎ x f共xgate兲 ⬎ xⴱ
共0,1兲 f共xgate + ␦兲 ⱕ xⴱ f共xgate + ␦兲 ⬎ xⴱ f共xgate + ␦兲 ⬎ xⴱ f共xgate + ␦兲 ⬎ xⴱ f共xgate + ␦兲 ⱕ xⴱ
共1,0兲 f共xgate + 2␦兲 ⱕ xⴱ f共xgate + 2␦兲 ⬎ xⴱ f共xgate + 2␦兲 ⬎ xⴱ f共xgate + 2␦兲 ⬎ xⴱ f共xgate + 2␦兲 ⱕ xⴱ
共1,1兲 f共xgate + 3␦兲 ⬎ xⴱ f共xgate + 3␦兲 ⬎ xⴱ f共xgate + 3␦兲 ⱕ xⴱ f共xgate + 3␦兲 ⱕ xⴱ f共xgate + 3␦兲 ⱕ xⴱ

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 037107-5 Chaogates: Morphing logic gates Chaos 20, 037107 共2010兲

TABLE VII. Necessary and sufficient conditions to be satisfied by a nonlinear system in order to implement the
logical operations AND, XOR, OR, NAND, XNOR, and NOR, with n being the number of evolution steps. For
example, when a = 4, xⴱ = 0.5, and ␦ = 1, x0 = 0.005, 0.05, 0.75, 0.3, 0.425, and 0.5 yield AND, XOR, OR, NAND,
XNOR, and NOR logic operations, respectively.

Inputs n AND XOR OR NAND XNOR NOR

共0,0兲 1 x1 = f共x0兲 ⱕ xⴱ x1 = f共x0兲 ⱕ xⴱ x1 = f共x0兲 ⱕ xⴱ x1 = f共x0兲 ⬎ xⴱ x1 = f共x0兲 ⬎ xⴱ x1 = f共x0兲 ⬎ xⴱ

共0,1兲 2 x2 = f共x1兲 ⱕ xⴱ x2 = f共x1兲 ⬎ xⴱ x2 = f共x1兲 ⬎ xⴱ x2 = f共x1兲 ⬎ xⴱ x2 = f共x1兲 ⱕ xⴱ x2 = f共x1兲 ⱕ xⴱ
共1,0兲 3 x3 = f共x2兲 ⱕ xⴱ x3 = f共x2兲 ⬎ xⴱ x3 = f共x2兲 ⬎ xⴱ x3 = f共x2兲 ⬎ xⴱ x3 = f共x2兲 ⱕ xⴱ x3 = f共x2兲 ⱕ xⴱ
共1,1兲 4 x4 = f共x3兲 ⬎ xⴱ x4 = f共x3兲 ⱕ xⴱ x4 = f共x3兲 ⬎ xⴱ x4 = f共x3兲 ⱕ xⴱ x4 = f共x3兲 ⬎ xⴱ x4 = f共x3兲 ⱕ xⴱ

Alternately one can use the iteration value n to encode logic gate outputs, in consecutive iterations, using a single
the logic inputs, one-dimensional chaotic element.
n → n + I1 + I2 . A. Half-adder operation
This again yields four distinct input conditions: A half-adder operates on two inputs, I1 and I2, and yields
Case 1: Both I1 and I2 are 0 共row 1 in Table I兲, i.e., the two outputs, carry and sum. Carry is the AND logic output of
evolution time is n + 0 + 0 = n. I1 and I2 关i.e., O1 = AND共I1 , I2兲兴, and sum is the XOR of I1
Case 2: I1 = 1 , I2 = 0 共row 2 in Table I兲, i.e., the evolu- and I2 关i.e., O2 = XOR共I1 , I2兲兴. A summary of the necessary
tion time is n + ␦ + 0 = n + ␦. and sufficient conditions to be satisfied for the cascaded bit-
Case 3: I1 = 0 , I2 = 1 共row 3 in Table I兲, i.e., the evolu- by-bit addition operation is given in Table VIII. It is required
tion time is n + 0 + 2␦ = n + 2␦. to have all the necessary and sufficient conditions tabulated
Case 4: Both I1 and I2 are 1 共row 4 in Table I兲, i.e., the in Table VIII to be satisfied simultaneously to implement
evolution time is n + ␦ + 2␦ = n + 3␦. O1 = AND共I1 , I2兲 and O2 = XOR共I1 , I2兲, since the mapping
After chaotic updates over n steps, the state of the from 共I1 , I2兲 to 共O1 , O2兲 must hold for all combinations of
evolved system f n共x兲 yields the desired logic output. 共I1 , I2兲. Conversely, when these conditions are satisfied,
In order to obtain all the desired input-output responses O1 = AND共I1 , I2兲 and O2 = XOR共I1 , I2兲 hold. That is, these
of all the basic logic gates displayed in Table I, we need to conditions are necessary and sufficient for the logic opera-
satisfy all the conditions enumerated in Table VII simulta- tions implementing half-adder arithmetic operation. For in-
neously. stance, for x0 = 0, xⴱ = 0.65, ␦ = 0.1, and a = 4.0, outputs O1
As a case study, we will next consider the implementa- and O2 are obtained in iterations n = 1 and 2, respectively, for
tion of bit-by-bit addition and subtraction, thus demonstrat- the logistic map.
ing how complex combinational operations can be directly
achieved by a single system, without necessitating concat- B. Half-subtractor operation
enation. Significantly, the half-subtractor is an asymmetric
logic operation and so it cannot be obtained by the formal- A half-subtractor operates on two inputs I1 and I2 and
ism in Sec. II. yields two outputs, borrow and difference. Borrow is the re-
sult of the AND operation on NOT共I1兲 and I2 关i.e.,
V. IMPLEMENTATION OF BIT-BY-BIT ARITHMETIC
O1 = AND共NOT共I1兲 , I2兲兴, and difference is the result of the
FUNCTIONS XOR operation on I1 and I2 关i.e., O2 = XOR共I1 , I2兲兴. A sum-
mary of the necessary and sufficient conditions to be satisfied
We demonstrate here how one can obtain the very for the cascaded bit-by-bit subtraction operation is given in
widely used bit-by-bit arithmetic function involving two Table IX. It is required that all the necessary and sufficient

TABLE VIII. Truth table of the half-adder and the necessary and sufficient TABLE IX. Truth table of half-subtractor and the necessary and sufficient
conditions that implement the half-adder. conditions that implement the half-subtractor.

Necessary Necessary
Logic Input set Logic and sufficient Logic Input set Logic and sufficient
operation 共I1 , I2兲 output Initial state condition operation 共I1 , I2兲 output Initial state condition
ⴱ
Carry 共0,0兲 0 x0 x1 = f共x0兲 ⱕ x Difference 共0,0兲 0 x0 = 0.525 x3 = f共x0兲 ⱕ xⴱ
共0,1兲 0 共x0 + ␦兲 x1 = f共x0 + ␦兲 ⱕ xⴱ 共0,1兲 1 共x0 + ␦兲 = 0.625 x3 = f共x0 + ␦兲 ⬎ xⴱ
共1,0兲 0 共x0 + 2␦兲 x1 = f共x0 + 2␦兲 ⱕ xⴱ 共1,0兲 1 共x0 + 2␦兲 = 0.725 x3 = f共x0 + 2␦兲 ⬎ xⴱ
共1,1兲 1 共x0 + 3␦兲 x1 = f共x0 + 3␦兲 ⬎ xⴱ 共1,1兲 0 共x0 + 3␦兲 = 0.825 x3 = f共x0 + 3␦兲 ⱕ xⴱ
Sum 共0,0兲 0 x0 x2 = f共x0兲 ⱕ xⴱ Borrow 共0,0兲 0 x0 = 0.525 x4 = f共x0兲 ⱕ xⴱ
共0,1兲 1 共x0 + ␦兲 x2 = f共x0 + ␦兲 ⬎ xⴱ 共0,1兲 1 共x0 + ␦兲 = 0.625 x4 = f共x0 + ␦兲 ⬎ xⴱ
共1,0兲 1 共x0 + 2␦兲 x2 = f共x0 + 2␦兲 ⬎ xⴱ 共1,0兲 0 共x0 + 2␦兲 = 0.725 x4 = f共x0 + 2␦兲 ⱕ xⴱ
共1,1兲 0 共x0 + 3␦兲 x2 = f共x0 + 3␦兲 ⱕ xⴱ 共1,1兲 0 共x0 + 3␦兲 = 0.825 x4 = f共x0 + 3␦兲 ⱕ xⴱ

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 037107-6 Ditto et al. Chaos 20, 037107 共2010兲

Input IN1 Out Output

ChaoGate
Input IN2
Element
VT1 VT2 VT3

Analog Analog Analog

Select
Select Select Select

Global
Thresholds
FIG. 2. 共Color online兲 Simplified schematic of the proof of concept VLSI
implementation of an ALU which can switch between at least two arithmetic
functions and a completely different function such as a small first-in, first- FIG. 3. 共Color online兲 共Left兲 Schematic of a two-input, one output mor-
out memory buffer. phable chaogate. The gate logic functionality 共NOR, NAND, and XOR兲 is
controlled 共morphed兲 in the current VLSI design by global thresholds con-
nected to VT1, VT2, and VT3 through analog multiplexing circuitry and
conditions tabulated in Table IX be satisfied simultaneously 共right兲 a size comparison between the current chaogate circuitry imple-
mented in the ChaoLogix VLSI chaotic computing chip and a typical
to implement O1 = AND共NOT共I1兲 , I2兲 and O2 = XOR共I1 , I2兲, NAND gate circuit 共courtesy of ChaoLogix, Inc.兲.
since the mapping from 共I1 , I2兲 to 共O1 , O2兲 must hold for all
combinations of 共I1 , I2兲. Conversely, when these conditions
are satisfied, O1 = AND共NOT共I1兲 , I2兲 and O2 = XOR共I1 , I2兲
hold. That is, these conditions are necessary and sufficient
for the logic operations implementing the half-subtractor Chaogates were then incorporated into a chaogate array
arithmetic operation. For instance, with x0 = 0.525, xⴱ = 0.65, in the VLSI chip to demonstrate higher order morphing func-
␦ = 0.1, and a = 4.0, outputs O2 and O1 are obtained in itera- tionality including the following:
tions n = 3 and n = 4, respectively, for the logistic map.
共1兲 A small ALU that morphs between higher order arith-
So the highlight of this method is the ability of a single
metic functions 共multiplier and adder/accumulator兲 in
nonlinear system to yield complicated logic outputs. The ba-
sis of this ability is the range of states a nonlinear system less than one clock cycle. An ALU is a basic building
accesses in the course of its evolution. This allows the evo- block of computer architectures.
lution time to be used as a “knob” to extract different com- 共2兲 A communications protocols unit that morphs between
binational logic responses, without necessitating concatena- two different complex communications protocols in less
tion of many units. than one clock cycle: serial peripheral interface 共a syn-
Thus we have presented a design for a computing device chronous serial data link兲 and an inter-integrated circuit
based on the capability of a nonlinear system to implement control bus implementation 共I2C, a multimaster serial
all the fundamental computing operations. It does this by computer bus兲.
exploiting the nonlinear responses of the system. The main While the design of the chaogates and chaogate arrays in
benefit is its ability to reconfigure a single chaotic element
this proof of concept VLSI chip was not optimized for per-
into different logic gates. Contrast this with a conventional
formance, it clearly demonstrates that chaogates can be con-
field programmable gate array element, where reconfigura-
structed and organized into reconfigurable chaotic logic gate
tion is achieved through switching between multiple single
arrays capable of morphing between higher order computa-
purpose gates. This latter sort of reconfiguration is both slow
tional building blocks. Current efforts are focused upon op-
and wasteful of space on an integrated circuit.
timizing the design of a single chaogate to levels where it is
comparable to or smaller than a single NAND gate in terms
VI. VLSI IMPLEMENTATION OF CHAOTIC COMPUTING of power and size, yet is capable of morphing between all
ARCHITECTURES—PROOF OF CONCEPT
gate functions in less than a single computer clock cycle.
Recently ChaoLogix, Inc. designed and fabricated a Preliminary designs indicate that this goal is achievable and
proof of concept chip that demonstrates the feasibility of that all gates currently used to design computers may be
constructing reconfigurable chaotic logic gates, dubbed cha- replaced with chaogates to provide added flexibility and per-
ogates, in standard CMOS-based VLSI 共0.18 ␮m process formance. Practical applications may also take a hybrid ap-
operating at 30 MHz with a 3.1⫻ 3.1 mm die size and a 1.8 proach, combining static hardware with modules of program-
V digital core兲. The basic building block chaogate is shown mable hardware.
schematically in Fig. 2. One should also add the following caveat: programming
The demonstration chip 共Fig. 3兲 has a parallel read/write chaogates requires the development of new hardware de-
interface to communicate with a microcontroller using stan- scription languages. The absence of these may pose a bottle-
dard logic gates. The read/write interface responds to a range neck in obtaining the most efficient use of the chaogate. It is
of addresses to give access to internal registers, and the in- conceivable that ideas from evolutionary algorithms may be
ternal registers will interface to the demonstration chaotic employed to reach optimal configurations of arrays of cha-
computing circuits. ogates. At this point, this is still a completely open problem.

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 037107-7 Chaogates: Morphing logic gates Chaos 20, 037107 共2010兲

5
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6
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10
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11
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13
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14
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共ASIC兲,22 and the general utility of a central processing unit 15
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19
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