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Indian Institute of Technology Goa: EE 232 Digital Circuits and Lab

The document provides instructions for an assignment to design an adder/subtractor unit and encoder. Students are asked to: 1. Design a unit to add or subtract two 4-bit XS3 encoded operands and output an 8-bit BCD encoded result, assuming the first operand is always greater. 2. Write VHDL for the unit and simulate to verify functionality. 3. Write VHDL using the designed blocks to indicate invalid output if the result is greater than 9, and simulate to verify functionality. The deadline is October 19th.

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Vishal Sharma
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51 views

Indian Institute of Technology Goa: EE 232 Digital Circuits and Lab

The document provides instructions for an assignment to design an adder/subtractor unit and encoder. Students are asked to: 1. Design a unit to add or subtract two 4-bit XS3 encoded operands and output an 8-bit BCD encoded result, assuming the first operand is always greater. 2. Write VHDL for the unit and simulate to verify functionality. 3. Write VHDL using the designed blocks to indicate invalid output if the result is greater than 9, and simulate to verify functionality. The deadline is October 19th.

Uploaded by

Vishal Sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Indian Institute of Technology Goa

EE 232 Digital Circuits and Lab


Instructor: Nandakumar Nambath
Assignment III: (En/De)coders

General instructions:

• Prepare a minimal report consisting of all the results in PDF format and upload the same. You have
to include the screenshots of the generated netlist and ModelSim waveforms.

• Along with the report upload a zip file containing your VHDL files for all the simulations.

• Make sure that the report and the zip file you upload have your name and roll number on them. I
hope I don’t have to remind you that this is not a group activity.

• The maximum upload size is 5 MB and the deadline is 10 pm on 19-10-2020.

• You are free to assume any missing data, but state them clearly in your solution. Feel free to use
the Piazza forum to discuss any doubts, but not the solutions.

1. Design an adder/subtractor unit which operates on two 4-bit XS3 encoded operands and gives out
an 8-bit BCD encoded output. Assume first operand is always greater than the second one. Make
use of the building blocks you have already designed for this purpose.

2. Write down a VHDL description for the entity given below, corresponding to your design, simulate
the design, and verify the functionality from the simulations.

entity XS3_ADD_SUB is -- Entity declaration


port(A, B : in std_logic_vector(3 downto 0); -- Input XS3 numbers
A_SBAR : in std_logic; -- 1 for addition, 0 for subtraction
Y : out std_logic_vector(7 downto 0); -- Output BCD number
end XS3_ADD_SUB;

3. Write down a VHDL description for the entity given below, instantiating the blocks you have designed
so far. The invalid output indicator should go high whenever the output of the adder/subtractor
module is greater than 9. Simulate your design using ModelSim and verify the functionality.

entity XS3_ADD_SUB_LED is -- Entity declaration


port(A, B : in std_logic_vector(3 downto 0); -- Input XS3 numbers
A_SBAR : in std_logic; -- 1 for addition, 0 for subtraction
Y : out std_logic_vector(6 downto 0); -- Output SSD code
F : out std_logic); -- Invalid output indicator
end XS3_ADD_SUB_LED;

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