Indian Institute of Technology Goa

EE 232 Digital Circuits and Lab

Instructor: Nandakumar Nambath
Assignment II: My Nibble Arithmetic Logic Unit

General instructions:
• Please go through the videos on VHDL and the sections 5.5 and 6.6 from Stephen Brown and Zvonko
Vranesic, “Fundamentals of Digital Logic with VHDL Design,” Tata McGraw Hill before you attempt
this assignment.
• Prepare a minimal report consisting of all the results in PDF format and upload the same. You have
to include the screenshots of the generated netlist and ModelSim waveforms.
• Along with the report upload a zip file containing your VHDL files for all the simulations.
• Make sure that the report and the zip file you upload have your name and roll number on them. I
hope I don’t have to remind you that this is not a group activity.
• The maximum upload size is 5 MB and the deadline is 10 pm on 19-10-2020.
• You are free to assume any missing data, but state them clearly in your solution. Feel free to use
the Piazza forum to discuss any doubts, but not the solutions.

1. Nibble Subtractor: Use the FOUR BIT ADDER designed previously to obtain the functionality of
a FOUR BIT SUBTRACTOR. Simulate your design using ModelSim to verify the functionality. (Hint:
Watching the Addition and Subtraction of 2’s Complement Numbers video might help you. See if
the circuit shown in Fig. 1 works as an adder when SU B/ADD = 0 and as a subtractor when
SU B/ADD = 1.)
B3 B2 B1 B0
SUB/ADD
A3 A2 A1 A0

B3 B2 B1 B0 A3 A2 A1 A0

Cin Four bit adder

Cout S3 S2 S1 S0

Figure 1: Generic adder/subtractor unit.

2. 2:1 Multiplexer: Write a VHDL description for the following entity instantiating 2-input AND,
2-input OR and NOT gates. Simulate the design using ModelSim and verify its functionality. (Hint:
What is the Boolean expression of a 2:1 MUX output? Watching the Multiplexers and Demultiplexers
video might help you.)

entity MUX_2X1 is -- Entity declaration

port(I0, I1, S0 : in std_logic; -- Inputs of the multiplexer
O0 : out std_logic); -- Output of the multiplexer
end entity;

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3. 4:1 Multiplexer: Write a VHDL description for the following entity instantiating the 2:1 MUXes de-
signed previously. Simulate the design using ModelSim and verify its functionality. (Hint: Watching
the Multi-Input Multiplexers video might help you.)

entity MUX_4X1 is -- Entity declaration

port(I0, I1, I2, I3 : in std_logic; -- Inputs of the multiplexer
S : in std_logic_vector(1 downto 0);
O0 : out std_logic); -- Output of the multiplexer
end entity;

4. 16:4 Multiplexer: Write a VHDL description for the following entity instantiating the 4:1 MUXes
designed previously. Simulate the design using ModelSim and verify its functionality. (Hint: Watch-
ing the Multi-Input Multiplexers video might help you.)

entity MUX_16X4 is -- Entity declaration

port(I0, I1, I2, I3 : in std_logic_vector(3 downto 0);-- Inputs of the multiplexer
S : in std_logic_vector(1 downto 0);
O0 : out std_logic_vector(3 downto 0)); -- Output of the multiplexer
end entity;

B0
A3 A2 A1 A0
B1
A3 A2 A1 A0
0

B3 B2 B1 B0 A3 A2 A1 A0

0 Cin Four bit Adder

Cout S3 S2 S1 S0
B2

B3 B2 B1 B0 A3 A2 A1 A0
0 Cin Four bit Adder
Cout S3 S2 S1 S0
B3

B3 B2 B1 B0 A3 A2 A1 A0
0 Cin Four bit Adder
Cout S3 S2 S1 S0

P7 P6 P5 P4 P3 P2 P1 P0

Figure 2: 4-bit array multiplier

5. Four-bit Array Multiplier: Complete the design of a 4-bit array multiplier for unsigned numbers
shown in Fig. 2. Write a structural VHDL description for the entity given below. In the design use

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 4-bit ripple carry adder and AND gate designed previously. Simulate the design using ModelSim and
verify its functionality. (Hint: Watching the Multiplication of 2’s Complement Numbers video might
help you. Reading section 5.6.1 of the textbook might also help you with the design.)

entity MULTIPLIER is -- Entity declaration

port(A, B : in std_logic_vector(3 downto 0); -- Inputs of the multiplier
M : out std_logic_vector(7 downto 0)); -- Output of the multiplier
end MULTIPLIER;

6. My Nibble ALU:

Operand A Operand B
4 4

Opcode S Overflow status O

3
4
Output F

Figure 3: My nibble ALU

(a) The architecture of a nibble arithmetic logic unit (ALU) is shown in Fig. 3. It has two 4-bit
unsigned inputs, A and B, a 3-bit opcode input, S, a 4-bit output function, F, and an overflow
status indicator, O which goes high whenever there is an overflow in the operations. Design this
ALU which performs the eight arithmetic and logic operations as per Table 1.

Table 1: Functionality of the Nibble ALU

Input Outputs
Operation
S(2) S(1) S(0) F

Addition 0 0 0 A + B
Subtraction 0 0 1 A - B
Subtraction 0 1 0 B - A
Bit-wise AND 0 1 1 A AND B
Bit-wise OR 1 0 0 A OR B
Bit-wise XOR 1 0 1 A XOR B
Bit-wise NOT 1 1 0 A’
Multiplication 1 1 1 A x B

(b) Write a VHDL description for the entity given below. In the design use the blocks designed
previously, such as adder, subtractor, multiplexers–especially the 16:4 multiplexer, etc. Simulate

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the design using ModelSim and verify its functionality. (Hint: The example 6.24 in the textbook
will help you with the concept. The behavioral code of a similar ALU is also given there. But,
you have to implement the functionality described in Table 1 instantiating the components you
have designed so far.)
entity NIBBLE_ALU is -- Entity declaration
port(A, B : in std_logic_vector(3 downto 0);-- Operands of the ALU
S : in std_logic_vector(2 downto 0); -- Opcode of the ALU
F : out std_logic_vector(3 downto 0); -- Output of the ALU
O : out std_logic); -- Overflow status of the ALU
end NIBBLE_ALU;