Bluespec Compiler, Bluesim, Emvm, and Development Workstation Release Notes
Bluespec Compiler, Bluesim, Emvm, and Development Workstation Release Notes
The 2012.01 release provides enhancements throughout the product set. The release includes two new
object-oriented Tcl API: Virtual and Waves. Virtual allows users to analyze the elaborated
hierarchy of a Bluespec design and its relation to the generated Verilog. Waves allows users to interact
with waveform viewers and decorate the waveforms with Bluespec-specific type information. Also
included is a new DMA lab controller exercise.
Documentation references are provided in parentheses. The following documents are referenced:
Reference Guide: rg
User Guide: ug
Prelude Enhancements
Compiler
Added parameter= attribute to support renaming module parameters in the generated RTL (rg
13.6.5)
Simplified file structure by no longer generating .bi files
Schedule will now return some information even if an error occurs in the middle of a compile, to
aid in debugging. This information is available with the –show-schedule flag (ug 7.13, 8.2.2)
AzureIP Library
Added extended precision fixed point operations to the FixedPoint package (rg C.5.3)
Added GetS interface to GetPut package which separates the get method into two methods:
first and deq. (rg C.7.1)
Efficiency improvements in FShow implementation (rg C.8.8)
Development Workstation
Type class information now displayed from Package Browser window. If you select a typeclass,
all instances of the typeclass will be displayed. (ug 5.1)
Added support for Bluespec-specific nWave behavior (ug 5.3.2)
Schedule analysis window now includes errors along with warnings. (ug 5.4.1)
Bluetcl
New Bluetcl API to facilitate analyzing Bluespec designs
o Virtual package provides Bluespec-specific accessor objects to analyze elaborated
hierarchy and its relation to the generated Verilog. (ug B.4.5)
o Waves package allows user to interact with waveform viewer objects and decorates
viewer with Bluespec-specific type information. (ug B.4.6)
Documentation
A DMA controller lab has been added, which leads the user through the basic aspects of the BSV
language and usage of the Bluespec Development Workstation for Bluesim and Verilog
simulations. The lab includes exercises using BSV’s TLM interface and implementing the
controller in emVM.
Corrections and updates have been made in all manuals