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Beginning FPGA Programming - Partie61

This document describes changes needed to be made to an i2c_slave.vhd IP file to change signal statuses from '1' to 'H'. It lists specific lines that need to be changed. It then describes steps to create a temperature sensor project in Quartus Prime, including adding necessary files, an Altera PLL IP, setting up a simulation testbench, and compiler settings.

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ali alilou
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52 views

Beginning FPGA Programming - Partie61

This document describes changes needed to be made to an i2c_slave.vhd IP file to change signal statuses from '1' to 'H'. It lists specific lines that need to be changed. It then describes steps to create a temperature sensor project in Quartus Prime, including adding necessary files, an Altera PLL IP, setting up a simulation testbench, and compiler settings.

Uploaded by

ali alilou
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapter 13 ■ Temperature Sensors: Is It Hot in Here, or Is It Just Me?

13.5.3.2 i2c_slave.vhd Code
We downloaded this .vhdl IP file from github.com and we need to make the following change to this IP. All
of those that are sda and scl with a status of '1' need to change to have a status of 'H'. The following shows the
line number that needs to be changed. Line 50 and line 262 are added to the vhdl.

Line 50: signal sda_i : std_logic;


Line 65: if scl_prev_reg = '0' and scl = 'H' then
Line 69: if scl_prev_reg = 'H' and scl = '0' then
Line 76: if scl = 'H' and scl_prev_reg = 'H' and
Line 77: sda_prev_reg = 'H' and sda = '0' then
Line 83: if scl_prev_reg = 'H' and scl = 'H' and
Line 84: sda_prev_reg = '0' and sda = 'H' then
LINE 117: addr_reg(6-bits_processed_reg) <= sda_i;
LINE 120: cmd_reg <= sda_i;
LINE 161: data_reg(6-bits_processed_reg) <= sda_i;
LINE 163: data_from_master_reg <= data_reg & sda_i;
Line 194: if sda = 'H' then -- nack = stop read

Line 261: read_req <= read_req_reg;


Line 262: sda_i <= '1' when sda = 'H' else '0';
Line 263: end architecture arch;

13.5.4 Create Temperature Sensor Project Design and Program It


We will start creating a project from a project template: BeMicro MAX 10 Kit Baseline Pinout.
1.
Project ➤ Add / Remove Files in the project and add all of the files from the
uart_16660_wrapper IP (under the core Figure 13-24 and core/library Figure 13-25)

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Chapter 13 ■ Temperature Sensors: Is It Hot in Here, or Is It Just Me?

Figure 13-24.  File list of UART 1650 IP core

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Chapter 13 ■ Temperature Sensors: Is It Hot in Here, or Is It Just Me?

Figure 13-25.  File list of UART 1650 IP library

2.
Project ➤ Add / Remove Files in the project and add i2c_master.vhd,
uartTOi2c.vhd, and temperature_sensor_top.vhd files in the project.
3.
Add Altera PLL IP—pll_29p5M.vhd as shown in the FPGA IP—Altera PLL IP
section
4.
Set up simulation tool and test bench. Assignment ➤ Settings… ➤ EDA Tool
Settings / Simulation ➤ Select Compile test bench and click Test Benches…
(Figure 13-26)

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Chapter 13 ■ Temperature Sensors: Is It Hot in Here, or Is It Just Me?

Figure 13-26.  Add test bench to the project

5.
Open the Test Benches window pop-up and click New… (Figure 13-27)

Figure 13-27.  Test Benches list

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Chapter 13 ■ Temperature Sensors: Is It Hot in Here, or Is It Just Me?

6.
In the New Test Bench Settings window, please follow Figure 13-28 and click OK
and OK again. You will add two .vhd files under Create new test bench settings:
I2C_slave.vhd and tb_temp_sensor_top.vhd.

Figure 13-28.  New Test Bench Settings

■■Note Only add the tb_temp_sensor_top.vhd under test bench settings but NOT the project file section.

7.
In the Compiler Setting ➤ VHDL Input, select VHDL 2008. Figure 13-29 shows
the setting.

301

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