Microprocessors and Microcontrollers/Interfacing with 8051 Multiple Choice

Questions
1. In 8051 an external interrupt 1 vector address is of ________ and causes of
interrupt if ____.
a) 000BH, a high to low transition on pin INT1
b) 001BH, a low to high transition on pin INT1
c) 0013H, a high to low transition on pin INT1
d) 0023H, a low to high transition on pin INT1

2. 2. Serial port vector address is of _______. And causes an interrupt when

________.
a) 0013H, either TI or RI flag is set
b) 0023H, either TI or RI flag is reset
c) 0013H, either TI or RI flag is reset
d) 0023H, either TI or RI flag is set

3.In modes 2 and 3, if _____ bit of SCON bit is set will causes enable multiprocessor
communication and is of ____ bit address. A
) SM1, 9EH
b) TB8 , 9CH
c) SM2 , 9DH
d) SM0, 9FH

1. Which devices are specifically being used for converting serial to parallel and from
parallel to serial respectively?
a) timers
b) counters
c) registers
d) serial communication
View Answer
2. What is the difference between UART and USART communication?
a) they are the names of the same particular thing, just the difference of A and S is
there in it
b) one uses asynchronous means of communication and the other uses synchronous
means of communication
c) one uses asynchronous means of communication and the other uses asynchronous
and synchronous means of communication
d) one uses angular means of the communication and the other uses linear means of
communication
View Answer
3. Which of the following best describes the use of framing in asynchronous means of
communication?
a) it binds the data properly
b) it tells us about the start and stop of the data to be transmitted or received
c) it is used for error checking
d) it is used for flow control

4. Which of the following signal control the flow of data?

a) RTS
b) DTR
c) both of the mentioned
d) none of the mentioned

5. Which of the following is the logic level understood by the micro-controller/micro-

processor?
a) TTL logic level
b) RS232 logic level
c) none of the mentioned
d) both of the mentioned

6. What is null modem connection?

a) no data transmission
b) no MAX232
c) the RxD of one is the TxD for the other
d) no serial communication

7. Which of the following best states the reason that why baud rate is mentioned in
serial communication?
a) to know about the no of bits being transmitted per second
b) to make the two devices compatible with each other, so that the transmission
becomes easy and error free
c) to use Timer 1
d) for wasting memory

8. With what frequency UART operates( where f denoted the crystal frequency )?
a) f/12
b) f/32
c) f/144
d) f/384

9. What is the function of SCON register?

a) to control SBUF and SMOD registers
b) to program the start bit, stop bit, and data bits of framing
c) none of the mentioned
d) both of the mentioned
10. What should be done if we want to double the baud rate?
a) change a bit of the TMOD register
b) change a bit of the PCON register
c) change a bit of the SCON register
d) change a bit of the SBUF register
11. The serial communication is
a) cheaper communication
b) requires less number of conductors
c) slow process of communication
d) all of the mentioned

12. The serial communication is used for

a) short distance communication
b) long distance communication
c) short and long distance communication
d) communication for a certain range of distance
View Answer
13. The mcs 51 architecture supports
a) serial transmission and reception
b) simultaneous transmission and reception
c) transmission and reception of data using serial communication interface
d) all of the mentioned

14. The number of bits transmitted or received per second is defined as

a) transmission rate
b) reception rate
c) transceiver rate
d) baud rate

15. The task of converting the byte into serial form and transmitting it bit by bit along
with start, stop and parity bits is carried out by
a) reception unit
b) serial communication unit
c) transmission unit
d) all of the mentioned

16. The transmission unit does not require assistance from processor if once a byte for
transmission is written to
a) SCON register
b) SBUF register
c) SFR address
d) any of the mentioned

17. The common unit shared by the receiver unit and transmission unit of serial
communication unit is
a) SCON(Serial Port Control) Register
b) SBUF(Serial Buffer) register
c) 8-bit serial data interface
d) all of the mentioned

18. During serial reception, the buffer that receives serial bits and converts to a byte is
a) receive buffer 0
b) receive buffer 1
c) receive buffer 2
d) none

19. If SM0=1, SM1=0, then the transceiver selected is

a) 8-bit synchronous
b) 9-bit synchronous
c) 8-bit asynchronous
d) 9-bit asynchronous

20. If the microcontroller is expected to communicate in multiprocessor system, then

the required condition is
a) SM0 is set
b) SM1 is set
c) SM2 is set
d) REN is set

21. In mode 2, the baud rate depends only on

a) SMOD bit
b) SCON bit
c) oscillator clock frequency
d) SMOD bit and oscillator clock frequency

22. The mode that offers the most secured parity enabled data communication at
lower baud rates is
a) mode 2
b) mode 1
c) mode 0
d) all of the mentioned
23. The external interrupts of 8051 can be enabled by
a) 4 LSBs of TCON register
b) Interrupt enable
c) priority register
d) all of the mentioned

24. The bits that control the external interrupts are

a) ET0 and ET1
b) ET1 and ET2
c) EX0 and EX1
d) EX1 and EX2

25. EA bit is used to

a) enable or disable external interrupts
b) enable or disable internal interrupts
c) enable or disable all the interrupts
d) none of the mentioned

26. The number of priority levels that each interrupt of 8051 have is
a) 1
b) 2
c) 3
d) 4

27. The priority level of interrupt of 8051 for which SI(serial interrupt) interrupt is
programmed is
a) level 0
b) level 1
c) level 0 or level 1
d) none

28. The interrupt bit that when set works at level 1, and otherwise at level 0 is
a) PT1
b) PT0
c) PX1
d) all of the mentioned

29. All the interrupts at level 1 are polled in the second clock cycle of the
a) forth T state
b) fifth T state
c) third T state
d) none

30. The minimum duration of the active low interrupt pulse for being sensed without
being lost must be
a) greater than one machine cycle
b) equal to one machine cycle
c) greater than 2 machine cycles
d) equal to 2 machine cycles

31. If two interrupts, of higher priority and lower priority occur simultaneously, then
the service provided is for
a) interrupt of lower priority
b) interrupt of higher priority
c) both the interrupts
d) none of the mentioned

32. For an interrupt to be guaranteedly served it should have duration of

a) one machine cycle
b) three machine cycles
c) two machine cycles
d) four machine cycles

33. The service to an interrupt will be delayed if it appears during the execution of
a) RETI instruction
b) instruction that writes to IE register
c) instruction that writes to IP register
d) all of the mentioned
34.Why is it not necessary to specify the baud rate to be equal to the number of bits
per second ?

A. Because each bit is preceded by a start bit & followed by one stop bit
B. Because each byte is preceded by a start byte & followed by one stop byte
C. Because each byte is preceded by a start bit & followed by one stop bit
D. Because each bit is preceded by a start byte &followed by one stop byte

35.Which factor/s is/are supposed to have the equal values at both phases of
transmission and reception levels with an intimation of error-free serial
communication?

a. Baud Rate
b. Number of data bits & stop bits
c. Status of Parity bits
d. All of the above

36.Which bits exhibit and signify the termination phase of the character transmission
and reception in SCON special function register?
a. Control bits
b. Status bits
c. Both a & b
d. None of the above
37.How does the processor respond to an occurrence of the interrupt?
a. By Interrupt Service Subroutine
b. By Interrupt Status Subroutine
c. By Interrupt Structure Subroutine
d. By Interrupt System Subroutine

38.Which address / location in the program memory is supposed to get occupied when
CPU jump and execute instantaneously during the occurrence of an interrupt ?
a. Scalar
b. Vector
c. Register
d. All of the above

39.Which location specify the storage / loading of vector address during the interrupt
generation?
a. Stack Pointer
b. Program Counter
c. Data Pointer
d. All of the above
40.Match the following :
A. ISS --------------------------------------- 1. Monitors the status of interrupt pin
B. IER --------------------------------------- 2. Allows the termination of ISS
C. RETI ------------------------------------- 3. MCS-51 Interrupts Initialization
D. INTO ------------------------------------ 4. Occurrence of high to low transition level
Codes :
a. A-1, B-2, C-3, D-4
b. A-3, B-2, C-4, D-1
c. A-1, B-3, C-2, D-4
d. A-4, B-3, C-2, D-1