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Aro Experiment 7 PDF

1. The document describes an experiment on implementing full adder circuits using logic gates. Students learned about the design of full adders, derived logic expressions for SUM and CARRY outputs, and implemented a 4-bit adder circuit by cascading full adders. 2. The experiment objectives were to design full adders using logic gates and implement a cascaded full adder circuit. Students tested various input combinations on a built full adder circuit and derived the SUM and CARRY expressions. 3. By employing a cascading technique, students then constructed a 4-bit adder circuit and tested sample input expressions to obtain the output sums. The experiment concluded with students understanding full adder circuit design and behavior through

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Trisha SARMIENTO
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102 views6 pages

Aro Experiment 7 PDF

1. The document describes an experiment on implementing full adder circuits using logic gates. Students learned about the design of full adders, derived logic expressions for SUM and CARRY outputs, and implemented a 4-bit adder circuit by cascading full adders. 2. The experiment objectives were to design full adders using logic gates and implement a cascaded full adder circuit. Students tested various input combinations on a built full adder circuit and derived the SUM and CARRY expressions. 3. By employing a cascading technique, students then constructed a 4-bit adder circuit and tested sample input expressions to obtain the output sums. The experiment concluded with students understanding full adder circuit design and behavior through

Uploaded by

Trisha SARMIENTO
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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De La Salle Lipa

1962, J.P. Laurel, Mataas na Lupa, Lipa City


Department of Electrical Engineering

Experiment # 7
FULL ADDERS

Name: ARO, DANILIA G. DOP:11-28-20


Course and Year: BSEE – 3rd Year DOS:12-12-20
Subject and Section: Logcist – V3B

Grade

Engr. Ramon P. Flores IV, MEO – CoE


Instructor
I. OBJECTIVES
At the end of the experiment, the students should be able to:
1. implement the design of full adders through the use of logic gates
2. implement a cascaded full adder circuit

II. EQUIPMENTS AND MATERIALS USED

1 Power Supply (w/ 5V DC source)


1 Logic Probe
1 Connecting Wires
1 Breadboard
2 7486 XOR Gates
3 7408 AND Gate
2 7432 OR Gate
2 LED Lights

III. DATA SHEET


1. Shown below is the circuit for the full adder implementation. Build the
circuit and supply the input combinations. Through the use of the logic
probe, test for the results and tabulate the findings on the table provided.
A B C CARRY SUM
0 0 0 0 0
1 0 0 0 1
1 1 0 0 1
0 1 1 1 0
0 0 1 0 1
0 1 0 1 0
1 0 1 1 0
1 1 1 1 1

2. Based on the truth table that you have tabulated, derive the expression for
the output variables SUM and CARRY.

SUM= A B C
CARRY= AB + C (A B)

3. Supplied with the knowledge of the full adder design, implement a four-bit
adder circuit. Draw the diagram below. (TIP: Employ cascading technique)

4. Construct the four-bit adder circuit; test for the results of the following
expressions and write the answer

A B C D E
1001 1011 0101 1000 0110
+ + + + +
0110 1010 0111 0011 1010
01111 10101 01100 01011 10000

5. Generally, half adders and full adders are represented by block diagrams as
shown.
IV. DISCUSSION
A full adder circuit is a digital circuit that performs addition. This adder
circuit design includes three inputs, the A, B (two binary numbers) and CARRY
IN and gives two number outputs, the SUM and CARRY. A full adder behavior
shows that when all inputs are LOW (0), the SUM and CARRY are also LOW (0)
and when all inputs are HIGH (1) the outputs are also HIGH (1). As for the output
of the CARRY, if the two or more inputs are HIGH (1), the CARRY output is
HIGH (1). Meanwhile, the sum produces a HIGH (1) output when two inputs are
LOW (0). Students used K-maps to produce the logic expression. With the usage
of a full adder design and a half adder design, students were able to implement a
four-bit adder circuit.
V. CONCLUSION
In this experiment, students were able to understand the full adder circuit
design. With the usage of Kmaps, students produced the logic expression. A full
adder circuit performs addition with the usage of logic gates. These includes the
usage of XOR Gates, OR Gates and AND Gate. All in all, students learned the
behavior and the implementation of the cascaded full adder circuit and
implemented the full adder design with the usage of logic gates. Including the
importance of a four-bit adder circuit.

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