A 0.

6 Volt Class-AB CMOS Voltage Follower

with Bulk-Driven Quasi-Floating Gate
Super Source Follower

Skawrat Wangtaphan and Varakorn Kasemsuwan, Member, IEEE

School of Electronics Engineering, Faculty of Engineering,
King Mongkut’s Institute of Technology Ladkrabang (KMITL)
Bangkok 10520, THAILAND
E-mail: kkvarako@kmitl.ac.th

Abstract—This paper presents a design of 0.6 V class-AB voltage feedback and/or additional circuitry at the output stages.
follower (VF) using 0.13 µm CMOS technology. The follower is Unfortunately, these solutions increased the circuit complexity,
developed based on the super source follower (SSF) using bulk- quiescent power consumption and, in most cases, reduced the
driven and quasi-floating gate (QFG) techniques. The proposed bandwidth. An interesting alternative solution known as super
VF can operate at low voltage without DC level shift between the source follower (SSF) is shown in Figure 1 [5]. As seen, the
input and output terminals. The simulation results show the total circuit is quite simple. The bias current of M1 is determined by
harmonic of 0.3 % for an input/output voltage of 0.18 Vpp at 100 the current source (IB) and independent of the output current,
kHz (RL//CL=5 kΩ//100 pF). The power dissipation is found to be resulting in constant gate-source voltage (VGS1). As a result, the
38 µW. output voltage follows the input. Transistors M2 is responsible
for driving load and, at the same times, form a negative
Keywords-buffer; super source follower; bulk-driven; quasi- feedback loop, resulting in the low output impedance. This
floating gate; low volt; low power
type of structure however suffers from three main drawbacks:
1) the circuit is operating in class A and thus its maximum
I. INTRODUCTION current driving capability is limited by IB, 2) the input swing is
Voltage followers (VFs) are one among useful basic limited to VSS+VDSsat ≤ vIN ≤ VDD− (2VDSsat+VT) and 3) the supply
building blocks in several analog and mixed-signal integrated voltage required of at least 3VDSsat + VT is required.
circuits. VFs have been used in several applications such as VDD
filters, comparators, current-conveyors and operational
transconductance amplifier (OTA) [1]-[3]. Normally, VFs are
required to have large driving capability, large output voltage 2IB
swing, low harmonic distortion and ability to operate at low
supply voltage. Low voltage operation becomes essential in vOUT
order to lower the power consumption and ensure the gate-
oxide reliability. Unfortunately, scaling down the supply vIN M1
voltage presents a formidable challenge to the design of analog M2
circuits. This challenge comes from the fact that the threshold
voltages of MOSFET devices cannot be set arbitrarily low but IB
set by the amount of off-state leakage current that can be
tolerated. It is known that class-AB VFs are used for their VSS VSS
relatively high power conversion efficiency and for current- Figure 1. Conventional super source follower [5]
handling capabilities, not limited by the quiescent currents. The
quiescent can be made small and, therefore, class AB VF is the Voltage followers using SSF technique have been modified
preferred choice for low power applications. and proposed in [6]-[10]. Their circuits showed good
performance, namely, low output impedance, good linearity
Several class-AB VFs have been proposed [4]-[15]. VF
and high bandwidth. However, their structures suffer from two
proposed in [4] is one of traditional CMOS class-AB VFs
common drawbacks: 1) supply voltage of at least 3VDSsat + VT is
whose structure is based on gate-input and source-input
required and 2) output signal swing is limited to less than
configurations. Although its topology showed good power
efficiency, it has limited output swing and requires a supply VSS+2VDSsat+VT ≤ vOUT ≤ VDD−VDSsat. These drawbacks make the
voltage larger than two gate-to-source voltages, precluding its circuit unsuitable especially for a sub volt supply voltage.
operation under low voltage conditions. Attempts to solve such Furthermore, additional circuitry is needed to ensure zero DC
problems have been reported in the literature using negative level shift, thus increasing the circuit complexity, chip area and
power consumption.

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 In this paper, we propose a class-AB VF based on the SSF The circuit however suffers from limited input voltage
structure. Both bulk-driven and quasi-floating gate techniques swing because the DC bias voltage is required at the input to
are employed and the proposed VF can operate at 0.6 V supply turn on M1. In addition, there is a voltage shift between the
with low power consumption, low output impedance and input and output terminals.
relatively wide input and output swings. The paper is organized
as follows. Section II introduces the proposed class-AB VF The problem associated with the input swing has been
and its input/output characteristics. Simulation results are alleviated by applying the input signal to the body terminal
discussed in Section III and conclusions are presented in instead of its gate terminal as illustrated in Fig. 2b). Transistors
section IV. M1, M3 and M5 form the SSF while M2 is used as a replica of
the transistor M1. Since the drain currents of M1 and M2 are the
same (equal to IB) and their gates are connected, the body
II. PREVIOUS VF AND THE PROPOSED CLASS-AB VF terminal voltage of M2 (Vout) tends to replicate the body
Fig. 2a) and 2b) illustrate two recently reported low-voltage terminal input voltage (Vin). One can see that this structure
SSF-based voltage followers [7], [9]. From Fig. 2a), one can results in no DC voltage shift between the input and output
see that, in terms of AC characteristics, a high pass filter is terminals (Vout=Vin).
formed with a cutoff frequency of 1/(2πRlargeCbat), when As previously discussed, M2 and IB are required to keep VGS
observed from the gate of M2 to the gate of M4. Thus the ac of transistor M1 constant and to eliminate the DC level shift
element of the signal at the gate of M2 can propagate to the gate between the input and output terminals. This additional
of M4, which in turn achieves class-AB operation without circuitry and bias current result in an extra power consumption
introducing any extra static current consumption. As a result, and chip area. In addition, the supply voltage of at least
this VF can improve the current driving capability of the class- 3VDSsat+VT is needed, while the output swing is limited to
A SSF in Fig. 1 without degrading other performance
VSS+2VDSsat+VT ≤ vOUT ≤ VDD−VDSsat. The limitation of the output
parameters. It is noted that diode-connected MOSFET
swing poses a serious problem especially when the supply
operating in the cutoff region can be used to form a very large
voltage is below one volt. In addition, loop gain of the circuit is
resistance (Rlarge), which leads to a low cutoff frequency (0.02
quite low because the back-gate transconductance (gmb) is
Hz) [16]. It is also noticed that the signal at the output is fed
employed and approximately four to five times smaller than the
back to the common-gate transistor M1 and to the common-
gate transconductance (gm), causing output impedance to be
source M2. This feedback mechanism ensures low output
relatively larger than that of Fig. 2a).
impedance.
VDD VDD
Rlarge
2× M3
M4
Cbat
IB vOUT
M1
vIN VB2
VSS Cbat Rlarge
M2
IB Rlarge Cbat

VSS VB1 VSS

(a) Figure 3. Propose class-AB bulk-driven quasi-floating gate super SSF
VDD VDD
Rlarge Fig. 3 shows the proposed voltage follower. As seen, the
M4 3× M5 circuit is similar to Figs. 1 and 2 except that both quasi-floating
gate and bulk-driven techniques are employed for the transistor
Cbat M1, while the quasi floating gate is used for the transistor M2.
vOUT The main advantages of this proposed configuration over that
IB
M1 M2 in Fig. 2a) and/or 2b) are the following: 1) the effective
VSS vIN transconductance of the input transistor M1 increases and equal
to Gmeff = gm1+gmb1, resulting larger loop gain and thus lower
M3 output impedance, 2) the bias voltage at the input is decoupled
from the input signal, allowing large input signal swing
IB compared to that of Fig. 2 a), 3) the output swing is larger and
IB
determined by VB1 and VB2, 4) the DC voltage at the output is
VSS VSS VSS set by the bias voltage VB1, bias current IB and size of M1 and
(b) independent on the bias voltage at the input terminal, and 5) the
Figure 2. SSF by a) A.J. Lopez-Martin et al. [7] and b) Y. Haga et al. [9]
circuit exhibit relatively smaller power consumption for the
same performance.
 TABLE I. PERFORMANCE COMPARISON WITH OTHER RECENTLY REPORTED SSFS

Reference Output Impedance Input Swing Output Swing Supply Voltage

1
SSF in [5] Rout ≅ VSS+VDSsat ≤ vIN ≤ VDD− (2VDSsat+VT) VSS+2VDSsat+VT ≤ vOUT ≤ VDD −VDSsat 3VDSsat+VT
( g m1 + g mb1 ) g m 2 ro1
1
SSF in [7] Rout ≅
( g m1 + g mb1 )( g m 2 + g m 4 ) ro1 VSS+VDSsat ≤ vIN ≤ VDD− (2VDSsat+VT) VSS+2VDSsat+VT ≤ vOUT ≤ VDD −VDSsat 3VDSsat+VT

1
SSF in [9] Rout ≅
( g mb1 )( g m 3 + g m 5 )ro1
VSS ≤ vIN ≤ VDD VSS+2VDSsat+VT ≤ vOUT ≤ VDD −VDSsat 3VDSsat+VT

1
This work Rout ≅
( g m1 + g mb1 )( g m 2 + g m3 ) ro1
VSS ≤ vIN ≤ VDD VSS+2VDSsat ≤ vOUT ≤ VDD −VDSsat 2VDSsat+VT

One can derive the output impedance of the proposed SSF

using straight forward small signal analysis which is given by 0.6

1
Rout ≅ (1)

Voltage (V)
( g m1 + g mb1 )( g m 2 + g m3 ) rO1 0.4

where rO1 is drain-source resistance of M1. gm2 and gm3 are the
transconductance of M2 and M3 , respectively. 0.2
Input Voltage
The quiescent current can also be derived and shown as Output Voltage

K 0.2 0.3 0.4 0.5 0.6

I Q = I B + 2 (VB 2 − VT 2 )
2
(2) Voltage (V)
2
Figure 4. DC transfer charecteristic.
where K2 is μCOX(W/L)2. 0.55

The minimum supply voltage that the circuit can operate is 0.50
given by VDD(min) = 2VDSsat+VT and output swing of the circuit is
0.45
Input Voltage
Output Voltage
VSS + 2VDSsat ≤ vOUT ≤ VDD − VDSsat (3) 0.40
Voltage (V)

0.35

Table I shows the performance comparison between the 0.30

proposed circuit and other SSFs. As seen, the output
impedance of the proposed circuit is same as that of the SSF in 0.25

[7] but lower than other SSFs, while the input swing is found to 0.20
be the same as that of SFF in [9] and better than other SSFs. It
is also noticed that our proposed VF shows the largest output 0.15
0 10 20 30 40
swing, and can operate at the minimum supply voltage. Time (us)

Figure 5. Input and output sinusoidal waveforms (0.3 Vpp, 100 kHz).
III. SIMULATION RESULTS
To evaluate the performance of the proposed VF, the circuit Fig. 6 shows the transient response of the proposed circuit,
has been simulated using Cadence Spectre with BSIM3V3 when input signal is a square wave (0.25 Vpp, 1 MHz). The
model parameters. In the design, a 0.13 µm CMOS technology resistor load is 5 kΩ parallel with capacitance load (CL) which
under the supply voltage of 0.6 V is employed. The bias is equal to 100 pF. As seen, the proposed circuit shows stable
current of the circuit (IB) is equal to 30 µA. characteristic and its rise and fall time is less than 78 ns and
10 ns, respectively.
Fig. 4 shows the dc transfer characteristics of the proposed
circuit where dotted and solid lines represent the input and Fig. 7 shows the frequency response of the proposed
output signal, respectively. As seen, the output can follow the circuit. The voltage gain is found to be 0.96 V/V, while the
input over a wide range when connected to 5 kΩ in parallel bandwidth of the circuit is 155 MHz (RL//CL=5 kΩ//10 pF).
with 100 pF load with good linearity. Figure 5 shows the Fig. 8 shows the output impedance and it is found to be 50 Ω
transient response of the circuit, when the input is a sinusoidal over the mid-band frequency. The total harmonic distortion
signal (0.3 Vpp, 100 kHz) and load is 5 kΩ in parallel with 100 (THD) for a sinusoidal input with 0.18 Vpp is 0.3% at 100 kHz.
pF. The output signal can trace the input signal over a wide The power dissipation of the circuit is 38 µW.
range.
 ACKNOWLEDGMENT
0.60
The authors would like to thank the Thailand Research
Fund (TRF) through the Royal Golden Jubilee Ph.D. Program
under the contract number PHD/0260/2552.
Voltage (V)

0.50

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This paper presents a low voltage class-AB voltage
follower. The circuit is designed based on the super source
follower. Quasi-floating gate and bulk-driven are employed for
the input transistor allowing the circuit to operate at low supply
voltage with good performance.