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FinalQuestion2 Soln

The document contains solutions to questions about cache memory organization, contents of a direct mapped cache after memory accesses, page table size calculation, minimum memory access time given TLB hit rate, page size and physical memory size calculation from virtual to physical address mapping, and contents of a two-entry TLB after two memory accesses.

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22 views

FinalQuestion2 Soln

The document contains solutions to questions about cache memory organization, contents of a direct mapped cache after memory accesses, page table size calculation, minimum memory access time given TLB hit rate, page size and physical memory size calculation from virtual to physical address mapping, and contents of a two-entry TLB after two memory accesses.

Uploaded by

Muhammad Zahid iqbal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CS224 Final Spring 2020

Question No. 2 Solution


1. Cache Memory (12 pts.) Consider a computer with byte-addressable physical (main) memory of size 0.5
GB. The word size is given as 32 bits. The cache memory organization is 2-way set-associative. The
cache memory size is 4 KB. The block size is given as 256 bits.

a. Show how the physical memory address is partitioned into fields for the cache access. Give the name and
bit length of each field.
Answer: 2^29 bytes memory, 4-byte words, 2^5 bytes blocks (256 bits= 256/8= 32 bytes). Therefore
byte offset-2, block offset-3. 4KB / (2 x 2^5 bytes) = 2^6 sets. Index/set – 6 bits. So,
Tag- 18
Index/set- 6
Block offset- 3
Byte offset- 2

b. Draw one line (set) of the cache memory in terms of its components. What is the total storage
required to implement one set in number of bits?
Answer: 2 ways - each with 1 bit V, 18 bits Tag, 256 bits actual data, in total 2 x 275 = 550 bits for
one set.

For the implementation of the cache memory do we need the following hardware components: equality
comparator, and gate, and or gates? If your answer is no: explain why. If your answer is yes: how many
of each component is needed. No need to draw a figure.
Answer: There will be 2 AND gates, 2 Comparators and 1 Or gate.

=======================================================================
2. Cache Memory (12 pts.) Consider a computer with physical (main) memory of size 4GB. The word size
is given as 32 bits. A direct mapped cache memory organization has a block size 1 word and has 4 sets.
All sets are initially empty. The memory accesses are done for the following memory locations:
0x23, 0x38, 0xA9.

a. Show the final contents of the cache memory. Clearly state the set numbers and their contents with field
names and values. Draw a table for illustration.

b. What is the number of hits?


Answer: Physical Memory Size 4 GB= 2^32: Tag – 28, Index-2, Byte offset-2,
0x23: 0010 0011 – set 00
0x38: 0011 1000 – set 10
0xA9:1010 1001 – set 10
Set V Tag Data
00 1 0x2 M[0x20-0x23]
01 0 - -
10 1 0xA M[0xA8-0xAB]
11 0 - -
b. What is the number of hits?

Answer: 0
=======================================================================
1
3. Virtual Memory (15 pts.) Consider a VM environment with VM size: 1 GB, page size: 4 KB, and
physical memory size: 128 MB.

a. What is the size of one row of the page table in number of bits?
Answer: Page offset- 12 bits, VPN – 18 bits, PPN – 15 bits.
Valid bit + PPN for each row, therefore 16 bits.

b. What is the total page table size in terms of number of bits? Please do the calculation as it is illustrated in
the textbook.
Answer: There are 2^18 virtual pages (rows) x 2^4 bits (for each row) = 2^22 bits.

c. This system has a TLB for address translation, the physical memory access time is 50 ns TLB access time
is 10 ns, the hit rate for TLB is 80%. What is the minimum memory access time?
Answer: Minimum access requires one TLB access and 1 memory access. That is 60ns.

=======================================================================
4. Virtual Memory (11 pts.) In a VM environment 4096 different virtual memory pages are mapped to one
physical memory page (in a textbook illustration, with complete detail, there would be 4096 different
virtual memory pages pointing to one single physical memory page). For this architecture consider the
following two VM accesses and the corresponding physical memory addresses obtained for them. (All
numbers are in hex.) As shown in the table the memory accesses are done for the VM locations first 0 40
A0 A0 and then 0 00 BA C0.

Virtual Physical
Memory Memory
Address Address
0 40 A0 A0 28 A0 A0
0 00 BA C0 00 BA C0

a. What is the page size?


Answer. One physical page is pointed by 4096 virtual pages: This implies that VPN field is 12 bit
(4096 = 2^12). In virtual memory addresses leftmost 3 hex digits indicate the virtual page number.
What remains is 4 hex digits or 16 bits.
Page size is 2^16= 64 KB.

b. What is the physical memory size?


Answer: 2^24= 16 MB.

c. This system has a two-entry TLB (Entry-0 and Entry-1). Give the contents of the TLB after performing
the above memory accesses. Answer:

Entry 1 Entry 0
V VPN PPN V VPN PPN
1 0x000 0x00 1 0x040 0x28
=======================================================================

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