Lecture 2:

CMOS Fabrication

Mark McDermott
Electrical and Computer Engineering
The University of Texas at Austin

VLSI-1 Class Notes

 Agenda

§ Last module:
– Introduction to the course
– How a transistor works
– CMOS transistors

§ This module:
– CMOS Fabrication

8/26/18 VLSI-1 Class Notes 2

 CMOS Fabrication

§ CMOS transistors are fabricated on silicon wafers

§ Lithography process has been the mainstream chip
manufacturing process
– Similar to a printing press
– See Chris Mack's page for a nice litho tutorial
§ On each step, different materials are deposited or etched
§ Easiest to understand by viewing both top and cross-section of
wafer in a simplified manufacturing process

8/26/18 VLSI-1 Class Notes 3

 Inverter Cross-section

§ Typically use p-type substrate for nMOS transistors

§ Requires n-well for body of pMOS transistors

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

8/26/18 VLSI-1 Class Notes 4

 Well and Substrate Taps

§ Substrate must be tied to GND, n-well to VDD

§ Metal to lightly-doped semiconductor forms poor connection
called Schottky Diode
§ Use heavily doped well and substrate contacts / taps

A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

8/26/18 VLSI-1 Class Notes 5

 Inverter Mask Set

§ Transistors and wires are defined by masks

§ Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

8/26/18 VLSI-1 Class Notes 6

 Detailed Mask Views
Six masks to build simple inverter

N-well
n well

Polysilicon Polysilicon

n+ diffusion
n+ Diffusion

p+ diffusion
p+ Diffusion

Contact
Contact

Metal
Metal

8/26/18 VLSI-1 Class Notes 7

 Fabrication Steps

§ Start with blank wafer

§ Build inverter from the bottom up
§ First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

8/26/18 VLSI-1 Class Notes 8

 Oxidation

§ Grow SiO2 on top of Si wafer

– 900℃ - 1200℃ with H2O or O2 in an oxidation furnace

SiO2

p substrate

8/26/18 VLSI-1 Class Notes 9

 Photoresist

§ Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate

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 Lithography

§ Expose photoresist through n-well mask

§ Strip off exposed photoresist

Photoresist
SiO2

p substrate

8/26/18 VLSI-1 Class Notes 11

 Etch

§ Etch oxide with hydrofluoric acid (HF)

– Seeps through skin and eats bone; nasty stuff!!!
§ Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

8/26/18 VLSI-1 Class Notes 12

 Strip Photoresist

§ Strip off remaining photoresist

– Old days we used a mixture of nitric and sulphuric acids called piranah etch
– Now we use a plasma etch which is much safer (and greener).
§ Necessary so resist doesn’t melt in the next step

SiO2

p substrate

8/26/18 VLSI-1 Class Notes 13

 n-Well

§ n-Well formed with diffusion or ion implant

§ Diffusion
– Place wafer in furnace with Arsine (AsH3) gas
– Heat until As atoms diffuse into exposed Si
§ Ion Implantation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si

SiO2

n well

8/26/18 VLSI-1 Class Notes 14

 Strip Oxide

§ Strip off the remaining oxide using HF

§ Back to bare wafer with n-well
§ Subsequent steps involve similar series of steps

n well
p substrate

8/26/18 VLSI-1 Class Notes 15

 Polysilicon

§ Grow/deposit very thin layer of gate oxide

– < 20 Å (6-7 atomic layers)
§ Chemical Vapor Deposition (CVD) of Si layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

Trend towards metal gates and rare earth (Hf, etc.) oxides
in nanometer-scale processes

8/26/18 VLSI-1 Class Notes 16

 Polysilicon Patterning

§ Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

8/26/18 VLSI-1 Class Notes 17

 Self-Aligned Process

§ Use oxide and masking to expose where n+ dopants should be

diffused or implanted
§ N-diffusion forms nMOS source, drain, and n-well contact

n well
p substrate

8/26/18 VLSI-1 Class Notes 18

 N-diffusion

§ Pattern oxide and form n+ regions

§ Self-aligned process - gate blocks diffusion
§ Polysilicon is better than metal for self-aligned gates because it
doesn
t melt during later processing

n+ Diffusion

n well
p substrate

8/26/18 VLSI-1 Class Notes 19

 N-diffusion, Cont
d

§ Historically dopants were diffused

§ Usually ion implantation today
§ But regions are still called diffusion

n+ n+ n+

n well
p substrate

8/26/18 VLSI-1 Class Notes 20

 N-diffusion, Cont
d

§ Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate

8/26/18 VLSI-1 Class Notes 21

 P-Diffusion

§ Similar set of steps form p+ diffusion regions for pMOS source

and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate

8/26/18 VLSI-1 Class Notes 22

 Contacts

§ Now we need to wire together the devices

§ Cover chip with thick field oxide
§ Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

8/26/18 VLSI-1 Class Notes 23

 Metallization

§ Sputter on aluminum over whole wafer

§ Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

8/26/18 VLSI-1 Class Notes 24

 Intel’s 2-Year Technology Cadence

•Source: Mark Bohr, Intel Corporation

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 MOBILITY IMPROVEMENT

•Source: Mark Bohr, Intel Corporation

8/26/18 VLSI-1 Class Notes 26

 •Strained silicon increases electron/hole mobility.

•Source: Mark Bohr, Intel Corporation

8/26/18 VLSI-1 Class Notes 27

 •Source: Mark Bohr, Intel Corporation

8/26/18 VLSI-1 Class Notes 28

 High-K, Metal Gate 45 nm CMOS (Intel)

•K. Mistry, et al., “A 45nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu
Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging”, Tech. Digest IEDM, Dec 2007.

8/26/18 VLSI-1 Class Notes 29

 High-K, Metal Gate 32 nm CMOS (Intel)

•P. Packan, et al., “High Performance 32nm Logic Technology Featuring 2nd Generation High-k + Metal Gate
Transistors”, Tech. Digest IEDM, Dec 2009.

8/26/18 VLSI-1 Class Notes •30

 90nm INTERCONNECT

8/26/18 VLSI-1 Class Notes 31

 65nm INTERCONNECT

8/26/18 VLSI-1 Class Notes 32

 45nm Interconnect

Loose pitch + thick metal

on upper layers:
High speed global wires
Low resistance power grid

Tight pitch on lower layers:

Maximum density for local
interconnects

8/26/18 VLSI-1 Class Notes 33

 32nm Interconnect

M8

M7

M6

M5

M4
M3
M2
M1

•C.-H. Jan, et al., “A 32nm SoC Platform Technology with 2nd Generation High-k/Metal Gate Transistors Optimized for
•Ultra Low Power, High Performance, and High Density Product Applications”, IEDM, Dec 2009.

8/26/18 VLSI-1 Class Notes 34

 22nm Interconnect

IDF 2012

8/26/18 VLSI-1 Class Notes 35

 FIN-FET Transistor Innovation

32 nm Planar Transistors 22 nm Tri-Gate Transistors

Gates Fins

Intel’s 22 nm technology introduces

revolutionary 3-D Tri-Gate transistors
(courtesy: Mark Bohr, Sr. Intel Fellow)
8/26/18 VLSI-1 Class Notes 36
 Traditional Planar Transistor

Gate

Drain
High-k
Dielectric
Source

Oxide

Silicon
Substrate

Traditional 2-D planar transistors form a conducting

channel on the silicon surface under the gate electrode

8/26/18 VLSI-1 Class Notes 37

 22 nm FIN-FET Transistor

Drain
Gate

Source

Oxide

Silicon
Substrate

3-D Tri-Gate transistors form conducting

channels on three sides of a vertical silicon fin

8/26/18 VLSI-1 Class Notes 38

 22 nm FIN-FET Transistor

Gate

Oxide

Silicon
Substrate

Tri-Gate transistors can connect together multiple fins for higher

drive current and higher performance

8/26/18 VLSI-1 Class Notes 39