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Exercise 10 Solution

This document provides an exercise solution on convolutional encoding and decoding. It discusses a rate 1/3 convolutional encoder with a single shift register and three modulo-2 adders. The generator words are given as 101, 110, and 111. It asks the reader to draw a diagram of the encoder, produce a state table and trellis diagram, and use the trellis diagram to demonstrate decoding a received bit sequence. It also provides a second exercise involving a rate 1/2 convolutional code with generator words 1111 and 1101.

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Mujaahid Khan
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69 views4 pages

Exercise 10 Solution

This document provides an exercise solution on convolutional encoding and decoding. It discusses a rate 1/3 convolutional encoder with a single shift register and three modulo-2 adders. The generator words are given as 101, 110, and 111. It asks the reader to draw a diagram of the encoder, produce a state table and trellis diagram, and use the trellis diagram to demonstrate decoding a received bit sequence. It also provides a second exercise involving a rate 1/2 convolutional code with generator words 1111 and 1101.

Uploaded by

Mujaahid Khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Exercise solution: Lecture 10

Exercise:
A rate 1/3 convolutional encoder has a single shift register with two Flip Flops. There are three
modulo-2 adders and an output switch. The generator words are:

gl = 101, g2 = 110, g3 = 111.

 Draw a diagram of the encoder


 Produce a state table and trellis diagram for this code.
 Use your trellis diagram to demonstrate the decoding of the received bits
111 010 101 000.

Note: The only difference between implementing Viterbi decoding for this code and for rate ½
code is that all three bits on the branches are compared to the three input bits at each stage.
Solution:
Exercise:
A rate ½ convolutional code has the generator words 1111 and 1101.

 Draw a diagram of the encoder.


 Construct a state table and trellis diagram (four input bits long).
 Determine the output sequence for the four input bits 1011 and show this on
your trellis diagram.

Solution:

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