TS5A63157 12 - SPDT Analog Switch 5-V/3.3-V Single-Channel 2:1 Multiplexer/demultiplexer
TS5A63157 12 - SPDT Analog Switch 5-V/3.3-V Single-Channel 2:1 Multiplexer/demultiplexer
TS5A63157
2 Applications
• Sample-and-Hold Circuits
• Battery-Powered Equipment
• Audio and Video Signal Routing
• Communication Circuits
Block Diagram
TS5A63157
NO
COM
NC
IN
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS5A63157
Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ....................................... 21
2 Applications ........................................................... 1 8.3 Feature Description................................................. 21
3 Description ............................................................. 1 8.4 Device Functional Modes........................................ 21
4 Revision History..................................................... 2 9 Application and Implementation ........................ 22
9.1 Application Information............................................ 22
5 Pin Configuration and Functions ......................... 3
9.2 Typical Application ................................................. 22
6 Specifications......................................................... 4
6.1 Absolute Minimum and Maximum Ratings .............. 4 10 Power Supply Recommendations ..................... 23
6.2 ESD Ratings.............................................................. 4 11 Layout................................................................... 23
6.3 Recommended Operating Conditions....................... 4 11.1 Layout Guidelines ................................................. 23
6.4 Thermal Information .................................................. 4 11.2 Layout Example .................................................... 23
6.5 Electrical Characteristics for 5-V Supply................... 5 12 Device and Documentation Support ................. 24
6.6 Electrical Characteristics for 3.3-V Supply................ 7 12.1 Receiving Notification of Documentation Updates 24
6.7 Electrical Characteristics for 2.5-V Supply................ 9 12.2 Community Resources.......................................... 24
6.8 Electrical Characteristics for 1.8-V Supply.............. 11 12.3 Trademarks ........................................................... 24
6.9 Typical Characteristics ............................................ 13 12.4 Electrostatic Discharge Caution ............................ 24
7 Parameter Measurement Information ................ 15 12.5 Glossary ................................................................ 24
8 Detailed Description ............................................ 21 13 Mechanical, Packaging, and Orderable
8.1 Overview ................................................................. 21
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added Device Information table, ESD Ratings table, Recommended Operating Conditions table, Thermal
Information table, Feature Description section, Device Functional Modes, Application and Implementation section,
Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
• Deleted the YEP or YZP package option .............................................................................................................................. 3
• Deleted 2 table notes from the Absolute Minimum and Maximum Ratings : "The input and output voltage ratings..."
and "This value is limited to 5.5 V maximum." ...................................................................................................................... 4
NO 1 6 IN
GND 2 5 V+
NC 3 4 CO M
No t to scale
Pin Functions
PIN
DESCRIPTION
NAME NO.
NO 1 Normally open
GND 2 Digital ground
NC 3 Normally closed
COM 4 Common
V+ 5 Power supply
IN 6 Digital control. Logic H = COM to NO, Logic = L COM to NC
6 Specifications
6.1 Absolute Minimum and Maximum Ratings (1) (2)
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
60 12
85°C
50 10
25°C
40 8
ron (Ω)
ron (W)
–40°C
30 6
V+ = 1.8 V
20 4
V+ = 2.5 V
V+ = 3.3 V V = 5 V
10 + 2
0 0
0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCOM (V) VCOM (V)
Figure 1. ron vs VCOM Figure 2. ron vs VCOM (V+ = 3 V)
9 0.00500
85°C 0.00450 COM (ON)
8
tON/tOFF (ns)
V+ = 1.8 V
8 tOFF
0
6
4
−10
2
−20 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
Bias Voltage (V)
V+ (V)
Figure 5. Charge Injection (QC) vs VCOM
Figure 6. tON and tOFF vs Supply Voltage
2
1.0
1
0.5
0 0.0
−40 25 85 0 1 2 3 4 5 6
TA (°C) V+ (V)
Figure 7. tON and tOFF vs Temperature (V+ = 5 V) Figure 8. Logic-Level Threshold vs V+
0 0
−1 −20
Crosstalk
Attenuation (dB)
−2 −40
Gain (dB)
−3 −60
−5 −100
−6 −120
0.1 1 10 100 1000 0.1 1 10 100 1000
Frequency (MHz) Frequency (MHz)
Figure 9. Bandwidth (V+ = 3.3 V) Figure 10. OFF Isolation and Crosstalk (V+ = 3.3 V)
0.064 250
0.062 200
THD + (%)
0.060 150
ICC+ (nA)
0.058 100
0.056 50
0.054 0
10 100
1K 10K 100K −60 −40 −20 0 20 40 60 80 100
Frequency (Hz)
TA (°C)
Figure 11. Total Harmonic Distortion (THD) vs Frequency
Figure 12. Power-Supply Current vs Temperature (V+ = 5 V)
(V+ = 3.3 V)
V+
VNC NC
COM VCOM Chann el O N
+
VNO NO
V COM V NO or V NC
r on :
ICOM I COM
VI IN
+
VI V IH or V IL
GND
V+
VNC NC
COM VCOM
+
+ OFF-State L eakage Current
VNO NO
Chann el O FF
VI IN VI V IH or V IL
+
GND
V+
VNC NC
COM
+ VCOM
ON-State L eakage Current
VNO NO
Chann el O N
IN VI V IH or V IL
VI
+
GND
V+
VNC NC
Capacitance
Meter V BIAS V or GND
VBIAS VNO NO VI V or GND
VCOM COM
IN Capacitance i s measured at NC,
NO, COM, and IN inp uts during
VI
ON and OFF conditions.
GND
V+
2uV
RL S1
Ope n
NC or NO
VCOM GND
CL RL
COM NC or NO
CL RL
IN
VI
Log ic
Input (1)
GND V+
Log ic In put
50 % 50 %
(VIN)
0V
tPZL tPLZ
Switch Ou tpu t
(VNC or VNO ) VOH
S1 at 2 x V + 50 % VOL + 0.3 V
VOL
tPZH tPHZ
VOH
Switch Ou tpu t 50 % VOH ± 0.3 V
(VNC or VNO ) 0V
S1 at G ND
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns,
tf < 5 ns.
V+
VTR
VNC or VNO
RL
NC or NO
Switch VCOM
Input NC or NO
COM
RL CL
IN
VI
GND
Switch Input a nd Output for Un dershoot Test
5.5 V
Switch Input 90 % 90 %
VNC or VNO 2 ns 2 ns
(Ope n S ocket) 10 % 10 %
-2 V
20 ns
20 ns
Switch Input 5.5 V
VNC or VNO
(Ope n S ocket) 90 % 90 %
2 ns 2 ns
10 % 10 %
-2 V
Switch Ou tpu t
VOL + 0.3
(VOUTO)
VOL
V+
NC or NO
CL(2) RL Switch 90 % 90 %
Output
(VCOM)
IN tBBM
VI
Log ic
VNC or VNO = V+/2
Input (1)
GND RL = 50 Ÿ
CL = 35 pF
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns,
tf < 5 ns.
(2) CL includes probe and jig capacitance.
V+
Networ k Anal yzer
50 VNC NC
COM VCOM Chann el O N: NC to COM
Sou rce VI = V+ or GND
Sign al NO
V+
Networ k Anal yzer
DC Bia s = 350 mV
V+
Log ic VIH
RGEN Input
NC or NO OFF ON OFF
(VI) VIL
COM VCOM
VGEN NC or NO
CL(2) ûVCOM
VCOM
VI IN
VGEN = 0 to V +
Log ic
RGEN = 0
Input(1)
GND CL = 0.1 nF
QC = CL × ûVCOM
VI = VIH or VIL
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns,
tf < 5 ns.
(2) CL includes probe and jig capacitance.
V+/2
V+
Aud io A nalyze r
RL
NO
Sou rce
Sign al
NC CL(1)
600
600 Ÿ
VI IN
GND
600 Ÿ
8 Detailed Description
8.1 Overview
The TS5A63157 is a single-pole, double-throw (SPDT) analog switch designed to operate from 1.65 V to 5.5 V.
This device can handle both digital and analog signals. Signals up to V+ (peak) can be transmitted in either
direction.
TS5A63157
NO
COM
NC
IN
8.3.3 Break-before-make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
V+
IN NO
MCU or To/From
System Logic System
COM NC
GND
7
6
25°C
ron (Ω)
5
4 –40°C
3
2
1
0
0 1 2 3 4 5
VCOM (V)
11 Layout
1W min.
W
Figure 27. Trace Example
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TS5A63157DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (JBEF, JBER)
TS5A63157DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 JBEF
TS5A63157DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (J75, J7F, J7R)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jul-2020
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jul-2020
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA
1
6
2X 0.95
3.05
2.75
1.9 5
2
4
3
0.50
6X
0.25
0.15
0.2 C A B (1.1) TYP
0.00
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2 5
2X (0.95)
3 4
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
4214840/B 03/2018
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2 5
2X(0.95)
3 4
(R0.05) TYP
(2.6)
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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