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CA Assignment2

This document outlines an assignment for a computer architecture course. It contains instructions for students to complete 5 questions testing their knowledge of multiplication and division algorithms from Chapter 3. Students are asked to show the step-by-step workings and contents of registers for octal and binary operations using shift-and-add approaches. The assignment is worth 5% of the course grade and must be submitted as a PDF by the due date.

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0% found this document useful (0 votes)
49 views

CA Assignment2

This document outlines an assignment for a computer architecture course. It contains instructions for students to complete 5 questions testing their knowledge of multiplication and division algorithms from Chapter 3. Students are asked to show the step-by-step workings and contents of registers for octal and binary operations using shift-and-add approaches. The assignment is worth 5% of the course grade and must be submitted as a PDF by the due date.

Uploaded by

Sam5127
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Habib University

Course: Computer Architecture Program: BS CS


Faculty: Taj Muhammad Khan Course Code: CS330
Examination: Assignment-2 Due Date: 17 April 2020
Total Marks: 50

Name: Salman Muhammad Younus ID: 04351

Objective: This assignment is to practice the knowledge you’ve gained in Chapter 3.

Instructions: Please follow below instructions. Failure to do so would result in deductions of marks.

1. Fill in your name and ID.


2. This assignment comprises 5% of your grade for this course.
3. Submit a PDF (containing all answers).
4. Rubric: Q1-4 10 marks each, Submission(PDF etc)=10 marks
5. No marks if not submitted on LMS.
6. You may be called for a viva to explain part or all of your submission.
Question 1 (10 marks) :
Using a table similar to that shown in Figure 3.6, calculate the product of the octal unsigned 6-bit integers 62 and
12 using the hardware described in Figure 3.3. You should show the contents of each register on each step.

Iteration Step Multiplier Multiplicand Product


0 Initial Values 0011 0010 0000 0000 0000 1010 0000 0000 0000 0000
1 1: 0 => No 0011 0010 0000 0000 0000 1010 0000 0000 0000 0000
operation
2: Shift left 0011 0010 0000 0000 0001 0100 0000 0000 0000 0000
multiplicand
3: Shift right 0001 1001 0000 0000 0001 0100 0000 0000 0000 0000
multiplier
2 1: 1 => Prod = 0001 1001 0000 0000 0001 0100 0000 0000 0001 0100
Prod + Mcand
2: Shift left 0001 1001 0000 0000 0010 1000 0000 0000 0001 0100
multiplicand
3: Shift right 0000 1100 0000 0000 0010 1000 0000 0000 0001 0100
multiplier
3 1: 0 => No 0000 1100 0000 0000 0010 1000 0000 0000 0001 0100
operation
2: Shift left 0000 1100 0000 0000 0101 0000 0000 0000 0001 0100
multiplicand
3: Shift right 0000 0110 0000 0000 0101 0000 0000 0000 0001 0100
multiplier
4 1: 0 => No 0000 0110 0000 0000 0101 0000 0000 0000 0001 0100
operation
2: Shift left 0000 0110 0000 0000 1010 0000 0000 0000 0001 0100
multiplicand
3: Shift right 0000 0011 0000 0000 1010 0000 0000 0000 0001 0100
multiplier
5 1: 1 => Prod = 0000 0011 0000 0000 1010 0000 0000 0000 1011 0100
Prod + Mcand
2: Shift left 0000 0011 0000 0001 0100 0000 0000 0000 1011 0100
multiplicand
3: Shift right 0000 0001 0000 0001 0100 0000 0000 0000 1011 0100
multiplier
6 1: 1 => Prod = 0000 0001 0000 0001 0100 0000 0000 0001 1111 0100
Prod + Mcand
2: Shift left 0000 0001 0000 0010 1000 0000 0000 0001 1111 0100
multiplicand
3: Shift right 0000 0000 0000 0010 1000 0000 0000 0001 1111 0100
multiplier
7 1: 0 => No 0000 0000 0000 0010 1000 0000 0000 0001 1111 0100
operation
2: Shift left 0000 0000 0000 0101 0000 0000 0000 0001 1111 0100
multiplicand
3: Shift right 0000 0000 0000 0101 0000 0000 0000 0001 1111 0100
multiplier
Iteration Step Multiplier Multiplicand Product
8 1: 0 => No 0000 0000 0000 0101 0000 0000 0000 0001 1111 0100
operation
2: Shift left 0000 0000 0000 1010 0000 0000 0000 0001 1111 0100
multiplicand
3: Shift right 0000 0000 0000 1010 0000 0000 0000 0001 1111 0100
multiplier

Question 2 (10 marks) :


Calculate the time necessary to perform a multiply using the approach given in Figures 3.3 and 3.4 if an integer is
8 bits wide and each step of the operation takes four time units. Assume that in step 1a an addition is always
performed—either the multiplicand will be added, or a zero will be. Also assume that the registers have already
been initialized (you are just counting how long it takes to do the multiplication loop itself). If this is being done
in hardware, the shifts of the multiplicand and multiplier can be done simultaneously. If this is being done in
software, they will have to be done one after the other. Solve for each case.

Time units taken by each step = 4


Total repetitions for an 8-bit integer = 8

Hardware:
Total steps in one repetition = 2 (i.e addition and shifting of registers)

Total Time units = 4*8*2 = 64

Software:
Total steps in one repetition = 3 (i.e addition, shifting of multiplicand and shifting of multiplier)

Total Time units = 4*8*3 = 96


Question 3 (10 marks) :
As discussed in the text, one possible performance enhancement is to do a shift and add instead of an actual
multiplication. Since 9 × 6, for example, can be written (2 × 2 × 2 + 1) × 6, we can calculate 9 × 6 by
shifting 6 to the left three times and then adding 6 to that result. Show the best way to calculate 0x33 × 0x55
using shifts and adds/subtracts. Assume both inputs are 8-bit unsigned integers.

0x33 = (51)10
0x55 = (85)10

(2 ×2 ×2 ×2 ×2 + 19) × 85

(2 ×2 ×2 ×2 ×2 + (2 ×2 ×2 ×2 + 3)) × 85

(2 ×2 ×2 ×2 ×2 + (2 ×2 ×2 ×2 + (2+1))) × 85

(25 + 24 + 2 + 1) × 85

(25 * 85) + (24 * 85) + (2 * 85) + (1 * 85)

As a result, the best way to calculate it would be summing the following values:
• Left shift 85 five times
• Left shift 85 four times
• Left shift 85 one time
• 85
Question 4 (10 marks) :
Using a table similar to that shown in Figure 3.10, calculate 74 divided by 21 using the hardware described in
Figure 3.8. You should show the contents of each register on each step. Assume both inputs are unsigned 6-bit
integers.

Iteration Step Quotient Divisor Remainder


0 Initial Values 0000 0000 0001 0001 0000 0000 0000 0000 0011 1100
1 1: Rem = Rem - 0000 0000 0001 0001 0000 0000 1110 1111 0011 1100
Div
2: Rem < 0 => 0000 0000 0001 0001 0000 0000 0000 0000 0011 1100
+Div, SLL Q, Q0 =
0
3: Shift Divisor 0000 0000 0000 1000 1000 0000 0000 0000 0011 1100
right
2 1: Rem = Rem - 0000 0000 0000 1000 1000 0000 1111 0111 1011 1100
Div
2: Rem < 0 => 0000 0000 0000 1000 1000 0000 0000 0000 0011 1100
+Div, SLL Q, Q0 =
0
3: Shift Divisor 0000 0000 0000 0100 0100 0000 0000 0000 0011 1100
right
3 1: Rem = Rem - 0000 0000 0000 0100 0100 0000 1111 1011 1111 1100
Div
2: Rem < 0 => 0000 0000 0000 0100 0100 0000 0000 0000 0011 1100
+Div, SLL Q, Q0 =
0
3: Shift Divisor 0000 0000 0000 0010 0010 0000 0000 0000 0011 1100
right
4 1: Rem = Rem - 0000 0000 0000 0010 0010 0000 1111 1110 0001 1100
Div
2: Rem < 0 => 0000 0000 0000 0010 0010 0000 0000 0000 0011 1100
+Div, SLL Q, Q0 =
0
3: Shift Divisor 0000 0000 0000 0001 0001 0000 0000 0000 0011 1100
right
5 1: Rem = Rem - 0000 0000 0000 0001 0001 0000 1111 1111 0010 1100
Div
2: Rem < 0 => 0000 0000 0000 0001 0001 0000 0000 0000 0011 1100
+Div, SLL Q, Q0 =
0
3: Shift Divisor 0000 0000 0000 0000 1000 1000 0000 0000 0011 1100
right
6 1: Rem = Rem - 0000 0000 0000 0000 1000 1000 1111 1111 1011 0100
Div
2: Rem < 0 => 0000 0000 0000 0000 1000 1000 0000 0000 0011 1100
+Div, SLL Q, Q0 =
0
3: Shift Divisor 0000 0000 0000 0000 0100 0100 0000 0000 0011 1100
right
Iteration Step Quotient Divisor Remainder
7 1: Rem = Rem - 0000 0000 0000 0000 0100 0100 1111 1111 1111 1000
Div
2: Rem < 0 => 0000 0000 0000 0000 0100 0100 0000 0000 0011 1100
+Div, SLL Q, Q0 =
0
3: Shift Divisor 0000 0000 0000 0000 0010 0010 0000 0000 0011 1100
right
8 1: Rem = Rem - 0000 0000 0000 0000 0010 0010 0000 0000 0001 1010
Div
2: Rem >= 0 => 0000 0001 0000 0000 0010 0010 0000 0000 0001 1010
SLL Q, Q0 = 1
3: Shift Divisor 0000 0001 0000 0000 0001 0001 0000 0000 0001 1010
right
9 1: Rem = Rem - 0000 0001 0000 0000 0001 0001 0000 0000 0000 1001
Div
2: Rem >= 0 => 0000 0011 0000 0000 0001 0001 0000 0000 0000 1001
SLL Q, Q0 = 1
3: Shift Divisor 0000 0011 0000 0000 0000 1000 0000 0000 0000 1001
right

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